1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU HEVC codec driver
4 *
5 * Copyright (C) 2020 Safran Passenger Innovations LLC
6 */
7
8 #include <media/v4l2-hevc.h>
9
10 #include "hantro_hw.h"
11 #include "hantro_g2_regs.h"
12
prepare_tile_info_buffer(struct hantro_ctx * ctx)13 static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
14 {
15 struct hantro_dev *vpu = ctx->dev;
16 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
17 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
18 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
19 u16 *p = (u16 *)((u8 *)ctx->hevc_dec.tile_sizes.cpu);
20 unsigned int num_tile_rows = v4l2_hevc_pps_num_tile_rows(pps);
21 unsigned int num_tile_cols = v4l2_hevc_pps_num_tile_columns(pps);
22 unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
23 unsigned int max_log2_ctb_size, ctb_size;
24 bool tiles_enabled, uniform_spacing;
25 u32 no_chroma = 0;
26
27 tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
28 uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);
29
30 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled);
31
32 max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
33 sps->log2_diff_max_min_luma_coding_block_size;
34 pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
35 (1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;
36 pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)
37 >> max_log2_ctb_size;
38 ctb_size = 1 << max_log2_ctb_size;
39
40 vpu_debug(1, "Preparing tile sizes buffer for %dx%d CTBs (CTB size %d)\n",
41 pic_width_in_ctbs, pic_height_in_ctbs, ctb_size);
42
43 if (tiles_enabled) {
44 unsigned int i, j, h;
45
46 vpu_debug(1, "Tiles enabled! %dx%d\n", num_tile_cols, num_tile_rows);
47
48 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);
49 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);
50
51 /* write width + height for each tile in pic */
52 if (!uniform_spacing) {
53 u32 tmp_w = 0, tmp_h = 0;
54
55 for (i = 0; i < num_tile_rows; i++) {
56 if (i == num_tile_rows - 1)
57 h = pic_height_in_ctbs - tmp_h;
58 else
59 h = pps->row_height_minus1[i] + 1;
60 tmp_h += h;
61 if (i == 0 && h == 1 && ctb_size == 16)
62 no_chroma = 1;
63 for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {
64 tmp_w += pps->column_width_minus1[j] + 1;
65 *p++ = pps->column_width_minus1[j] + 1;
66 *p++ = h;
67 if (i == 0 && h == 1 && ctb_size == 16)
68 no_chroma = 1;
69 }
70 /* last column */
71 *p++ = pic_width_in_ctbs - tmp_w;
72 *p++ = h;
73 }
74 } else { /* uniform spacing */
75 u32 tmp, prev_h, prev_w;
76
77 for (i = 0, prev_h = 0; i < num_tile_rows; i++) {
78 tmp = (i + 1) * pic_height_in_ctbs / num_tile_rows;
79 h = tmp - prev_h;
80 prev_h = tmp;
81 if (i == 0 && h == 1 && ctb_size == 16)
82 no_chroma = 1;
83 for (j = 0, prev_w = 0; j < num_tile_cols; j++) {
84 tmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;
85 *p++ = tmp - prev_w;
86 *p++ = h;
87 if (j == 0 &&
88 (pps->column_width_minus1[0] + 1) == 1 &&
89 ctb_size == 16)
90 no_chroma = 1;
91 prev_w = tmp;
92 }
93 }
94 }
95 } else {
96 hantro_reg_write(vpu, &g2_num_tile_rows, 1);
97 hantro_reg_write(vpu, &g2_num_tile_cols, 1);
98
99 /* There's one tile, with dimensions equal to pic size. */
100 p[0] = pic_width_in_ctbs;
101 p[1] = pic_height_in_ctbs;
102 }
103
104 if (no_chroma)
105 vpu_debug(1, "%s: no chroma!\n", __func__);
106 }
107
compute_header_skip_length(struct hantro_ctx * ctx)108 static int compute_header_skip_length(struct hantro_ctx *ctx)
109 {
110 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
111 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
112 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
113 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
114 int skip = 0;
115
116 if (pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT)
117 /* size of pic_output_flag */
118 skip++;
119
120 if (sps->flags & V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE)
121 /* size of pic_order_cnt_lsb */
122 skip += 2;
123
124 if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
125 /* size of pic_order_cnt_lsb */
126 skip += sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
127
128 /* size of short_term_ref_pic_set_sps_flag */
129 skip++;
130
131 if (decode_params->short_term_ref_pic_set_size)
132 /* size of st_ref_pic_set( num_short_term_ref_pic_sets ) */
133 skip += decode_params->short_term_ref_pic_set_size;
134 else if (sps->num_short_term_ref_pic_sets > 1)
135 skip += fls(sps->num_short_term_ref_pic_sets - 1);
136
137 skip += decode_params->long_term_ref_pic_set_size;
138 }
139
140 return skip;
141 }
142
set_params(struct hantro_ctx * ctx)143 static void set_params(struct hantro_ctx *ctx)
144 {
145 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
146 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
147 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
148 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
149 struct hantro_dev *vpu = ctx->dev;
150 u32 min_log2_cb_size, max_log2_ctb_size, min_cb_size, max_ctb_size;
151 u32 pic_width_in_min_cbs, pic_height_in_min_cbs;
152 u32 pic_width_aligned, pic_height_aligned;
153 u32 partial_ctb_x, partial_ctb_y;
154
155 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);
156 hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);
157
158 hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx));
159
160 min_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
161 max_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size;
162
163 hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);
164 hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);
165
166 min_cb_size = 1 << min_log2_cb_size;
167 max_ctb_size = 1 << max_log2_ctb_size;
168
169 pic_width_in_min_cbs = sps->pic_width_in_luma_samples / min_cb_size;
170 pic_height_in_min_cbs = sps->pic_height_in_luma_samples / min_cb_size;
171 pic_width_aligned = ALIGN(sps->pic_width_in_luma_samples, max_ctb_size);
172 pic_height_aligned = ALIGN(sps->pic_height_in_luma_samples, max_ctb_size);
173
174 partial_ctb_x = !!(sps->pic_width_in_luma_samples != pic_width_aligned);
175 partial_ctb_y = !!(sps->pic_height_in_luma_samples != pic_height_aligned);
176
177 hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);
178 hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);
179
180 hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);
181 hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);
182
183 hantro_reg_write(vpu, &g2_pic_width_4x4,
184 (pic_width_in_min_cbs * min_cb_size) / 4);
185 hantro_reg_write(vpu, &g2_pic_height_4x4,
186 (pic_height_in_min_cbs * min_cb_size) / 4);
187
188 hantro_reg_write(vpu, &hevc_max_inter_hierdepth,
189 sps->max_transform_hierarchy_depth_inter);
190 hantro_reg_write(vpu, &hevc_max_intra_hierdepth,
191 sps->max_transform_hierarchy_depth_intra);
192 hantro_reg_write(vpu, &hevc_min_trb_size,
193 sps->log2_min_luma_transform_block_size_minus2 + 2);
194 hantro_reg_write(vpu, &hevc_max_trb_size,
195 sps->log2_min_luma_transform_block_size_minus2 + 2 +
196 sps->log2_diff_max_min_luma_transform_block_size);
197
198 hantro_reg_write(vpu, &g2_tempor_mvp_e,
199 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) &&
200 !(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC));
201 hantro_reg_write(vpu, &g2_strong_smooth_e,
202 !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));
203 hantro_reg_write(vpu, &g2_asym_pred_e,
204 !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
205 hantro_reg_write(vpu, &g2_sao_e,
206 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
207 hantro_reg_write(vpu, &g2_sign_data_hide,
208 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));
209
210 if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {
211 hantro_reg_write(vpu, &g2_cu_qpd_e, 1);
212 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);
213 } else {
214 hantro_reg_write(vpu, &g2_cu_qpd_e, 0);
215 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
216 }
217
218 hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
219 hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
220
221 hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
222 hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
223 hantro_reg_write(vpu, &g2_slice_hdr_ext_e,
224 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));
225 hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);
226 hantro_reg_write(vpu, &g2_slice_chqp_present,
227 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));
228 hantro_reg_write(vpu, &g2_weight_bipr_idc,
229 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));
230 hantro_reg_write(vpu, &g2_transq_bypass,
231 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));
232 hantro_reg_write(vpu, &g2_list_mod_e,
233 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));
234 hantro_reg_write(vpu, &g2_entropy_sync_e,
235 !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));
236 hantro_reg_write(vpu, &g2_cabac_init_present,
237 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
238 hantro_reg_write(vpu, &g2_idr_pic_e,
239 !!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC));
240 hantro_reg_write(vpu, &hevc_parallel_merge,
241 pps->log2_parallel_merge_level_minus2 + 2);
242 hantro_reg_write(vpu, &g2_pcm_filt_d,
243 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
244 hantro_reg_write(vpu, &g2_pcm_e,
245 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED));
246 if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
247 hantro_reg_write(vpu, &g2_max_pcm_size,
248 sps->log2_diff_max_min_pcm_luma_coding_block_size +
249 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
250 hantro_reg_write(vpu, &g2_min_pcm_size,
251 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
252 hantro_reg_write(vpu, &g2_bit_depth_pcm_y,
253 sps->pcm_sample_bit_depth_luma_minus1 + 1);
254 hantro_reg_write(vpu, &g2_bit_depth_pcm_c,
255 sps->pcm_sample_bit_depth_chroma_minus1 + 1);
256 } else {
257 hantro_reg_write(vpu, &g2_max_pcm_size, 0);
258 hantro_reg_write(vpu, &g2_min_pcm_size, 0);
259 hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);
260 hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);
261 }
262
263 hantro_reg_write(vpu, &g2_start_code_e, 1);
264 hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);
265 hantro_reg_write(vpu, &g2_weight_pred_e,
266 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));
267 hantro_reg_write(vpu, &g2_cabac_init_present,
268 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
269 hantro_reg_write(vpu, &g2_const_intra_e,
270 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));
271 hantro_reg_write(vpu, &g2_transform_skip,
272 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));
273 hantro_reg_write(vpu, &g2_out_filtering_dis,
274 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));
275 hantro_reg_write(vpu, &g2_filt_ctrl_pres,
276 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));
277 hantro_reg_write(vpu, &g2_dependent_slice,
278 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));
279 hantro_reg_write(vpu, &g2_filter_override,
280 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));
281 hantro_reg_write(vpu, &g2_refidx0_active,
282 pps->num_ref_idx_l0_default_active_minus1 + 1);
283 hantro_reg_write(vpu, &g2_refidx1_active,
284 pps->num_ref_idx_l1_default_active_minus1 + 1);
285 hantro_reg_write(vpu, &g2_apf_threshold, 8);
286 }
287
get_dpb_index(const struct v4l2_ctrl_hevc_decode_params * decode_params,const u32 index)288 static u32 get_dpb_index(const struct v4l2_ctrl_hevc_decode_params *decode_params,
289 const u32 index)
290 {
291 if (index > decode_params->num_active_dpb_entries)
292 return 0;
293
294 return index;
295 }
296
set_ref_pic_list(struct hantro_ctx * ctx)297 static void set_ref_pic_list(struct hantro_ctx *ctx)
298 {
299 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
300 struct hantro_dev *vpu = ctx->dev;
301 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
302 u32 list0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
303 u32 list1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
304 static const struct hantro_reg ref_pic_regs0[] = {
305 hevc_rlist_f0,
306 hevc_rlist_f1,
307 hevc_rlist_f2,
308 hevc_rlist_f3,
309 hevc_rlist_f4,
310 hevc_rlist_f5,
311 hevc_rlist_f6,
312 hevc_rlist_f7,
313 hevc_rlist_f8,
314 hevc_rlist_f9,
315 hevc_rlist_f10,
316 hevc_rlist_f11,
317 hevc_rlist_f12,
318 hevc_rlist_f13,
319 hevc_rlist_f14,
320 hevc_rlist_f15,
321 };
322 static const struct hantro_reg ref_pic_regs1[] = {
323 hevc_rlist_b0,
324 hevc_rlist_b1,
325 hevc_rlist_b2,
326 hevc_rlist_b3,
327 hevc_rlist_b4,
328 hevc_rlist_b5,
329 hevc_rlist_b6,
330 hevc_rlist_b7,
331 hevc_rlist_b8,
332 hevc_rlist_b9,
333 hevc_rlist_b10,
334 hevc_rlist_b11,
335 hevc_rlist_b12,
336 hevc_rlist_b13,
337 hevc_rlist_b14,
338 hevc_rlist_b15,
339 };
340 unsigned int i, j;
341
342 /* List 0 contains: short term before, short term after and long term */
343 j = 0;
344 for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list0); i++)
345 list0[j++] = decode_params->poc_st_curr_before[i];
346 for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list0); i++)
347 list0[j++] = decode_params->poc_st_curr_after[i];
348 for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list0); i++)
349 list0[j++] = decode_params->poc_lt_curr[i];
350
351 /* Fill the list, copying over and over */
352 i = 0;
353 while (j < ARRAY_SIZE(list0))
354 list0[j++] = list0[i++];
355
356 j = 0;
357 for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list1); i++)
358 list1[j++] = decode_params->poc_st_curr_after[i];
359 for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list1); i++)
360 list1[j++] = decode_params->poc_st_curr_before[i];
361 for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list1); i++)
362 list1[j++] = decode_params->poc_lt_curr[i];
363
364 i = 0;
365 while (j < ARRAY_SIZE(list1))
366 list1[j++] = list1[i++];
367
368 for (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
369 hantro_reg_write(vpu, &ref_pic_regs0[i],
370 get_dpb_index(decode_params, list0[i]));
371 hantro_reg_write(vpu, &ref_pic_regs1[i],
372 get_dpb_index(decode_params, list1[i]));
373 }
374 }
375
set_ref(struct hantro_ctx * ctx)376 static int set_ref(struct hantro_ctx *ctx)
377 {
378 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
379 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
380 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
381 const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
382 dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
383 dma_addr_t compress_luma_addr, compress_chroma_addr = 0;
384 struct hantro_dev *vpu = ctx->dev;
385 struct vb2_v4l2_buffer *vb2_dst;
386 struct hantro_decoded_buffer *dst;
387 size_t cr_offset = hantro_g2_chroma_offset(ctx);
388 size_t mv_offset = hantro_g2_motion_vectors_offset(ctx);
389 size_t compress_luma_offset = hantro_g2_luma_compress_offset(ctx);
390 size_t compress_chroma_offset = hantro_g2_chroma_compress_offset(ctx);
391 u32 max_ref_frames;
392 u16 dpb_longterm_e;
393 static const struct hantro_reg cur_poc[] = {
394 hevc_cur_poc_00,
395 hevc_cur_poc_01,
396 hevc_cur_poc_02,
397 hevc_cur_poc_03,
398 hevc_cur_poc_04,
399 hevc_cur_poc_05,
400 hevc_cur_poc_06,
401 hevc_cur_poc_07,
402 hevc_cur_poc_08,
403 hevc_cur_poc_09,
404 hevc_cur_poc_10,
405 hevc_cur_poc_11,
406 hevc_cur_poc_12,
407 hevc_cur_poc_13,
408 hevc_cur_poc_14,
409 hevc_cur_poc_15,
410 };
411 unsigned int i;
412
413 max_ref_frames = decode_params->num_poc_lt_curr +
414 decode_params->num_poc_st_curr_before +
415 decode_params->num_poc_st_curr_after;
416 /*
417 * Set max_ref_frames to non-zero to avoid HW hang when decoding
418 * badly marked I-frames.
419 */
420 max_ref_frames = max_ref_frames ? max_ref_frames : 1;
421 hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);
422 hantro_reg_write(vpu, &g2_filter_over_slices,
423 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));
424 hantro_reg_write(vpu, &g2_filter_over_tiles,
425 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
426
427 /*
428 * Write POC count diff from current pic.
429 */
430 for (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {
431 char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt_val;
432
433 hantro_reg_write(vpu, &cur_poc[i], poc_diff);
434 }
435
436 if (i < ARRAY_SIZE(cur_poc)) {
437 /*
438 * After the references, fill one entry pointing to itself,
439 * i.e. difference is zero.
440 */
441 hantro_reg_write(vpu, &cur_poc[i], 0);
442 i++;
443 }
444
445 /* Fill the rest with the current picture */
446 for (; i < ARRAY_SIZE(cur_poc); i++)
447 hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);
448
449 set_ref_pic_list(ctx);
450
451 /* We will only keep the reference pictures that are still used */
452 hantro_hevc_ref_init(ctx);
453
454 /* Set up addresses of DPB buffers */
455 dpb_longterm_e = 0;
456 for (i = 0; i < decode_params->num_active_dpb_entries &&
457 i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
458 luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt_val);
459 if (!luma_addr)
460 return -ENOMEM;
461
462 chroma_addr = luma_addr + cr_offset;
463 mv_addr = luma_addr + mv_offset;
464 compress_luma_addr = luma_addr + compress_luma_offset;
465 compress_chroma_addr = luma_addr + compress_chroma_offset;
466
467 if (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
468 dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
469
470 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
471 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
472 hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
473 hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), compress_luma_addr);
474 hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i), compress_chroma_addr);
475 }
476
477 vb2_dst = hantro_get_dst_buf(ctx);
478 dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
479 luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
480 if (!luma_addr)
481 return -ENOMEM;
482
483 if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))
484 return -EINVAL;
485
486 chroma_addr = luma_addr + cr_offset;
487 mv_addr = luma_addr + mv_offset;
488 compress_luma_addr = luma_addr + compress_luma_offset;
489 compress_chroma_addr = luma_addr + compress_chroma_offset;
490
491 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
492 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
493 hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
494 hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), compress_luma_addr);
495 hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i++), compress_chroma_addr);
496
497 hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
498 hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
499 hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
500 hantro_write_addr(vpu, G2_OUT_COMP_LUMA_ADDR, compress_luma_addr);
501 hantro_write_addr(vpu, G2_OUT_COMP_CHROMA_ADDR, compress_chroma_addr);
502
503 for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
504 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
505 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);
506 hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);
507 hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), 0);
508 hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i), 0);
509 }
510
511 hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
512
513 return 0;
514 }
515
set_buffers(struct hantro_ctx * ctx)516 static void set_buffers(struct hantro_ctx *ctx)
517 {
518 struct vb2_v4l2_buffer *src_buf;
519 struct hantro_dev *vpu = ctx->dev;
520 dma_addr_t src_dma;
521 u32 src_len, src_buf_len;
522
523 src_buf = hantro_get_src_buf(ctx);
524
525 /* Source (stream) buffer. */
526 src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
527 src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
528 src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
529
530 hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);
531 hantro_reg_write(vpu, &g2_stream_len, src_len);
532 hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
533 hantro_reg_write(vpu, &g2_strm_start_offset, 0);
534 hantro_reg_write(vpu, &g2_start_bit, 0);
535 hantro_reg_write(vpu, &g2_write_mvs_e, 1);
536
537 hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
538 hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
539 hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
540 hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);
541 }
542
prepare_scaling_list_buffer(struct hantro_ctx * ctx)543 static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
544 {
545 struct hantro_dev *vpu = ctx->dev;
546 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
547 const struct v4l2_ctrl_hevc_scaling_matrix *sc = ctrls->scaling;
548 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
549 u8 *p = ((u8 *)ctx->hevc_dec.scaling_lists.cpu);
550 unsigned int scaling_list_enabled;
551 unsigned int i, j, k;
552
553 scaling_list_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
554 hantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled);
555
556 if (!scaling_list_enabled)
557 return;
558
559 for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_16x16); i++)
560 *p++ = sc->scaling_list_dc_coef_16x16[i];
561
562 for (i = 0; i < ARRAY_SIZE(sc->scaling_list_dc_coef_32x32); i++)
563 *p++ = sc->scaling_list_dc_coef_32x32[i];
564
565 /* 128-bit boundary */
566 p += 8;
567
568 /* write scaling lists column by column */
569
570 for (i = 0; i < 6; i++)
571 for (j = 0; j < 4; j++)
572 for (k = 0; k < 4; k++)
573 *p++ = sc->scaling_list_4x4[i][4 * k + j];
574
575 for (i = 0; i < 6; i++)
576 for (j = 0; j < 8; j++)
577 for (k = 0; k < 8; k++)
578 *p++ = sc->scaling_list_8x8[i][8 * k + j];
579
580 for (i = 0; i < 6; i++)
581 for (j = 0; j < 8; j++)
582 for (k = 0; k < 8; k++)
583 *p++ = sc->scaling_list_16x16[i][8 * k + j];
584
585 for (i = 0; i < 2; i++)
586 for (j = 0; j < 8; j++)
587 for (k = 0; k < 8; k++)
588 *p++ = sc->scaling_list_32x32[i][8 * k + j];
589
590 hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
591 }
592
hantro_g2_hevc_dec_run(struct hantro_ctx * ctx)593 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
594 {
595 struct hantro_dev *vpu = ctx->dev;
596 int ret;
597
598 /* Prepare HEVC decoder context. */
599 ret = hantro_hevc_dec_prepare_run(ctx);
600 if (ret)
601 return ret;
602
603 /* Configure hardware registers. */
604 set_params(ctx);
605
606 /* set reference pictures */
607 ret = set_ref(ctx);
608 if (ret)
609 return ret;
610
611 set_buffers(ctx);
612 prepare_tile_info_buffer(ctx);
613
614 prepare_scaling_list_buffer(ctx);
615
616 hantro_end_prepare_run(ctx);
617
618 hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE);
619 hantro_reg_write(vpu, &g2_clk_gate_e, 1);
620
621 /* Don't disable output */
622 hantro_reg_write(vpu, &g2_out_dis, 0);
623
624 hantro_reg_write(vpu, &g2_ref_compress_bypass, !ctx->hevc_dec.use_compression);
625
626 /* Bus width and max burst */
627 hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);
628 hantro_reg_write(vpu, &g2_max_burst, 16);
629
630 /* Swap */
631 hantro_reg_write(vpu, &g2_strm_swap, 0xf);
632 hantro_reg_write(vpu, &g2_dirmv_swap, 0xf);
633 hantro_reg_write(vpu, &g2_compress_swap, 0xf);
634
635 /* Start decoding! */
636 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT);
637
638 return 0;
639 }
640