1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "debug.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "reg.h"
10
11 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = {
12 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE,
13 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE,
14 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE,
15 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE,
16 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE,
17 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE,
18 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE,
19 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE,
20 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE,
21 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE,
22 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE,
23 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE,
24 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE,
25 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE,
26 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE,
27 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE,
28 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE,
29 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE,
30 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE,
31 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE,
32 [RTW89_MAC_MEM_MLD_TBL] = MLD_TBL_BASE_ADDR_BE,
33 };
34
35 static const struct rtw89_port_reg rtw89_port_base_be = {
36 .port_cfg = R_BE_PORT_CFG_P0,
37 .tbtt_prohib = R_BE_TBTT_PROHIB_P0,
38 .bcn_area = R_BE_BCN_AREA_P0,
39 .bcn_early = R_BE_BCNERLYINT_CFG_P0,
40 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0,
41 .tbtt_agg = R_BE_TBTT_AGG_P0,
42 .bcn_space = R_BE_BCN_SPACE_CFG_P0,
43 .bcn_forcetx = R_BE_BCN_FORCETX_P0,
44 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0,
45 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0,
46 .dtim_ctrl = R_BE_DTIM_CTRL_P0,
47 .tbtt_shift = R_BE_TBTT_SHIFT_P0,
48 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0,
49 .tsftr_l = R_BE_TSFTR_LOW_P0,
50 .tsftr_h = R_BE_TSFTR_HIGH_P0,
51 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL,
52 .bss_color = R_BE_PTCL_BSS_COLOR_0,
53 .mbssid = R_BE_MBSSID_CTRL,
54 .mbssid_drop = R_BE_MBSSID_DROP_0,
55 .tsf_sync = R_BE_PORT_0_TSF_SYNC,
56 .ptcl_dbg = R_BE_PTCL_DBG,
57 .ptcl_dbg_info = R_BE_PTCL_DBG_INFO,
58 .bcn_drop_all = R_BE_BCN_DROP_ALL0,
59 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG,
60 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2,
61 R_BE_PORT_HGQ_WINDOW_CFG + 3},
62 };
63
rtw89_mac_check_mac_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)64 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx,
65 enum rtw89_mac_hwmod_sel sel)
66 {
67 if (sel == RTW89_DMAC_SEL &&
68 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags))
69 return 0;
70 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 &&
71 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags))
72 return 0;
73 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 &&
74 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags))
75 return 0;
76
77 return -EFAULT;
78 }
79
is_qta_poh(struct rtw89_dev * rtwdev)80 static bool is_qta_poh(struct rtw89_dev *rtwdev)
81 {
82 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
83 }
84
hfc_get_mix_info_be(struct rtw89_dev * rtwdev)85 static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
86 {
87 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
88 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
89 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
90 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
91 u32 val;
92
93 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
94 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK);
95 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK);
96
97 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3);
98 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK);
99 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK);
100 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2),
101 B_BE_PUB_AVAL_PG_MASK);
102 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1),
103 B_BE_WP_AVAL_PG_MASK);
104
105 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
106 param->en = !!(val & B_BE_HCI_FC_EN);
107 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN);
108 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK);
109 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK);
110 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK);
111 prec_cfg->wp_ch07_full_cond =
112 u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
113 prec_cfg->wp_ch811_full_cond =
114 u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
115
116 val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
117 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
118 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
119
120 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
121 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
122
123 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
124 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
125 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
126
127 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
128 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
129
130 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1);
131 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK);
132 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK);
133 }
134
hfc_h2c_cfg_be(struct rtw89_dev * rtwdev)135 static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev)
136 {
137 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
138 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
139 u32 val;
140
141 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
142 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
143 }
144
hfc_mix_cfg_be(struct rtw89_dev * rtwdev)145 static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev)
146 {
147 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
148 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
149 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
150 u32 val;
151
152 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
153 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
154 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
155
156 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
157 rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
158
159 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
160 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
161 rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
162
163 val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
164 param->mode, B_BE_HCI_FC_MODE_MASK);
165 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
166 B_BE_HCI_FC_WD_FULL_COND_MASK);
167 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
168 B_BE_HCI_FC_CH12_FULL_COND_MASK);
169 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
170 B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
171 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
172 B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
173 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
174 }
175
hfc_func_en_be(struct rtw89_dev * rtwdev,bool en,bool h2c_en)176 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
177 {
178 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
179 u32 val;
180
181 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
182 param->en = en;
183 param->h2c_en = h2c_en;
184 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN);
185 val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) :
186 (val & ~B_BE_HCI_FC_CH12_EN);
187 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
188 }
189
dle_func_en_be(struct rtw89_dev * rtwdev,bool enable)190 static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable)
191 {
192 if (enable)
193 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
194 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
195 else
196 rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN,
197 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
198 }
199
dle_clk_en_be(struct rtw89_dev * rtwdev,bool enable)200 static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable)
201 {
202 if (enable)
203 rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN,
204 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
205 else
206 rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN,
207 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
208 }
209
dle_mix_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)210 static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
211 {
212 const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg;
213 u32 bound;
214 u32 val;
215
216 wde_size_cfg = cfg->wde_size;
217 ple_size_cfg = cfg->ple_size;
218
219 val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG);
220
221 switch (wde_size_cfg->pge_size) {
222 default:
223 case RTW89_WDE_PG_64:
224 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
225 B_BE_WDE_PAGE_SEL_MASK);
226 break;
227 case RTW89_WDE_PG_128:
228 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
229 B_BE_WDE_PAGE_SEL_MASK);
230 break;
231 case RTW89_WDE_PG_256:
232 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
233 return -EINVAL;
234 }
235
236 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT;
237 val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK);
238 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num,
239 B_BE_WDE_FREE_PAGE_NUM_MASK);
240 rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val);
241
242 val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG);
243
244 switch (ple_size_cfg->pge_size) {
245 default:
246 case RTW89_PLE_PG_64:
247 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
248 return -EINVAL;
249 case RTW89_PLE_PG_128:
250 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
251 B_BE_PLE_PAGE_SEL_MASK);
252 break;
253 case RTW89_PLE_PG_256:
254 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
255 B_BE_PLE_PAGE_SEL_MASK);
256 break;
257 }
258
259 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT;
260 val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK);
261 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num,
262 B_BE_PLE_FREE_PAGE_NUM_MASK);
263 rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val);
264
265 return 0;
266 }
267
chk_dle_rdy_be(struct rtw89_dev * rtwdev,bool wde_or_ple)268 static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple)
269 {
270 u32 reg, mask;
271 u32 ini;
272
273 if (wde_or_ple) {
274 reg = R_AX_WDE_INI_STATUS;
275 mask = WDE_MGN_INI_RDY;
276 } else {
277 reg = R_AX_PLE_INI_STATUS;
278 mask = PLE_MGN_INI_RDY;
279 }
280
281 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1,
282 2000, false, rtwdev, reg);
283 }
284
285 #define INVALID_QT_WCPU U16_MAX
286 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
287 do { \
288 val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \
289 u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \
290 rtw89_write32(rtwdev, \
291 R_BE_ ## _module ## _QTA ## _idx ## _CFG, \
292 val); \
293 } while (0)
294 #define SET_QUOTA(_x, _module, _idx) \
295 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
296
wde_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)297 static void wde_quota_cfg_be(struct rtw89_dev *rtwdev,
298 const struct rtw89_wde_quota *min_cfg,
299 const struct rtw89_wde_quota *max_cfg,
300 u16 ext_wde_min_qt_wcpu)
301 {
302 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
303 ext_wde_min_qt_wcpu : min_cfg->wcpu;
304 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu);
305 u32 val;
306
307 SET_QUOTA(hif, WDE, 0);
308 SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1);
309 SET_QUOTA_VAL(0, 0, WDE, 2);
310 SET_QUOTA(pkt_in, WDE, 3);
311 SET_QUOTA(cpu_io, WDE, 4);
312 }
313
ple_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)314 static void ple_quota_cfg_be(struct rtw89_dev *rtwdev,
315 const struct rtw89_ple_quota *min_cfg,
316 const struct rtw89_ple_quota *max_cfg)
317 {
318 u32 val;
319
320 SET_QUOTA(cma0_tx, PLE, 0);
321 SET_QUOTA(cma1_tx, PLE, 1);
322 SET_QUOTA(c2h, PLE, 2);
323 SET_QUOTA(h2c, PLE, 3);
324 SET_QUOTA(wcpu, PLE, 4);
325 SET_QUOTA(mpdu_proc, PLE, 5);
326 SET_QUOTA(cma0_dma, PLE, 6);
327 SET_QUOTA(cma1_dma, PLE, 7);
328 SET_QUOTA(bb_rpt, PLE, 8);
329 SET_QUOTA(wd_rel, PLE, 9);
330 SET_QUOTA(cpu_io, PLE, 10);
331 SET_QUOTA(tx_rpt, PLE, 11);
332 SET_QUOTA(h2d, PLE, 12);
333 }
334
rtw89_mac_hci_func_en_be(struct rtw89_dev * rtwdev)335 static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
336 {
337 rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN |
338 B_BE_HCI_RXDMA_EN);
339 }
340
rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev * rtwdev)341 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
342 {
343 u32 val;
344
345 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
346
347 switch (rtwdev->hci.type) {
348 case RTW89_HCI_TYPE_PCIE:
349 val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU,
350 B_BE_DMA_MODE_MASK);
351 break;
352 case RTW89_HCI_TYPE_USB:
353 val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK);
354 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
355 break;
356 case RTW89_HCI_TYPE_SDIO:
357 val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK);
358 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
359 break;
360 default:
361 return;
362 }
363
364 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
365
366 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1,
367 B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 |
368 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
369 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
370 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 |
371 B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14);
372
373 rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
374 }
375
376 static
rtw89_mac_write_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)377 int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
378 {
379 u32 val32;
380 int ret;
381
382 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
383 u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) |
384 u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) |
385 u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) |
386 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
387 B_BE_WL_XTAL_SI_CMD_POLL;
388 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
389
390 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
391 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
392 if (ret) {
393 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
394 offset, val, mask);
395 return ret;
396 }
397
398 return 0;
399 }
400
401 static
rtw89_mac_read_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 * val)402 int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
403 {
404 u32 val32;
405 int ret;
406
407 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
408 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) |
409 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) |
410 u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) |
411 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
412 B_BE_WL_XTAL_SI_CMD_POLL;
413 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
414
415 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
416 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
417 if (ret) {
418 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
419 return ret;
420 }
421
422 *val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1);
423
424 return 0;
425 }
426
rtw89_mac_disable_cpu_be(struct rtw89_dev * rtwdev)427 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
428 {
429 u32 val32;
430
431 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
432
433 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
434 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
435 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
436
437 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
438 val32 &= B_BE_RUN_ENV_MASK;
439 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32);
440
441 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
442
443 rtw89_write32(rtwdev, R_BE_UDM0, 0);
444 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
445 rtw89_write32(rtwdev, R_BE_UDM2, 0);
446 }
447
set_cpu_en(struct rtw89_dev * rtwdev,bool include_bb)448 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb)
449 {
450 u32 set = B_BE_WLANCPU_FWDL_EN;
451
452 if (include_bb)
453 set |= B_BE_BBMCU0_FWDL_EN;
454
455 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set);
456 }
457
wcpu_on(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw)458 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
459 {
460 u32 val32;
461 int ret;
462
463 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H);
464 if (val32) {
465 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
466 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32);
467 }
468 val32 = rtw89_read32(rtwdev, R_BE_UDM1);
469 if (val32) {
470 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
471 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32);
472 }
473 val32 = rtw89_read32(rtwdev, R_BE_UDM2);
474 if (val32) {
475 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
476 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32);
477 }
478
479 rtw89_write32(rtwdev, R_BE_UDM1, 0);
480 rtw89_write32(rtwdev, R_BE_UDM2, 0);
481 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0);
482 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
483 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0);
484 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0);
485
486 val32 = rtw89_read32(rtwdev, R_BE_HISR0);
487 rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT);
488 rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32);
489
490 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN);
491 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5,
492 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN);
493 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL,
494 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET);
495
496 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason);
497 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
498 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
499 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
500
501 if (!dlfw) {
502 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
503 if (ret)
504 return ret;
505 }
506
507 return 0;
508 }
509
rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw,bool include_bb)510 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev,
511 u8 boot_reason, bool dlfw,
512 bool include_bb)
513 {
514 set_cpu_en(rtwdev, include_bb);
515
516 return wcpu_on(rtwdev, boot_reason, dlfw);
517 }
518
519 static const u8 fwdl_status_map[] = {
520 [0] = RTW89_FWDL_INITIAL_STATE,
521 [1] = RTW89_FWDL_FWDL_ONGOING,
522 [4] = RTW89_FWDL_CHECKSUM_FAIL,
523 [5] = RTW89_FWDL_SECURITY_FAIL,
524 [6] = RTW89_FWDL_SECURITY_FAIL,
525 [7] = RTW89_FWDL_CV_NOT_MATCH,
526 [8] = RTW89_FWDL_RSVD0,
527 [2] = RTW89_FWDL_WCPU_FWDL_RDY,
528 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY,
529 [9] = RTW89_FWDL_RSVD0,
530 };
531
fwdl_get_status_be(struct rtw89_dev * rtwdev,enum rtw89_fwdl_check_type type)532 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
533 {
534 bool check_pass = false;
535 u32 val32;
536 u8 st;
537
538 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
539
540 switch (type) {
541 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE:
542 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN);
543 break;
544 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE:
545 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN);
546 break;
547 case RTW89_FWDL_CHECK_BB0_FWDL_DONE:
548 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN);
549 break;
550 case RTW89_FWDL_CHECK_BB1_FWDL_DONE:
551 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN);
552 break;
553 default:
554 break;
555 }
556
557 if (check_pass)
558 return RTW89_FWDL_WCPU_FW_INIT_RDY;
559
560 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK);
561 if (st < ARRAY_SIZE(fwdl_status_map))
562 return fwdl_status_map[st];
563
564 return st;
565 }
566
rtw89_fwdl_check_path_ready_be(struct rtw89_dev * rtwdev,bool h2c_or_fwdl)567 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev,
568 bool h2c_or_fwdl)
569 {
570 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY;
571 u32 val;
572
573 return read_poll_timeout_atomic(rtw89_read32, val, val & check,
574 1, 1000000, false,
575 rtwdev, R_BE_WCPU_FW_CTRL);
576 }
577
dmac_func_en_be(struct rtw89_dev * rtwdev)578 static int dmac_func_en_be(struct rtw89_dev *rtwdev)
579 {
580 return 0;
581 }
582
cmac_func_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)583 static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
584 {
585 u32 reg;
586
587 if (mac_idx > RTW89_MAC_1)
588 return -EINVAL;
589
590 if (mac_idx == RTW89_MAC_0)
591 return 0;
592
593 if (en) {
594 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
595 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
596 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
597
598 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
599 rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET);
600
601 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
602 rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
603
604 set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
605 } else {
606 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
607 rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
608
609 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
610 rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET);
611
612 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
613 rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
614 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
615
616 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
617 }
618
619 return 0;
620 }
621
chip_func_en_be(struct rtw89_dev * rtwdev)622 static int chip_func_en_be(struct rtw89_dev *rtwdev)
623 {
624 return 0;
625 }
626
sys_init_be(struct rtw89_dev * rtwdev)627 static int sys_init_be(struct rtw89_dev *rtwdev)
628 {
629 int ret;
630
631 ret = dmac_func_en_be(rtwdev);
632 if (ret)
633 return ret;
634
635 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
636 if (ret)
637 return ret;
638
639 ret = chip_func_en_be(rtwdev);
640 if (ret)
641 return ret;
642
643 return ret;
644 }
645
sta_sch_init_be(struct rtw89_dev * rtwdev)646 static int sta_sch_init_be(struct rtw89_dev *rtwdev)
647 {
648 u32 p_val;
649 int ret;
650
651 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
652 if (ret)
653 return ret;
654
655 rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN);
656
657 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE,
658 1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL);
659 if (ret) {
660 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
661 return ret;
662 }
663
664 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT);
665 rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN);
666
667 return 0;
668 }
669
mpdu_proc_init_be(struct rtw89_dev * rtwdev)670 static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
671 {
672 u32 val32;
673 int ret;
674
675 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
676 if (ret)
677 return ret;
678
679 rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
680 rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
681
682 val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING);
683 val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN);
684 val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK;
685 rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32);
686
687 rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV);
688
689 val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0);
690 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK);
691 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK);
692 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK);
693 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK);
694 rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32);
695
696 return 0;
697 }
698
sec_eng_init_be(struct rtw89_dev * rtwdev)699 static int sec_eng_init_be(struct rtw89_dev *rtwdev)
700 {
701 u32 val32;
702 int ret;
703
704 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
705 if (ret)
706 return ret;
707
708 val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL);
709 val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP |
710 B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC |
711 B_BE_MC_DEC | B_BE_BC_DEC |
712 B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC |
713 B_BE_SEC_PRE_ENQUE_TX;
714 rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32);
715
716 rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC);
717
718 return 0;
719 }
720
txpktctrl_init_be(struct rtw89_dev * rtwdev)721 static int txpktctrl_init_be(struct rtw89_dev *rtwdev)
722 {
723 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
724 u32 val32;
725 int ret;
726
727 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg);
728 if (ret) {
729 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n",
730 DLE_RSVD_QT_MPDU_INFO, ret);
731 return ret;
732 }
733
734 val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG);
735 val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK);
736 val32 = u32_replace_bits(val32, MPDU_INFO_B1_OFST, B_BE_MPDUINFO_B1_BADDR_MASK);
737 val32 |= B_BE_MPDUINFO_FEN;
738 rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32);
739
740 return 0;
741 }
742
mlo_init_be(struct rtw89_dev * rtwdev)743 static int mlo_init_be(struct rtw89_dev *rtwdev)
744 {
745 u32 val32;
746 int ret;
747
748 val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
749
750 val32 |= B_BE_MLO_TABLE_REINIT;
751 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
752 val32 &= ~B_BE_MLO_TABLE_REINIT;
753 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
754
755 ret = read_poll_timeout_atomic(rtw89_read32, val32,
756 val32 & B_BE_MLO_TABLE_INIT_DONE,
757 1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL);
758 if (ret)
759 rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__);
760
761 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_MLO_HW_CHGLINK_EN);
762 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
763
764 return ret;
765 }
766
dmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)767 static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
768 {
769 int ret;
770
771 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
772 if (ret) {
773 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
774 return ret;
775 }
776
777 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode);
778 if (ret) {
779 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
780 return ret;
781 }
782
783 ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
784 if (ret) {
785 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
786 return ret;
787 }
788
789 ret = sta_sch_init_be(rtwdev);
790 if (ret) {
791 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
792 return ret;
793 }
794
795 ret = mpdu_proc_init_be(rtwdev);
796 if (ret) {
797 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
798 return ret;
799 }
800
801 ret = sec_eng_init_be(rtwdev);
802 if (ret) {
803 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
804 return ret;
805 }
806
807 ret = txpktctrl_init_be(rtwdev);
808 if (ret) {
809 rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret);
810 return ret;
811 }
812
813 ret = mlo_init_be(rtwdev);
814 if (ret) {
815 rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret);
816 return ret;
817 }
818
819 return ret;
820 }
821
scheduler_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)822 static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
823 {
824 u32 val32;
825 u32 reg;
826 int ret;
827
828 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
829 if (ret)
830 return ret;
831
832 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx);
833 val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 |
834 B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP |
835 B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV |
836 B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV;
837 rtw89_write32(rtwdev, reg, val32);
838
839 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx);
840 val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP |
841 B_BE_HE_SIFS_CHK_NO_GNT_WL;
842 rtw89_write32(rtwdev, reg, val32);
843
844 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx);
845 val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV;
846 rtw89_write32(rtwdev, reg, val32);
847
848 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx);
849 rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN);
850
851 if (is_qta_poh(rtwdev)) {
852 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx);
853 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK,
854 SCH_PREBKF_24US);
855
856 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx);
857 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK,
858 SCH_PREBKF_24US);
859 }
860
861 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx);
862 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32);
863 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US);
864
865 return 0;
866 }
867
addr_cam_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)868 static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
869 {
870 u32 val32;
871 u16 val16;
872 u32 reg;
873 int ret;
874
875 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
876 if (ret)
877 return ret;
878
879 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
880 val32 = rtw89_read32(rtwdev, reg);
881 val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK);
882 val32 |= B_BE_ADDR_CAM_EN;
883 if (mac_idx == RTW89_MAC_0)
884 val32 |= B_BE_ADDR_CAM_CLR;
885 rtw89_write32(rtwdev, reg, val32);
886
887 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
888 ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR),
889 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
890 if (ret)
891 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
892
893 return ret;
894 }
895
rtw89_mac_typ_fltr_opt_be(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)896 static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev,
897 enum rtw89_machdr_frame_type type,
898 enum rtw89_mac_fwd_target fwd_target,
899 u8 mac_idx)
900 {
901 u32 reg;
902 u32 val;
903
904 switch (fwd_target) {
905 case RTW89_FWD_DONT_CARE:
906 val = RX_FLTR_FRAME_DROP_BE;
907 break;
908 case RTW89_FWD_TO_HOST:
909 case RTW89_FWD_TO_WLAN_CPU:
910 val = RX_FLTR_FRAME_ACCEPT_BE;
911 break;
912 default:
913 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
914 return -EINVAL;
915 }
916
917 switch (type) {
918 case RTW89_MGNT:
919 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx);
920 break;
921 case RTW89_CTRL:
922 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx);
923 break;
924 case RTW89_DATA:
925 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx);
926 break;
927 default:
928 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
929 return -EINVAL;
930 }
931 rtw89_write32(rtwdev, reg, val);
932
933 return 0;
934 }
935
rx_fltr_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)936 static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
937 {
938 u32 reg;
939 u32 val;
940
941 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx);
942 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx);
943 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx);
944
945 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
946 val = B_BE_A_BC_CAM_MATCH | B_BE_A_UC_CAM_MATCH | B_BE_A_MC |
947 B_BE_A_BC | B_BE_A_A1_MATCH | B_BE_SNIFFER_MODE |
948 u32_encode_bits(15, B_BE_UID_FILTER_MASK);
949 rtw89_write32(rtwdev, reg, val);
950 u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK);
951
952 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
953 val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK |
954 B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK |
955 B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK;
956 rtw89_write16(rtwdev, reg, val);
957
958 return 0;
959 }
960
cca_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)961 static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
962 {
963 return 0;
964 }
965
nav_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)966 static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
967 {
968 u32 val32;
969 u32 reg;
970
971 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx);
972
973 val32 = rtw89_read32(rtwdev, reg);
974 val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN;
975 val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN;
976 val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK);
977
978 rtw89_write32(rtwdev, reg, val32);
979
980 return 0;
981 }
982
spatial_reuse_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)983 static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
984 {
985 u32 reg;
986 int ret;
987
988 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
989 if (ret)
990 return ret;
991
992 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx);
993 rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN);
994
995 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx);
996 rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN);
997
998 return 0;
999 }
1000
tmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1001 static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1002 {
1003 u32 reg;
1004
1005 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx);
1006 rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN);
1007
1008 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx);
1009 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12);
1010 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe);
1011
1012 return 0;
1013 }
1014
trxptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1015 static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1016 {
1017 const struct rtw89_chip_info *chip = rtwdev->chip;
1018 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
1019 struct rtw89_hal *hal = &rtwdev->hal;
1020 u32 val32;
1021 u32 reg;
1022 int ret;
1023
1024 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1025 if (ret)
1026 return ret;
1027
1028 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx);
1029 val32 = rtw89_read32(rtwdev, reg);
1030 val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF,
1031 B_BE_MACLBK_PLCP_DLY_MASK);
1032 val32 &= ~B_BE_MACLBK_EN;
1033 rtw89_write32(rtwdev, reg, val32);
1034
1035 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1036 val32 = rtw89_read32(rtwdev, reg);
1037 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_CCK,
1038 B_BE_WMAC_SPEC_SIFS_CCK_MASK);
1039 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_OFDM_1115E,
1040 B_BE_WMAC_SPEC_SIFS_OFDM_MASK);
1041 rtw89_write32(rtwdev, reg, val32);
1042
1043 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx);
1044 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA);
1045
1046 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx);
1047 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA);
1048
1049 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx);
1050 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA);
1051
1052 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx);
1053 rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN);
1054
1055 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx);
1056 val32 = rtw89_read32(rtwdev, reg);
1057 val32 &= B_BE_FTM_RRSR_RATE_EN_MASK | B_BE_WMAC_RESP_DOPPLEB_BE_EN |
1058 B_BE_WMAC_RESP_DCM_EN | B_BE_WMAC_RESP_REF_RATE_MASK;
1059 rtw89_write32(rtwdev, reg, val32);
1060 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
1061
1062 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1063 val32 = rtw89_read32(rtwdev, reg);
1064 val32 &= B_BE_RRSR_RATE_EN_MASK | B_BE_RRSR_CCK_MASK | B_BE_RSC_MASK;
1065 rtw89_write32(rtwdev, reg, val32);
1066
1067 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx);
1068 val32 = rtw89_read32(rtwdev, reg);
1069 val32 &= B_BE_RRSR_OFDM_MASK | B_BE_RRSR_HT_MASK | B_BE_RRSR_VHT_MASK |
1070 B_BE_RRSR_HE_MASK;
1071 rtw89_write32(rtwdev, reg, val32);
1072
1073 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) {
1074 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1075 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1);
1076 }
1077
1078 return 0;
1079 }
1080
rst_bacam_be(struct rtw89_dev * rtwdev)1081 static int rst_bacam_be(struct rtw89_dev *rtwdev)
1082 {
1083 u32 val;
1084 int ret;
1085
1086 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK,
1087 S_BE_BACAM_RST_ALL);
1088
1089 ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE,
1090 1, 1000, false,
1091 rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK);
1092 if (ret)
1093 rtw89_err(rtwdev, "[ERR]bacam rst timeout\n");
1094
1095 return ret;
1096 }
1097
1098 #define PLD_RLS_MAX_PG 127
1099 #define RX_MAX_LEN_UNIT 512
1100 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
1101
rmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1102 static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1103 {
1104 u32 rx_min_qta, rx_max_len, rx_max_pg;
1105 u16 val16;
1106 u32 reg;
1107 int ret;
1108
1109 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1110 if (ret)
1111 return ret;
1112
1113 if (mac_idx == RTW89_MAC_0) {
1114 ret = rst_bacam_be(rtwdev);
1115 if (ret)
1116 return ret;
1117 }
1118
1119 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx);
1120 val16 = rtw89_read16(rtwdev, reg);
1121 val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK);
1122 val16 = u16_replace_bits(val16, TRXCFG_RMAC_CCA_TO, B_BE_RX_DLK_CCA_TIME_MASK);
1123 val16 |= B_BE_RX_DLK_RST_EN;
1124 rtw89_write16(rtwdev, reg, val16);
1125
1126 if (mac_idx == RTW89_MAC_0)
1127 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta;
1128 else
1129 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta;
1130 rx_max_pg = min_t(u32, rx_min_qta, PLD_RLS_MAX_PG);
1131 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size;
1132 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
1133 rx_max_len /= RX_MAX_LEN_UNIT;
1134
1135 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
1136 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len);
1137
1138 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1139 rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK);
1140
1141 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
1142 rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN);
1143
1144 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx);
1145 rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC);
1146
1147 return 0;
1148 }
1149
resp_pktctl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1150 static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1151 {
1152 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
1153 enum rtw89_mac_dle_rsvd_qt_type type;
1154 u32 reg;
1155 int ret;
1156
1157 if (mac_idx == RTW89_MAC_1)
1158 type = DLE_RSVD_QT_B1_CSI;
1159 else
1160 type = DLE_RSVD_QT_B0_CSI;
1161
1162 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, type, &qt_cfg);
1163 if (ret) {
1164 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", type, ret);
1165 return ret;
1166 }
1167
1168 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx);
1169 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid);
1170 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num);
1171
1172 return 0;
1173 }
1174
cmac_com_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1175 static int cmac_com_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1176 {
1177 u32 val32;
1178 int ret;
1179
1180 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1181 if (ret)
1182 return ret;
1183
1184 if (mac_idx == RTW89_MAC_0) {
1185 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE);
1186 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_8, B_BE_TXSB_20M_MASK);
1187 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_4, B_BE_TXSB_40M_MASK);
1188 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_2, B_BE_TXSB_80M_MASK);
1189 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_1, B_BE_TXSB_160M_MASK);
1190 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE, val32);
1191 } else {
1192 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1);
1193 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_2, B_BE_TXSB_20M_MASK);
1194 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_1, B_BE_TXSB_40M_MASK);
1195 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_0, B_BE_TXSB_80M_MASK);
1196 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_0, B_BE_TXSB_160M_MASK);
1197 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1, val32);
1198 }
1199
1200 return 0;
1201 }
1202
ptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1203 static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1204 {
1205 u32 val32;
1206 u8 val8;
1207 u32 reg;
1208 int ret;
1209
1210 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1211 if (ret)
1212 return ret;
1213
1214 if (is_qta_poh(rtwdev)) {
1215 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx);
1216 val32 = rtw89_read32(rtwdev, reg);
1217 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K,
1218 B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK);
1219 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B,
1220 B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
1221 val32 |= B_BE_HW_CTS2SELF_EN;
1222 rtw89_write32(rtwdev, reg, val32);
1223
1224 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx);
1225 val32 = rtw89_read32(rtwdev, reg);
1226 val32 = u32_replace_bits(val32, S_AX_PTCL_TO_2MS,
1227 B_BE_PTCL_TX_ARB_TO_THR_MASK);
1228 val32 &= ~B_BE_PTCL_TX_ARB_TO_MODE;
1229 rtw89_write32(rtwdev, reg, val32);
1230 }
1231
1232 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx);
1233 val8 = rtw89_read8(rtwdev, reg);
1234 val8 |= B_BE_CMAC_TX_MODE_0 | B_BE_CMAC_TX_MODE_1;
1235 val8 &= ~(B_BE_PTCL_TRIGGER_SS_EN_0 |
1236 B_BE_PTCL_TRIGGER_SS_EN_1 |
1237 B_BE_PTCL_TRIGGER_SS_EN_UL);
1238 rtw89_write8(rtwdev, reg, val8);
1239
1240 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1241 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, AMPDU_MAX_TIME);
1242
1243 return 0;
1244 }
1245
cmac_dma_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1246 static int cmac_dma_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1247 {
1248 u32 val32;
1249 u32 reg;
1250 int ret;
1251
1252 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1253 if (ret)
1254 return ret;
1255
1256 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx);
1257
1258 val32 = rtw89_read32(rtwdev, reg);
1259 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1260 B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK);
1261 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1262 B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK);
1263 rtw89_write32(rtwdev, reg, val32);
1264
1265 return 0;
1266 }
1267
cmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1268 static int cmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1269 {
1270 int ret;
1271
1272 ret = scheduler_init_be(rtwdev, mac_idx);
1273 if (ret) {
1274 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
1275 return ret;
1276 }
1277
1278 ret = addr_cam_init_be(rtwdev, mac_idx);
1279 if (ret) {
1280 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
1281 ret);
1282 return ret;
1283 }
1284
1285 ret = rx_fltr_init_be(rtwdev, mac_idx);
1286 if (ret) {
1287 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
1288 ret);
1289 return ret;
1290 }
1291
1292 ret = cca_ctrl_init_be(rtwdev, mac_idx);
1293 if (ret) {
1294 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
1295 ret);
1296 return ret;
1297 }
1298
1299 ret = nav_ctrl_init_be(rtwdev, mac_idx);
1300 if (ret) {
1301 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
1302 ret);
1303 return ret;
1304 }
1305
1306 ret = spatial_reuse_init_be(rtwdev, mac_idx);
1307 if (ret) {
1308 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
1309 mac_idx, ret);
1310 return ret;
1311 }
1312
1313 ret = tmac_init_be(rtwdev, mac_idx);
1314 if (ret) {
1315 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
1316 return ret;
1317 }
1318
1319 ret = trxptcl_init_be(rtwdev, mac_idx);
1320 if (ret) {
1321 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
1322 return ret;
1323 }
1324
1325 ret = rmac_init_be(rtwdev, mac_idx);
1326 if (ret) {
1327 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
1328 return ret;
1329 }
1330
1331 ret = resp_pktctl_init_be(rtwdev, mac_idx);
1332 if (ret) {
1333 rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret);
1334 return ret;
1335 }
1336
1337 ret = cmac_com_init_be(rtwdev, mac_idx);
1338 if (ret) {
1339 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
1340 return ret;
1341 }
1342
1343 ret = ptcl_init_be(rtwdev, mac_idx);
1344 if (ret) {
1345 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
1346 return ret;
1347 }
1348
1349 ret = cmac_dma_init_be(rtwdev, mac_idx);
1350 if (ret) {
1351 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
1352 return ret;
1353 }
1354
1355 return ret;
1356 }
1357
tx_idle_poll_band_be(struct rtw89_dev * rtwdev,u8 mac_idx)1358 static int tx_idle_poll_band_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1359 {
1360 u32 reg;
1361 u8 val8;
1362 int ret;
1363
1364 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1365 if (ret)
1366 return ret;
1367
1368 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx);
1369
1370 ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY),
1371 30, 66000, false, rtwdev, reg);
1372
1373 return ret;
1374 }
1375
dle_buf_req_be(struct rtw89_dev * rtwdev,u16 buf_len,bool wd,u16 * pkt_id)1376 static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
1377 {
1378 u32 val, reg;
1379 int ret;
1380
1381 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ;
1382 val = buf_len;
1383 val |= B_BE_WD_BUF_REQ_EXEC;
1384 rtw89_write32(rtwdev, reg, val);
1385
1386 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS;
1387
1388 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_BUF_STAT_DONE,
1389 1, 2000, false, rtwdev, reg);
1390 if (ret)
1391 return ret;
1392
1393 *pkt_id = u32_get_bits(val, B_BE_WD_BUF_STAT_PKTID_MASK);
1394 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID)
1395 return -ENOENT;
1396
1397 return 0;
1398 }
1399
set_cpuio_be(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)1400 static int set_cpuio_be(struct rtw89_dev *rtwdev,
1401 struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
1402 {
1403 u32 val_op0, val_op1, val_op2, val_op3;
1404 u32 val, cmd_type, reg;
1405 int ret;
1406
1407 cmd_type = ctrl_para->cmd_type;
1408
1409 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3;
1410 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid,
1411 B_BE_WD_CPUQ_OP_STRT_PKTID_MASK);
1412 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid,
1413 B_BE_WD_CPUQ_OP_END_PKTID_MASK);
1414 rtw89_write32(rtwdev, reg, val_op3);
1415
1416 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1;
1417 val_op1 = u32_replace_bits(0, ctrl_para->src_pid,
1418 B_BE_WD_CPUQ_OP_SRC_PID_MASK);
1419 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid,
1420 B_BE_WD_CPUQ_OP_SRC_QID_MASK);
1421 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid,
1422 B_BE_WD_CPUQ_OP_SRC_MACID_MASK);
1423 rtw89_write32(rtwdev, reg, val_op1);
1424
1425 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2;
1426 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid,
1427 B_BE_WD_CPUQ_OP_DST_PID_MASK);
1428 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid,
1429 B_BE_WD_CPUQ_OP_DST_QID_MASK);
1430 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid,
1431 B_BE_WD_CPUQ_OP_DST_MACID_MASK);
1432 rtw89_write32(rtwdev, reg, val_op2);
1433
1434 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0;
1435 val_op0 = u32_replace_bits(0, cmd_type,
1436 B_BE_WD_CPUQ_OP_CMD_TYPE_MASK);
1437 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num,
1438 B_BE_WD_CPUQ_OP_PKTNUM_MASK);
1439 val_op0 |= B_BE_WD_CPUQ_OP_EXEC;
1440 rtw89_write32(rtwdev, reg, val_op0);
1441
1442 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS;
1443
1444 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_CPUQ_OP_STAT_DONE,
1445 1, 2000, false, rtwdev, reg);
1446 if (ret) {
1447 rtw89_err(rtwdev, "[ERR]set cpuio wd timeout\n");
1448 rtw89_err(rtwdev, "[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n",
1449 val_op0, val_op1, val_op2);
1450 return ret;
1451 }
1452
1453 if (cmd_type == CPUIO_OP_CMD_GET_NEXT_PID ||
1454 cmd_type == CPUIO_OP_CMD_GET_1ST_PID)
1455 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK);
1456
1457 return 0;
1458 }
1459
dle_upd_qta_aval_page_be(struct rtw89_dev * rtwdev,enum rtw89_mac_dle_ctrl_type type,enum rtw89_mac_dle_ple_quota_id quota_id)1460 static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev,
1461 enum rtw89_mac_dle_ctrl_type type,
1462 enum rtw89_mac_dle_ple_quota_id quota_id)
1463 {
1464 u32 val;
1465
1466 if (type == DLE_CTRL_TYPE_WDE) {
1467 rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL,
1468 B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id);
1469 rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ);
1470
1471 return read_poll_timeout(rtw89_read32, val,
1472 !(val & B_BE_WDE_AVAL_UPD_REQ),
1473 1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL);
1474 } else if (type == DLE_CTRL_TYPE_PLE) {
1475 rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL,
1476 B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id);
1477 rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ);
1478
1479 return read_poll_timeout(rtw89_read32, val,
1480 !(val & B_BE_PLE_AVAL_UPD_REQ),
1481 1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL);
1482 }
1483
1484 rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type);
1485 return -EINVAL;
1486 }
1487
dle_quota_change_be(struct rtw89_dev * rtwdev,bool band1_en)1488 static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en)
1489 {
1490 int ret;
1491
1492 if (band1_en) {
1493 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1494 PLE_QTAID_B0_TXPL);
1495 if (ret) {
1496 rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret);
1497 return ret;
1498 }
1499
1500 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1501 PLE_QTAID_CMAC0_RX);
1502 if (ret) {
1503 rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret);
1504 return ret;
1505 }
1506 } else {
1507 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1508 PLE_QTAID_B1_TXPL);
1509 if (ret) {
1510 rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret);
1511 return ret;
1512 }
1513
1514 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1515 PLE_QTAID_CMAC1_RX);
1516 if (ret) {
1517 rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret);
1518 return ret;
1519 }
1520 }
1521
1522 return 0;
1523 }
1524
preload_init_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_qta_mode mode)1525 static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
1526 enum rtw89_qta_mode mode)
1527 {
1528 u32 max_preld_size, min_rsvd_size;
1529 u32 val32;
1530 u32 reg;
1531
1532 max_preld_size = mac_idx == RTW89_MAC_0 ?
1533 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM;
1534 max_preld_size *= PRELD_AMSDU_SIZE;
1535
1536 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 :
1537 R_BE_TXPKTCTL_B1_PRELD_CFG0;
1538 val32 = rtw89_read32(rtwdev, reg);
1539 val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK);
1540 val32 |= B_BE_B0_PRELD_FEN;
1541 rtw89_write32(rtwdev, reg, val32);
1542
1543 min_rsvd_size = PRELD_AMSDU_SIZE;
1544 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 :
1545 R_BE_TXPKTCTL_B1_PRELD_CFG1;
1546 val32 = rtw89_read32(rtwdev, reg);
1547 val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK);
1548 val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK);
1549 rtw89_write32(rtwdev, reg, val32);
1550
1551 return 0;
1552 }
1553
dbcc_bb_ctrl_be(struct rtw89_dev * rtwdev,bool bb1_en)1554 static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en)
1555 {
1556 u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN;
1557
1558 if (bb1_en)
1559 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set);
1560 else
1561 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set);
1562
1563 return 0;
1564 }
1565
enable_imr_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)1566 static int enable_imr_be(struct rtw89_dev *rtwdev, u8 mac_idx,
1567 enum rtw89_mac_hwmod_sel sel)
1568 {
1569 const struct rtw89_chip_info *chip = rtwdev->chip;
1570 const struct rtw89_imr_table *table;
1571 const struct rtw89_reg_imr *reg;
1572 u32 addr;
1573 u32 val;
1574 int i;
1575
1576 if (sel == RTW89_DMAC_SEL)
1577 table = chip->imr_dmac_table;
1578 else if (sel == RTW89_CMAC_SEL)
1579 table = chip->imr_cmac_table;
1580 else
1581 return -EINVAL;
1582
1583 for (i = 0; i < table->n_regs; i++) {
1584 reg = &table->regs[i];
1585 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx);
1586
1587 val = rtw89_read32(rtwdev, addr);
1588 val &= ~reg->clr;
1589 val |= reg->set;
1590 rtw89_write32(rtwdev, addr, val);
1591 }
1592
1593 return 0;
1594 }
1595
err_imr_ctrl_be(struct rtw89_dev * rtwdev,bool en)1596 static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en)
1597 {
1598 u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS;
1599 u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS;
1600 u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS;
1601
1602 v32_dmac &= ~B_BE_DMAC_NOTX_ERR_INT_EN;
1603
1604 rtw89_write32(rtwdev, R_BE_DMAC_ERR_IMR, v32_dmac);
1605 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR, v32_cmac0);
1606
1607 if (rtwdev->dbcc_en)
1608 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR_C1, v32_cmac1);
1609 }
1610
band1_enable_be(struct rtw89_dev * rtwdev)1611 static int band1_enable_be(struct rtw89_dev *rtwdev)
1612 {
1613 int ret;
1614
1615 ret = tx_idle_poll_band_be(rtwdev, RTW89_MAC_0);
1616 if (ret) {
1617 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
1618 return ret;
1619 }
1620
1621 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
1622 if (ret) {
1623 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
1624 return ret;
1625 }
1626
1627 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode);
1628 if (ret) {
1629 rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret);
1630 return ret;
1631 }
1632
1633 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
1634 if (ret) {
1635 rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret);
1636 return ret;
1637 }
1638
1639 ret = cmac_init_be(rtwdev, RTW89_MAC_1);
1640 if (ret) {
1641 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret);
1642 return ret;
1643 }
1644
1645 ret = dbcc_bb_ctrl_be(rtwdev, true);
1646 if (ret) {
1647 rtw89_err(rtwdev, "[ERR]enable bb 1 %d\n", ret);
1648 return ret;
1649 }
1650
1651 ret = enable_imr_be(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
1652 if (ret) {
1653 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
1654 return ret;
1655 }
1656
1657 return 0;
1658 }
1659
band1_disable_be(struct rtw89_dev * rtwdev)1660 static int band1_disable_be(struct rtw89_dev *rtwdev)
1661 {
1662 int ret;
1663
1664 ret = dbcc_bb_ctrl_be(rtwdev, false);
1665 if (ret) {
1666 rtw89_err(rtwdev, "[ERR]disable bb 1 %d\n", ret);
1667 return ret;
1668 }
1669
1670 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false);
1671 if (ret) {
1672 rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret);
1673 return ret;
1674 }
1675
1676 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false);
1677 if (ret) {
1678 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
1679 return ret;
1680 }
1681
1682 return 0;
1683 }
1684
dbcc_enable_be(struct rtw89_dev * rtwdev,bool enable)1685 static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable)
1686 {
1687 int ret;
1688
1689 if (enable) {
1690 ret = band1_enable_be(rtwdev);
1691 if (ret) {
1692 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
1693 return ret;
1694 }
1695
1696 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
1697 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true);
1698 if (ret) {
1699 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
1700 __func__, ret);
1701 return ret;
1702 }
1703 }
1704 } else {
1705 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
1706 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false);
1707 if (ret) {
1708 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
1709 __func__, ret);
1710 return ret;
1711 }
1712 }
1713
1714 ret = band1_disable_be(rtwdev);
1715 if (ret) {
1716 rtw89_err(rtwdev, "[ERR] band1_disable %d\n", ret);
1717 return ret;
1718 }
1719 }
1720
1721 return 0;
1722 }
1723
set_host_rpr_be(struct rtw89_dev * rtwdev)1724 static int set_host_rpr_be(struct rtw89_dev *rtwdev)
1725 {
1726 u32 val32;
1727 u32 mode;
1728 u32 fltr;
1729 bool poh;
1730
1731 poh = is_qta_poh(rtwdev);
1732
1733 if (poh) {
1734 mode = RTW89_RPR_MODE_POH;
1735 fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT |
1736 S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID;
1737 } else {
1738 mode = RTW89_RPR_MODE_STF;
1739 fltr = 0;
1740 }
1741
1742 rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode);
1743
1744 val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1);
1745 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK);
1746 val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK);
1747 val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK);
1748 rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32);
1749
1750 return 0;
1751 }
1752
trx_init_be(struct rtw89_dev * rtwdev)1753 static int trx_init_be(struct rtw89_dev *rtwdev)
1754 {
1755 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1756 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
1757 int ret;
1758
1759 ret = dmac_init_be(rtwdev, 0);
1760 if (ret) {
1761 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
1762 return ret;
1763 }
1764
1765 ret = cmac_init_be(rtwdev, 0);
1766 if (ret) {
1767 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
1768 return ret;
1769 }
1770
1771 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) {
1772 ret = dbcc_enable_be(rtwdev, true);
1773 if (ret) {
1774 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
1775 return ret;
1776 }
1777 }
1778
1779 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1780 if (ret) {
1781 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
1782 return ret;
1783 }
1784
1785 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
1786 if (ret) {
1787 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
1788 return ret;
1789 }
1790
1791 err_imr_ctrl_be(rtwdev, true);
1792
1793 ret = set_host_rpr_be(rtwdev);
1794 if (ret) {
1795 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
1796 return ret;
1797 }
1798
1799 if (chip_id == RTL8922A)
1800 rtw89_write32_clr(rtwdev, R_BE_RSP_CHK_SIG,
1801 B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN);
1802
1803 return 0;
1804 }
1805
rtw89_mac_cfg_gnt_v2(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)1806 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1807 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
1808 {
1809 u32 val = 0;
1810
1811 if (gnt_cfg->band[0].gnt_bt)
1812 val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL |
1813 B_BE_GNT_BT_TX_BB0_VAL;
1814
1815 if (gnt_cfg->band[0].gnt_bt_sw_en)
1816 val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL |
1817 B_BE_GNT_BT_TX_BB0_SWCTRL;
1818
1819 if (gnt_cfg->band[0].gnt_wl)
1820 val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL |
1821 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
1822
1823 if (gnt_cfg->band[0].gnt_wl_sw_en)
1824 val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
1825 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
1826
1827 if (gnt_cfg->band[1].gnt_bt)
1828 val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL |
1829 B_BE_GNT_BT_TX_BB1_VAL;
1830
1831 if (gnt_cfg->band[1].gnt_bt_sw_en)
1832 val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL |
1833 B_BE_GNT_BT_TX_BB1_SWCTRL;
1834
1835 if (gnt_cfg->band[1].gnt_wl)
1836 val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL |
1837 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
1838
1839 if (gnt_cfg->band[1].gnt_wl_sw_en)
1840 val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
1841 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
1842
1843 if (gnt_cfg->bt[0].wlan_act_en)
1844 val |= B_BE_WL_ACT_SWCTRL;
1845 if (gnt_cfg->bt[0].wlan_act)
1846 val |= B_BE_WL_ACT_VAL;
1847 if (gnt_cfg->bt[1].wlan_act_en)
1848 val |= B_BE_WL_ACT2_SWCTRL;
1849 if (gnt_cfg->bt[1].wlan_act)
1850 val |= B_BE_WL_ACT2_VAL;
1851
1852 rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val);
1853
1854 return 0;
1855 }
1856 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2);
1857
rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev * rtwdev,bool wl)1858 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl)
1859 {
1860 struct rtw89_btc *btc = &rtwdev->btc;
1861 struct rtw89_btc_dm *dm = &btc->dm;
1862 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
1863 struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt;
1864 int i;
1865
1866 if (wl)
1867 return 0;
1868
1869 for (i = 0; i < RTW89_PHY_NUM; i++) {
1870 g[i].gnt_bt_sw_en = 1;
1871 g[i].gnt_bt = 1;
1872 g[i].gnt_wl_sw_en = 1;
1873 g[i].gnt_wl = 0;
1874 gbt[i].wlan_act = 1;
1875 gbt[i].wlan_act_en = 0;
1876 }
1877
1878 return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);
1879 }
1880 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2);
1881
1882 static
rtw89_mac_cfg_plt_be(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1883 int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1884 {
1885 u32 reg;
1886 u16 val;
1887 int ret;
1888
1889 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
1890 if (ret)
1891 return ret;
1892
1893 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band);
1894 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) |
1895 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) |
1896 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) |
1897 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) |
1898 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) |
1899 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) |
1900 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) |
1901 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) |
1902 B_BE_PLT_EN;
1903 rtw89_write16(rtwdev, reg, val);
1904
1905 return 0;
1906 }
1907
rtw89_mac_get_plt_cnt_be(struct rtw89_dev * rtwdev,u8 band)1908 static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band)
1909 {
1910 u32 reg;
1911 u16 cnt;
1912
1913 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band);
1914 cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK);
1915 rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST);
1916
1917 return cnt;
1918 }
1919
rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)1920 static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1921 u32 tx_en, u32 tx_en_mask)
1922 {
1923 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx);
1924 u32 val;
1925 int ret;
1926
1927 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1928 if (ret)
1929 return ret;
1930
1931 val = rtw89_read32(rtwdev, reg);
1932 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
1933 rtw89_write32(rtwdev, reg, val);
1934
1935 return 0;
1936 }
1937
rtw89_mac_stop_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)1938 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1939 u32 *tx_en, enum rtw89_sch_tx_sel sel)
1940 {
1941 int ret;
1942
1943 *tx_en = rtw89_read32(rtwdev,
1944 rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx));
1945
1946 switch (sel) {
1947 case RTW89_SCH_TX_SEL_ALL:
1948 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
1949 B_BE_CTN_TXEN_ALL_MASK);
1950 if (ret)
1951 return ret;
1952 break;
1953 case RTW89_SCH_TX_SEL_HIQ:
1954 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
1955 0, B_BE_CTN_TXEN_HGQ);
1956 if (ret)
1957 return ret;
1958 break;
1959 case RTW89_SCH_TX_SEL_MG0:
1960 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
1961 0, B_BE_CTN_TXEN_MGQ);
1962 if (ret)
1963 return ret;
1964 break;
1965 case RTW89_SCH_TX_SEL_MACID:
1966 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
1967 B_BE_CTN_TXEN_ALL_MASK);
1968 if (ret)
1969 return ret;
1970 break;
1971 default:
1972 return 0;
1973 }
1974
1975 return 0;
1976 }
1977 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v2);
1978
rtw89_mac_resume_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)1979 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
1980 {
1981 int ret;
1982
1983 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, tx_en,
1984 B_BE_CTN_TXEN_ALL_MASK);
1985 if (ret)
1986 return ret;
1987
1988 return 0;
1989 }
1990 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v2);
1991
rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1992 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1993 {
1994 u32 reg, val;
1995
1996 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
1997 val = enable ? MAC_AX_PHY_RPT_SIZE_8 : MAC_AX_PHY_RPT_SIZE_0;
1998 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val);
1999 rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0);
2000
2001 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx);
2002 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable);
2003 }
2004 EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be);
2005
2006 static
rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)2007 int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
2008 {
2009 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx);
2010 int ret;
2011
2012 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2013 if (ret)
2014 return ret;
2015
2016 if (!enable) {
2017 rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN);
2018 return 0;
2019 }
2020
2021 rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3);
2022 rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN | B_BE_PPDU_MAC_INFO |
2023 B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT |
2024 B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA);
2025
2026 return 0;
2027 }
2028
rtw89_mac_get_txpwr_cr_be(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)2029 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev,
2030 enum rtw89_phy_idx phy_idx,
2031 u32 reg_base, u32 *cr)
2032 {
2033 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
2034 int ret;
2035
2036 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx,
2037 RTW89_CMAC_SEL);
2038 if (ret) {
2039 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2040 return false;
2041
2042 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n");
2043 return false;
2044 }
2045
2046 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) {
2047 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n",
2048 reg_base);
2049 return false;
2050 }
2051
2052 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
2053
2054 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) {
2055 if (mode == RTW89_QTA_SCC) {
2056 rtw89_err(rtwdev,
2057 "[TXPWR] addr=0x%x but hw not enable\n",
2058 *cr);
2059 return false;
2060 }
2061 }
2062
2063 return true;
2064 }
2065
rtw89_mac_init_bfee_be(struct rtw89_dev * rtwdev,u8 mac_idx)2066 static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx)
2067 {
2068 u32 reg;
2069 u32 val;
2070 int ret;
2071
2072 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2073 if (ret)
2074 return ret;
2075
2076 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
2077
2078 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2079 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL |
2080 B_BE_BFMEE_USE_NSTS |
2081 B_BE_BFMEE_CSI_GID_SEL |
2082 B_BE_BFMEE_CSI_FORCE_RETE_EN);
2083 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG);
2084
2085 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx);
2086 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN |
2087 B_BE_CSIPRT_HESU_AID_EN |
2088 B_BE_CSIPRT_EHTSU_AID_EN);
2089
2090 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2091 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE);
2092
2093 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
2094 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK,
2095 CSI_RRSC_BITMAP_CFG);
2096
2097 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx);
2098 val = u32_encode_bits(CSI_INIT_RATE_HT, B_BE_BFMEE_HT_CSI_RATE_MASK) |
2099 u32_encode_bits(CSI_INIT_RATE_VHT, B_BE_BFMEE_VHT_CSI_RATE_MASK) |
2100 u32_encode_bits(CSI_INIT_RATE_HE, B_BE_BFMEE_HE_CSI_RATE_MASK) |
2101 u32_encode_bits(CSI_INIT_RATE_EHT, B_BE_BFMEE_EHT_CSI_RATE_MASK);
2102
2103 rtw89_write32(rtwdev, reg, val);
2104
2105 return 0;
2106 }
2107
rtw89_mac_set_csi_para_reg_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2108 static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev,
2109 struct rtw89_vif_link *rtwvif_link,
2110 struct rtw89_sta_link *rtwsta_link)
2111 {
2112 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
2113 struct ieee80211_link_sta *link_sta;
2114 u8 mac_idx = rtwvif_link->mac_idx;
2115 u8 port_sel = rtwvif_link->port;
2116 u8 sound_dim = 3, t;
2117 u8 *phy_cap;
2118 u32 reg;
2119 u16 val;
2120 int ret;
2121
2122 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2123 if (ret)
2124 return ret;
2125
2126 rcu_read_lock();
2127
2128 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2129 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
2130
2131 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
2132 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
2133 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
2134 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
2135 t = u8_get_bits(phy_cap[5],
2136 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK);
2137 sound_dim = min(sound_dim, t);
2138 }
2139
2140 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
2141 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
2142 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
2143 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
2144 t = u32_get_bits(link_sta->vht_cap.cap,
2145 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK);
2146 sound_dim = min(sound_dim, t);
2147 }
2148
2149 nc = min(nc, sound_dim);
2150 nr = min(nr, sound_dim);
2151
2152 rcu_read_unlock();
2153
2154 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2155 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2156
2157 val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) |
2158 u16_encode_bits(nr, B_BE_BFMEE_CSIINFO0_NR_MASK) |
2159 u16_encode_bits(ng, B_BE_BFMEE_CSIINFO0_NG_MASK) |
2160 u16_encode_bits(cb, B_BE_BFMEE_CSIINFO0_CB_MASK) |
2161 u16_encode_bits(cs, B_BE_BFMEE_CSIINFO0_CS_MASK) |
2162 u16_encode_bits(ldpc_en, B_BE_BFMEE_CSIINFO0_LDPC_EN) |
2163 u16_encode_bits(stbc_en, B_BE_BFMEE_CSIINFO0_STBC_EN);
2164
2165 if (port_sel == 0)
2166 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0,
2167 mac_idx);
2168 else
2169 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1,
2170 mac_idx);
2171
2172 rtw89_write16(rtwdev, reg, val);
2173
2174 return 0;
2175 }
2176
rtw89_mac_csi_rrsc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2177 static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev,
2178 struct rtw89_vif_link *rtwvif_link,
2179 struct rtw89_sta_link *rtwsta_link)
2180 {
2181 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
2182 struct ieee80211_link_sta *link_sta;
2183 u8 mac_idx = rtwvif_link->mac_idx;
2184 int ret;
2185 u32 reg;
2186
2187 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2188 if (ret)
2189 return ret;
2190
2191 rcu_read_lock();
2192
2193 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2194
2195 if (link_sta->he_cap.has_he) {
2196 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
2197 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
2198 BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
2199 }
2200 if (link_sta->vht_cap.vht_supported) {
2201 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
2202 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
2203 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
2204 }
2205 if (link_sta->ht_cap.ht_supported) {
2206 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
2207 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
2208 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
2209 }
2210
2211 rcu_read_unlock();
2212
2213 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2214 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2215 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN);
2216
2217 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2218 rtw89_write32(rtwdev, reg, rrsc);
2219
2220 return 0;
2221 }
2222
rtw89_mac_bf_assoc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2223 static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev,
2224 struct rtw89_vif_link *rtwvif_link,
2225 struct rtw89_sta_link *rtwsta_link)
2226 {
2227 struct ieee80211_link_sta *link_sta;
2228 bool has_beamformer_cap;
2229
2230 rcu_read_lock();
2231
2232 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2233 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta);
2234
2235 rcu_read_unlock();
2236
2237 if (has_beamformer_cap) {
2238 rtw89_debug(rtwdev, RTW89_DBG_BF,
2239 "initialize bfee for new association\n");
2240 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx);
2241 rtw89_mac_set_csi_para_reg_be(rtwdev, rtwvif_link, rtwsta_link);
2242 rtw89_mac_csi_rrsc_be(rtwdev, rtwvif_link, rtwsta_link);
2243 }
2244 }
2245
dump_err_status_dispatcher_be(struct rtw89_dev * rtwdev)2246 static void dump_err_status_dispatcher_be(struct rtw89_dev *rtwdev)
2247 {
2248 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x ",
2249 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR));
2250 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n",
2251 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1));
2252 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x ",
2253 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR));
2254 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n",
2255 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2));
2256 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x ",
2257 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR));
2258 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n",
2259 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0));
2260 }
2261
rtw89_mac_dump_qta_lost_be(struct rtw89_dev * rtwdev)2262 static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev)
2263 {
2264 struct rtw89_mac_dle_dfi_qempty qempty;
2265 struct rtw89_mac_dle_dfi_quota quota;
2266 struct rtw89_mac_dle_dfi_ctrl ctrl;
2267 u32 val, not_empty, i;
2268 int ret;
2269
2270 qempty.dle_type = DLE_CTRL_TYPE_PLE;
2271 qempty.grpsel = 0;
2272 qempty.qempty = ~(u32)0;
2273 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
2274 if (ret)
2275 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2276 else
2277 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
2278
2279 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
2280 if (!(not_empty & BIT(0)))
2281 continue;
2282 ctrl.type = DLE_CTRL_TYPE_PLE;
2283 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
2284 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
2285 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK);
2286 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
2287 if (ret)
2288 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2289 else
2290 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i,
2291 u32_get_bits(ctrl.out_data,
2292 QLNKTBL_DATA_SEL1_PKT_CNT_MASK));
2293 }
2294
2295 quota.dle_type = DLE_CTRL_TYPE_PLE;
2296 quota.qtaid = 6;
2297 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
2298 if (ret)
2299 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2300 else
2301 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
2302 quota.rsv_pgnum, quota.use_pgnum);
2303
2304 val = rtw89_read32(rtwdev, R_BE_PLE_QTA6_CFG);
2305 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n",
2306 u32_get_bits(val, B_BE_PLE_Q6_MIN_SIZE_MASK));
2307 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n",
2308 u32_get_bits(val, B_BE_PLE_Q6_MAX_SIZE_MASK));
2309 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT);
2310 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
2311 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
2312 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG=0x%08x\n",
2313 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG));
2314 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0=0x%08x\n",
2315 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0));
2316
2317 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
2318 quota.dle_type = DLE_CTRL_TYPE_PLE;
2319 quota.qtaid = 7;
2320 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
2321 if (ret)
2322 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2323 else
2324 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n",
2325 quota.rsv_pgnum, quota.use_pgnum);
2326
2327 val = rtw89_read32(rtwdev, R_BE_PLE_QTA7_CFG);
2328 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n",
2329 u32_get_bits(val, B_BE_PLE_Q7_MIN_SIZE_MASK));
2330 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n",
2331 u32_get_bits(val, B_BE_PLE_Q7_MAX_SIZE_MASK));
2332 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT_C1);
2333 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
2334 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
2335 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG_C1=0x%08x\n",
2336 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG_C1));
2337 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0_C1=0x%08x\n",
2338 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0_C1));
2339 }
2340
2341 rtw89_info(rtwdev, "R_BE_DLE_EMPTY0=0x%08x\n",
2342 rtw89_read32(rtwdev, R_BE_DLE_EMPTY0));
2343 rtw89_info(rtwdev, "R_BE_DLE_EMPTY1=0x%08x\n",
2344 rtw89_read32(rtwdev, R_BE_DLE_EMPTY1));
2345
2346 dump_err_status_dispatcher_be(rtwdev);
2347 }
2348
rtw89_wow_config_mac_be(struct rtw89_dev * rtwdev,bool enable_wow)2349 static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow)
2350 {
2351 if (enable_wow) {
2352 rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
2353 rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE);
2354 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
2355 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
2356 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
2357 rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0);
2358 rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0);
2359 rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0);
2360 rtw89_write32(rtwdev, R_BE_FWD_TF0, 0);
2361 rtw89_write32(rtwdev, R_BE_FWD_TF1, 0);
2362 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
2363 rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0);
2364 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
2365 } else {
2366 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
2367 rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
2368 rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT);
2369 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
2370 }
2371
2372 return 0;
2373 }
2374
rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev * rtwdev,u8 band)2375 static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev,
2376 u8 band)
2377 {
2378 u32 offset = 0;
2379 u32 cmac_err;
2380 int ret;
2381
2382 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
2383 if (ret) {
2384 rtw89_info(rtwdev, "[CMAC] : CMAC%d not enabled\n", band);
2385 return;
2386 }
2387
2388 if (band)
2389 offset = RTW89_MAC_BE_BAND_REG_OFFSET;
2390
2391 cmac_err = rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset);
2392 rtw89_info(rtwdev, "R_BE_CMAC_ERR_ISR [%d]=0x%08x\n", band,
2393 rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset));
2394 rtw89_info(rtwdev, "R_BE_CMAC_FUNC_EN [%d]=0x%08x\n", band,
2395 rtw89_read32(rtwdev, R_BE_CMAC_FUNC_EN + offset));
2396 rtw89_info(rtwdev, "R_BE_CK_EN [%d]=0x%08x\n", band,
2397 rtw89_read32(rtwdev, R_BE_CK_EN + offset));
2398
2399 if (cmac_err & B_BE_SCHEDULE_TOP_ERR_IND) {
2400 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
2401 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_IMR + offset));
2402 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
2403 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_ISR + offset));
2404 }
2405
2406 if (cmac_err & B_BE_PTCL_TOP_ERR_IND) {
2407 rtw89_info(rtwdev, "R_BE_PTCL_IMR0 [%d]=0x%08x\n", band,
2408 rtw89_read32(rtwdev, R_BE_PTCL_IMR0 + offset));
2409 rtw89_info(rtwdev, "R_BE_PTCL_ISR0 [%d]=0x%08x\n", band,
2410 rtw89_read32(rtwdev, R_BE_PTCL_ISR0 + offset));
2411 rtw89_info(rtwdev, "R_BE_PTCL_IMR1 [%d]=0x%08x\n", band,
2412 rtw89_read32(rtwdev, R_BE_PTCL_IMR1 + offset));
2413 rtw89_info(rtwdev, "R_BE_PTCL_ISR1 [%d]=0x%08x\n", band,
2414 rtw89_read32(rtwdev, R_BE_PTCL_ISR1 + offset));
2415 }
2416
2417 if (cmac_err & B_BE_DMA_TOP_ERR_IND) {
2418 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
2419 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR + offset));
2420 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG [%d]=0x%08x\n", band,
2421 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG + offset));
2422 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
2423 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG_IMR + offset));
2424 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG [%d]=0x%08x\n", band,
2425 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG + offset));
2426 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR_1 [%d]=0x%08x\n", band,
2427 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR_1 + offset));
2428 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_1 [%d]=0x%08x\n", band,
2429 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_1 + offset));
2430 }
2431
2432 if (cmac_err & B_BE_PHYINTF_ERR_IND) {
2433 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
2434 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_IMR_V1 + offset));
2435 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
2436 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_ISR + offset));
2437 }
2438
2439 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
2440 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_FLAG [%d]=0x%08x\n", band,
2441 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_FLAG + offset));
2442 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_IMR [%d]=0x%08x\n", band,
2443 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_IMR + offset));
2444 }
2445
2446 if (cmac_err & (B_BE_WMAC_RX_ERR_IND | B_BE_WMAC_TX_ERR_IND |
2447 B_BE_WMAC_RX_IDLETO_IDCT | B_BE_PTCL_TX_IDLETO_IDCT)) {
2448 rtw89_info(rtwdev, "R_BE_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
2449 rtw89_read32(rtwdev, R_BE_DBGSEL_TRXPTCL + offset));
2450 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
2451 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA_MASK + offset));
2452 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
2453 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA + offset));
2454 rtw89_info(rtwdev, "R_BE_RX_ERR_IMR [%d]=0x%08x\n", band,
2455 rtw89_read32(rtwdev, R_BE_RX_ERR_IMR + offset));
2456 rtw89_info(rtwdev, "R_BE_RX_ERR_ISR [%d]=0x%08x\n", band,
2457 rtw89_read32(rtwdev, R_BE_RX_ERR_ISR + offset));
2458 }
2459
2460 rtw89_info(rtwdev, "R_BE_CMAC_ERR_IMR [%d]=0x%08x\n", band,
2461 rtw89_read32(rtwdev, R_BE_CMAC_ERR_IMR + offset));
2462 }
2463
rtw89_mac_dump_err_status_be(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)2464 static void rtw89_mac_dump_err_status_be(struct rtw89_dev *rtwdev,
2465 enum mac_ax_err_info err)
2466 {
2467 if (err != MAC_AX_ERR_L1_ERR_DMAC &&
2468 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
2469 err != MAC_AX_ERR_L0_ERR_CMAC0 &&
2470 err != MAC_AX_ERR_L0_ERR_CMAC1 &&
2471 err != MAC_AX_ERR_RXI300)
2472 return;
2473
2474 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
2475 rtw89_info(rtwdev, "R_BE_SER_DBG_INFO=0x%08x\n",
2476 rtw89_read32(rtwdev, R_BE_SER_DBG_INFO));
2477 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT=0x%08x\n",
2478 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT));
2479 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1=0x%08x\n",
2480 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1));
2481 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT2=0x%08x\n",
2482 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT2));
2483 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT3=0x%08x\n",
2484 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT3));
2485 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
2486 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT_C1=0x%08x\n",
2487 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT_C1));
2488 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1_C1=0x%08x\n",
2489 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1_C1));
2490 }
2491 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_0=0x%08x\n",
2492 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_0));
2493 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_1=0x%08x\n",
2494 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_1));
2495 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_2=0x%08x\n",
2496 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_2));
2497 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_3=0x%08x\n",
2498 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_3));
2499 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_4=0x%08x\n",
2500 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_4));
2501 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_5=0x%08x\n",
2502 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_5));
2503 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_6=0x%08x\n",
2504 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_6));
2505 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_7=0x%08x\n",
2506 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_7));
2507
2508 rtw89_mac_dump_dmac_err_status(rtwdev);
2509 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_0);
2510 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_1);
2511
2512 rtwdev->hci.ops->dump_err_status(rtwdev);
2513
2514 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
2515 rtw89_mac_dump_l0_to_l1(rtwdev, err);
2516
2517 rtw89_info(rtwdev, "<---\n");
2518 }
2519
mac_is_txq_empty_be(struct rtw89_dev * rtwdev)2520 static bool mac_is_txq_empty_be(struct rtw89_dev *rtwdev)
2521 {
2522 struct rtw89_mac_dle_dfi_qempty qempty;
2523 u32 val32, msk32;
2524 u32 grpnum;
2525 int ret;
2526 int i;
2527
2528 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
2529 qempty.dle_type = DLE_CTRL_TYPE_WDE;
2530
2531 for (i = 0; i < grpnum; i++) {
2532 qempty.grpsel = i;
2533 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
2534 if (ret) {
2535 rtw89_warn(rtwdev,
2536 "%s: failed to dle dfi acq empty: %d\n",
2537 __func__, ret);
2538 return false;
2539 }
2540
2541 /* Each acq group contains 32 queues (8 macid * 4 acq),
2542 * but here, we can simply check if all bits are set.
2543 */
2544 if (qempty.qempty != MASKDWORD)
2545 return false;
2546 }
2547
2548 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
2549 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
2550 if (ret) {
2551 rtw89_warn(rtwdev, "%s: failed to dle dfi mgq empty: %d\n",
2552 __func__, ret);
2553 return false;
2554 }
2555
2556 msk32 = B_CMAC0_MGQ_NORMAL_BE | B_CMAC1_MGQ_NORMAL_BE;
2557 if ((qempty.qempty & msk32) != msk32)
2558 return false;
2559
2560 msk32 = B_BE_WDE_EMPTY_QUE_OTHERS;
2561 val32 = rtw89_read32(rtwdev, R_BE_DLE_EMPTY0);
2562 return (val32 & msk32) == msk32;
2563 }
2564
2565 const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
2566 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET,
2567 .filter_model_addr = R_BE_FILTER_MODEL_ADDR,
2568 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY,
2569 .mem_base_addrs = rtw89_mac_mem_base_addrs_be,
2570 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_BE,
2571 .rx_fltr = R_BE_RX_FLTR_OPT,
2572 .port_base = &rtw89_port_base_be,
2573 .agg_len_ht = R_BE_AGG_LEN_HT_0,
2574 .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL,
2575
2576 .muedca_ctrl = {
2577 .addr = R_BE_MUEDCA_EN,
2578 .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0,
2579 },
2580 .bfee_ctrl = {
2581 .addr = R_BE_BFMEE_RESP_OPTION,
2582 .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN |
2583 B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN,
2584 },
2585 .narrow_bw_ru_dis = {
2586 .addr = R_BE_RXTRIG_TEST_USER_2,
2587 .mask = B_BE_RXTRIG_RU26_DIS,
2588 },
2589 .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,},
2590 .agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,},
2591 .txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,},
2592
2593 .check_mac_en = rtw89_mac_check_mac_en_be,
2594 .sys_init = sys_init_be,
2595 .trx_init = trx_init_be,
2596 .hci_func_en = rtw89_mac_hci_func_en_be,
2597 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be,
2598 .dle_func_en = dle_func_en_be,
2599 .dle_clk_en = dle_clk_en_be,
2600 .bf_assoc = rtw89_mac_bf_assoc_be,
2601
2602 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be,
2603 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be,
2604 .cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be,
2605
2606 .dle_mix_cfg = dle_mix_cfg_be,
2607 .chk_dle_rdy = chk_dle_rdy_be,
2608 .dle_buf_req = dle_buf_req_be,
2609 .hfc_func_en = hfc_func_en_be,
2610 .hfc_h2c_cfg = hfc_h2c_cfg_be,
2611 .hfc_mix_cfg = hfc_mix_cfg_be,
2612 .hfc_get_mix_info = hfc_get_mix_info_be,
2613 .wde_quota_cfg = wde_quota_cfg_be,
2614 .ple_quota_cfg = ple_quota_cfg_be,
2615 .set_cpuio = set_cpuio_be,
2616 .dle_quota_change = dle_quota_change_be,
2617
2618 .disable_cpu = rtw89_mac_disable_cpu_be,
2619 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
2620 .fwdl_get_status = fwdl_get_status_be,
2621 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be,
2622 .fwdl_secure_idmem_share_mode = NULL,
2623 .parse_efuse_map = rtw89_parse_efuse_map_be,
2624 .parse_phycap_map = rtw89_parse_phycap_map_be,
2625 .cnv_efuse_state = rtw89_cnv_efuse_state_be,
2626 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be,
2627
2628 .cfg_plt = rtw89_mac_cfg_plt_be,
2629 .get_plt_cnt = rtw89_mac_get_plt_cnt_be,
2630
2631 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be,
2632
2633 .write_xtal_si = rtw89_mac_write_xtal_si_be,
2634 .read_xtal_si = rtw89_mac_read_xtal_si_be,
2635
2636 .dump_qta_lost = rtw89_mac_dump_qta_lost_be,
2637 .dump_err_status = rtw89_mac_dump_err_status_be,
2638
2639 .is_txq_empty = mac_is_txq_empty_be,
2640
2641 .prep_chan_list = rtw89_hw_scan_prep_chan_list_be,
2642 .free_chan_list = rtw89_hw_scan_free_chan_list_be,
2643 .add_chan_list = rtw89_hw_scan_add_chan_list_be,
2644 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_be,
2645 .scan_offload = rtw89_fw_h2c_scan_offload_be,
2646
2647 .wow_config_mac = rtw89_wow_config_mac_be,
2648 };
2649 EXPORT_SYMBOL(rtw89_mac_gen_be);
2650