1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
4 *
5 * Based on tc358764.c by
6 * Andrzej Hajda <a.hajda@samsung.com>
7 * Maciej Purski <m.purski@samsung.com>
8 *
9 * Based on rpi_touchscreen.c by
10 * Eric Anholt <eric@anholt.net>
11 */
12
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/regulator/consumer.h>
18
19 #include <video/mipi_display.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
28
29 /* PPI layer registers */
30 #define PPI_STARTPPI 0x0104 /* START control bit */
31 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
32 #define PPI_D0S_ATMR 0x0144
33 #define PPI_D1S_ATMR 0x0148
34 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
36 #define PPI_START_FUNCTION 1
37
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
41 #define DSI_RX_START 1
42
43 /* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */
44 #define LCDCTRL 0x0420 /* Video Path Control */
45 #define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */
46 #define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */
47 #define LCDCTRL_UNK6 BIT(6) /* Unknown */
48 #define LCDCTRL_EVTMODE BIT(5) /* Event mode */
49 #define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */
50 #define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
51 #define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */
52 #define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
53 #define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */
54
55 /* SPI Master Registers */
56 #define SPICMR 0x0450
57 #define SPITCR 0x0454
58
59 /* System Controller Registers */
60 #define SYSCTRL 0x0464
61
62 /* System registers */
63 #define LPX_PERIOD 3
64
65 /* Lane enable PPI and DSI register bits */
66 #define LANEENABLE_CLEN BIT(0)
67 #define LANEENABLE_L0EN BIT(1)
68 #define LANEENABLE_L1EN BIT(2)
69
70 struct tc358762 {
71 struct device *dev;
72 struct drm_bridge bridge;
73 struct regulator *regulator;
74 struct drm_bridge *panel_bridge;
75 struct gpio_desc *reset_gpio;
76 struct drm_display_mode mode;
77 bool pre_enabled;
78 int error;
79 };
80
tc358762_clear_error(struct tc358762 * ctx)81 static int tc358762_clear_error(struct tc358762 *ctx)
82 {
83 int ret = ctx->error;
84
85 ctx->error = 0;
86 return ret;
87 }
88
tc358762_write(struct tc358762 * ctx,u16 addr,u32 val)89 static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
90 {
91 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
92 ssize_t ret;
93 u8 data[6];
94
95 if (ctx->error)
96 return;
97
98 data[0] = addr;
99 data[1] = addr >> 8;
100 data[2] = val;
101 data[3] = val >> 8;
102 data[4] = val >> 16;
103 data[5] = val >> 24;
104
105 ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
106 if (ret < 0)
107 ctx->error = ret;
108 }
109
bridge_to_tc358762(struct drm_bridge * bridge)110 static inline struct tc358762 *bridge_to_tc358762(struct drm_bridge *bridge)
111 {
112 return container_of(bridge, struct tc358762, bridge);
113 }
114
tc358762_init(struct tc358762 * ctx)115 static int tc358762_init(struct tc358762 *ctx)
116 {
117 u32 lcdctrl;
118
119 tc358762_write(ctx, DSI_LANEENABLE,
120 LANEENABLE_L0EN | LANEENABLE_CLEN);
121 tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
122 tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
123 tc358762_write(ctx, PPI_D0S_ATMR, 0);
124 tc358762_write(ctx, PPI_D1S_ATMR, 0);
125 tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
126
127 tc358762_write(ctx, SPICMR, 0x00);
128
129 lcdctrl = LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 |
130 LCDCTRL_UNK6 | LCDCTRL_VTGEN;
131
132 if (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC)
133 lcdctrl |= LCDCTRL_HSPOL;
134
135 if (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC)
136 lcdctrl |= LCDCTRL_VSPOL;
137
138 tc358762_write(ctx, LCDCTRL, lcdctrl);
139
140 tc358762_write(ctx, SYSCTRL, 0x040f);
141 msleep(100);
142
143 tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
144 tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START);
145
146 msleep(100);
147
148 return tc358762_clear_error(ctx);
149 }
150
tc358762_post_disable(struct drm_bridge * bridge,struct drm_atomic_commit * state)151 static void tc358762_post_disable(struct drm_bridge *bridge,
152 struct drm_atomic_commit *state)
153 {
154 struct tc358762 *ctx = bridge_to_tc358762(bridge);
155 int ret;
156
157 /*
158 * The post_disable hook might be called multiple times.
159 * We want to avoid regulator imbalance below.
160 */
161 if (!ctx->pre_enabled)
162 return;
163
164 ctx->pre_enabled = false;
165
166 if (ctx->reset_gpio)
167 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
168
169 ret = regulator_disable(ctx->regulator);
170 if (ret < 0)
171 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
172 }
173
tc358762_pre_enable(struct drm_bridge * bridge,struct drm_atomic_commit * state)174 static void tc358762_pre_enable(struct drm_bridge *bridge,
175 struct drm_atomic_commit *state)
176 {
177 struct tc358762 *ctx = bridge_to_tc358762(bridge);
178 int ret;
179
180 ret = regulator_enable(ctx->regulator);
181 if (ret < 0)
182 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
183
184 if (ctx->reset_gpio) {
185 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
186 usleep_range(5000, 10000);
187 }
188
189 ctx->pre_enabled = true;
190 }
191
tc358762_enable(struct drm_bridge * bridge,struct drm_atomic_commit * state)192 static void tc358762_enable(struct drm_bridge *bridge,
193 struct drm_atomic_commit *state)
194 {
195 struct tc358762 *ctx = bridge_to_tc358762(bridge);
196 int ret;
197
198 ret = tc358762_init(ctx);
199 if (ret < 0)
200 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
201 }
202
tc358762_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)203 static int tc358762_attach(struct drm_bridge *bridge,
204 struct drm_encoder *encoder,
205 enum drm_bridge_attach_flags flags)
206 {
207 struct tc358762 *ctx = bridge_to_tc358762(bridge);
208
209 return drm_bridge_attach(encoder, ctx->panel_bridge,
210 bridge, flags);
211 }
212
tc358762_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj)213 static void tc358762_bridge_mode_set(struct drm_bridge *bridge,
214 const struct drm_display_mode *mode,
215 const struct drm_display_mode *adj)
216 {
217 struct tc358762 *ctx = bridge_to_tc358762(bridge);
218
219 drm_mode_copy(&ctx->mode, mode);
220 }
221
222 static const struct drm_bridge_funcs tc358762_bridge_funcs = {
223 .atomic_post_disable = tc358762_post_disable,
224 .atomic_pre_enable = tc358762_pre_enable,
225 .atomic_enable = tc358762_enable,
226 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
227 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
228 .atomic_create_state = drm_atomic_helper_bridge_create_state,
229 .attach = tc358762_attach,
230 .mode_set = tc358762_bridge_mode_set,
231 };
232
tc358762_parse_dt(struct tc358762 * ctx)233 static int tc358762_parse_dt(struct tc358762 *ctx)
234 {
235 struct drm_bridge *panel_bridge;
236 struct device *dev = ctx->dev;
237
238 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
239 if (IS_ERR(panel_bridge))
240 return PTR_ERR(panel_bridge);
241
242 ctx->panel_bridge = panel_bridge;
243
244 /* Reset GPIO is optional */
245 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
246 if (IS_ERR(ctx->reset_gpio))
247 return PTR_ERR(ctx->reset_gpio);
248
249 return 0;
250 }
251
tc358762_configure_regulators(struct tc358762 * ctx)252 static int tc358762_configure_regulators(struct tc358762 *ctx)
253 {
254 ctx->regulator = devm_regulator_get(ctx->dev, "vddc");
255 if (IS_ERR(ctx->regulator))
256 return PTR_ERR(ctx->regulator);
257
258 return 0;
259 }
260
tc358762_probe(struct mipi_dsi_device * dsi)261 static int tc358762_probe(struct mipi_dsi_device *dsi)
262 {
263 struct device *dev = &dsi->dev;
264 struct tc358762 *ctx;
265 int ret;
266
267 ctx = devm_drm_bridge_alloc(dev, struct tc358762, bridge,
268 &tc358762_bridge_funcs);
269 if (IS_ERR(ctx))
270 return PTR_ERR(ctx);
271
272 mipi_dsi_set_drvdata(dsi, ctx);
273
274 ctx->dev = dev;
275 ctx->pre_enabled = false;
276
277 /* TODO: Find out how to get dual-lane mode working */
278 dsi->lanes = 1;
279 dsi->format = MIPI_DSI_FMT_RGB888;
280 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
281 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_HSE;
282
283 ret = tc358762_parse_dt(ctx);
284 if (ret < 0)
285 return ret;
286
287 ret = tc358762_configure_regulators(ctx);
288 if (ret < 0)
289 return ret;
290
291 ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
292 ctx->bridge.of_node = dev->of_node;
293 ctx->bridge.pre_enable_prev_first = true;
294
295 ret = devm_drm_bridge_add(dev, &ctx->bridge);
296 if (ret < 0)
297 return ret;
298
299 ret = devm_mipi_dsi_attach(dev, dsi);
300 if (ret < 0)
301 dev_err(dev, "failed to attach dsi\n");
302
303 return ret;
304 }
305
306 static const struct of_device_id tc358762_of_match[] = {
307 { .compatible = "toshiba,tc358762" },
308 { }
309 };
310 MODULE_DEVICE_TABLE(of, tc358762_of_match);
311
312 static struct mipi_dsi_driver tc358762_driver = {
313 .probe = tc358762_probe,
314 .driver = {
315 .name = "tc358762",
316 .of_match_table = tc358762_of_match,
317 },
318 };
319 module_mipi_dsi_driver(tc358762_driver);
320
321 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
322 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358762 DSI/DPI Bridge");
323 MODULE_LICENSE("GPL v2");
324