1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include "mt76_connac.h"
5 #include "mt76_connac2_mac.h"
6 #include "dma.h"
7
8 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
9 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
10 IEEE80211_RADIOTAP_HE_##f)
11
mt76_connac_gen_ppe_thresh(u8 * he_ppet,int nss,enum nl80211_band band)12 void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss, enum nl80211_band band)
13 {
14 static const u8 ppet16_ppet8_ru3_ru0[] = { 0x1c, 0xc7, 0x71 };
15 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0xf;
16
17 if (band == NL80211_BAND_2GHZ)
18 ru_bit_mask = 0x3;
19
20 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) |
21 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK,
22 ru_bit_mask);
23
24 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE *
25 nss * hweight8(ru_bit_mask) * 2;
26 ppet_size = DIV_ROUND_UP(ppet_bits, 8);
27
28 for (i = 0; i < ppet_size - 1; i++)
29 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3];
30
31 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] &
32 (0xff >> (8 - (ppet_bits - 1) % 8));
33 }
34 EXPORT_SYMBOL_GPL(mt76_connac_gen_ppe_thresh);
35
mt76_connac_pm_wake(struct mt76_phy * phy,struct mt76_connac_pm * pm)36 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm)
37 {
38 struct mt76_dev *dev = phy->dev;
39
40 if (mt76_is_usb(dev))
41 return 0;
42
43 cancel_delayed_work_sync(&pm->ps_work);
44 if (!test_bit(MT76_STATE_PM, &phy->state))
45 return 0;
46
47 if (pm->suspended)
48 return 0;
49
50 queue_work(dev->wq, &pm->wake_work);
51 if (!wait_event_timeout(pm->wait,
52 !test_bit(MT76_STATE_PM, &phy->state),
53 3 * HZ)) {
54 ieee80211_wake_queues(phy->hw);
55 return -ETIMEDOUT;
56 }
57
58 return 0;
59 }
60 EXPORT_SYMBOL_GPL(mt76_connac_pm_wake);
61
mt76_connac_power_save_sched(struct mt76_phy * phy,struct mt76_connac_pm * pm)62 void mt76_connac_power_save_sched(struct mt76_phy *phy,
63 struct mt76_connac_pm *pm)
64 {
65 struct mt76_dev *dev = phy->dev;
66
67 if (mt76_is_usb(dev))
68 return;
69
70 if (!pm->enable)
71 return;
72
73 if (pm->suspended)
74 return;
75
76 pm->last_activity = jiffies;
77
78 if (!test_bit(MT76_STATE_PM, &phy->state)) {
79 cancel_delayed_work(&phy->mac_work);
80 queue_delayed_work(dev->wq, &pm->ps_work, pm->idle_timeout);
81 }
82 }
83 EXPORT_SYMBOL_GPL(mt76_connac_power_save_sched);
84
mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm * pm,struct mt76_wcid * wcid)85 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
86 struct mt76_wcid *wcid)
87 {
88 int i;
89
90 spin_lock_bh(&pm->txq_lock);
91 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
92 if (wcid && pm->tx_q[i].wcid != wcid)
93 continue;
94
95 dev_kfree_skb(pm->tx_q[i].skb);
96 pm->tx_q[i].skb = NULL;
97 }
98 spin_unlock_bh(&pm->txq_lock);
99 }
100 EXPORT_SYMBOL_GPL(mt76_connac_free_pending_tx_skbs);
101
mt76_connac_pm_queue_skb(struct ieee80211_hw * hw,struct mt76_connac_pm * pm,struct mt76_wcid * wcid,struct sk_buff * skb)102 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
103 struct mt76_connac_pm *pm,
104 struct mt76_wcid *wcid,
105 struct sk_buff *skb)
106 {
107 int qid = skb_get_queue_mapping(skb);
108 struct mt76_phy *phy = hw->priv;
109
110 spin_lock_bh(&pm->txq_lock);
111 if (!pm->tx_q[qid].skb) {
112 ieee80211_stop_queues(hw);
113 pm->tx_q[qid].wcid = wcid;
114 pm->tx_q[qid].skb = skb;
115 queue_work(phy->dev->wq, &pm->wake_work);
116 } else {
117 dev_kfree_skb(skb);
118 }
119 spin_unlock_bh(&pm->txq_lock);
120 }
121 EXPORT_SYMBOL_GPL(mt76_connac_pm_queue_skb);
122
mt76_connac_pm_dequeue_skbs(struct mt76_phy * phy,struct mt76_connac_pm * pm)123 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
124 struct mt76_connac_pm *pm)
125 {
126 int i;
127
128 spin_lock_bh(&pm->txq_lock);
129 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
130 struct mt76_wcid *wcid = pm->tx_q[i].wcid;
131 struct ieee80211_sta *sta = NULL;
132
133 if (!pm->tx_q[i].skb)
134 continue;
135
136 if (wcid && wcid->sta)
137 sta = container_of((void *)wcid, struct ieee80211_sta,
138 drv_priv);
139
140 mt76_tx(phy, sta, wcid, pm->tx_q[i].skb);
141 pm->tx_q[i].skb = NULL;
142 }
143 spin_unlock_bh(&pm->txq_lock);
144
145 mt76_worker_schedule(&phy->dev->tx_worker);
146 }
147 EXPORT_SYMBOL_GPL(mt76_connac_pm_dequeue_skbs);
148
mt76_connac_tx_complete_skb(struct mt76_dev * mdev,struct mt76_queue_entry * e)149 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
150 struct mt76_queue_entry *e)
151 {
152 if (!e->txwi) {
153 dev_kfree_skb_any(e->skb);
154 return;
155 }
156
157 if (e->skb)
158 mt76_tx_complete_skb(mdev, e->wcid, e->skb);
159 }
160 EXPORT_SYMBOL_GPL(mt76_connac_tx_complete_skb);
161
mt76_connac_write_hw_txp(struct mt76_dev * dev,struct mt76_tx_info * tx_info,void * txp_ptr,u32 id)162 void mt76_connac_write_hw_txp(struct mt76_dev *dev,
163 struct mt76_tx_info *tx_info,
164 void *txp_ptr, u32 id)
165 {
166 struct mt76_connac_hw_txp *txp = txp_ptr;
167 struct mt76_connac_txp_ptr *ptr = &txp->ptr[0];
168 int i, nbuf = tx_info->nbuf - 1;
169 u32 last_mask;
170
171 tx_info->buf[0].len = MT_TXD_SIZE + sizeof(*txp);
172 tx_info->nbuf = 1;
173
174 txp->msdu_id[0] = cpu_to_le16(id | MT_MSDU_ID_VALID);
175
176 if (is_mt7663(dev) || is_connac2(dev) || is_connac3(dev))
177 last_mask = MT_TXD_LEN_LAST;
178 else
179 last_mask = MT_TXD_LEN_AMSDU_LAST |
180 MT_TXD_LEN_MSDU_LAST;
181
182 for (i = 0; i < nbuf; i++) {
183 u16 len = tx_info->buf[i + 1].len & MT_TXD_LEN_MASK;
184 u32 addr = tx_info->buf[i + 1].addr;
185
186 if (i == nbuf - 1)
187 len |= last_mask;
188
189 if (i & 1) {
190 ptr->buf1 = cpu_to_le32(addr);
191 ptr->len1 = cpu_to_le16(len);
192 ptr++;
193 } else {
194 ptr->buf0 = cpu_to_le32(addr);
195 ptr->len0 = cpu_to_le16(len);
196 }
197 }
198 }
199 EXPORT_SYMBOL_GPL(mt76_connac_write_hw_txp);
200
201 static void
mt76_connac_txp_skb_unmap_fw(struct mt76_dev * mdev,struct mt76_connac_fw_txp * txp)202 mt76_connac_txp_skb_unmap_fw(struct mt76_dev *mdev,
203 struct mt76_connac_fw_txp *txp)
204 {
205 struct device *dev = is_connac_v1(mdev) ? mdev->dev : mdev->dma_dev;
206 int i;
207
208 for (i = 0; i < txp->nbuf; i++)
209 dma_unmap_single(dev, le32_to_cpu(txp->buf[i]),
210 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
211 }
212
213 static void
mt76_connac_txp_skb_unmap_hw(struct mt76_dev * dev,struct mt76_connac_hw_txp * txp)214 mt76_connac_txp_skb_unmap_hw(struct mt76_dev *dev,
215 struct mt76_connac_hw_txp *txp)
216 {
217 u32 last_mask;
218 int i;
219
220 if (is_mt7663(dev) || is_connac2(dev) || is_connac3(dev))
221 last_mask = MT_TXD_LEN_LAST;
222 else
223 last_mask = MT_TXD_LEN_MSDU_LAST;
224
225 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
226 struct mt76_connac_txp_ptr *ptr = &txp->ptr[i];
227 bool last;
228 u16 len;
229
230 len = le16_to_cpu(ptr->len0);
231 last = len & last_mask;
232 len &= MT_TXD_LEN_MASK;
233 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
234 DMA_TO_DEVICE);
235 if (last)
236 break;
237
238 len = le16_to_cpu(ptr->len1);
239 last = len & last_mask;
240 len &= MT_TXD_LEN_MASK;
241 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
242 DMA_TO_DEVICE);
243 if (last)
244 break;
245 }
246 }
247
mt76_connac_txp_skb_unmap(struct mt76_dev * dev,struct mt76_txwi_cache * t)248 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
249 struct mt76_txwi_cache *t)
250 {
251 struct mt76_connac_txp_common *txp;
252
253 txp = mt76_connac_txwi_to_txp(dev, t);
254 if (is_mt76_fw_txp(dev))
255 mt76_connac_txp_skb_unmap_fw(dev, &txp->fw);
256 else
257 mt76_connac_txp_skb_unmap_hw(dev, &txp->hw);
258 }
259 EXPORT_SYMBOL_GPL(mt76_connac_txp_skb_unmap);
260
mt76_connac_init_tx_queues(struct mt76_phy * phy,int idx,int n_desc,int ring_base,void * wed,u32 flags)261 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
262 int ring_base, void *wed, u32 flags)
263 {
264 int i, err;
265
266 err = mt76_init_tx_queue(phy, 0, idx, n_desc, ring_base,
267 wed, flags);
268 if (err < 0)
269 return err;
270
271 for (i = 1; i <= MT_TXQ_PSD; i++)
272 phy->q_tx[i] = phy->q_tx[0];
273
274 return 0;
275 }
276 EXPORT_SYMBOL_GPL(mt76_connac_init_tx_queues);
277
mt76_connac_set_txpower_cur(struct mt76_phy * phy,s8 max_power)278 void mt76_connac_set_txpower_cur(struct mt76_phy *phy, s8 max_power)
279 {
280 int delta;
281
282 delta = mt76_tx_power_path_delta(hweight16(phy->chainmask));
283 phy->txpower_cur = max_power - delta;
284 }
285 EXPORT_SYMBOL_GPL(mt76_connac_set_txpower_cur);
286
287 #define __bitrate_mask_check(_mcs, _mode) \
288 ({ \
289 u8 i = 0; \
290 for (nss = 0; i < ARRAY_SIZE(mask->control[band]._mcs); i++) { \
291 if (!mask->control[band]._mcs[i]) \
292 continue; \
293 if (hweight16(mask->control[band]._mcs[i]) == 1) { \
294 mode = MT_PHY_TYPE_##_mode; \
295 rateidx = ffs(mask->control[band]._mcs[i]) - 1; \
296 if (mode == MT_PHY_TYPE_HT) \
297 rateidx += 8 * i; \
298 else \
299 nss = i + 1; \
300 goto out; \
301 } \
302 } \
303 })
304
mt76_connac2_mac_tx_rate_val(struct mt76_phy * mphy,struct ieee80211_bss_conf * conf,bool beacon,bool mcast)305 u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,
306 struct ieee80211_bss_conf *conf,
307 bool beacon, bool mcast)
308 {
309 u8 nss = 0, mode = 0, band = NL80211_BAND_2GHZ;
310 int rateidx = 0, offset = 0, mcast_rate;
311 struct cfg80211_chan_def *chandef;
312 struct mt76_vif_link *mvif;
313
314 if (!conf)
315 goto legacy;
316
317 mvif = mt76_vif_conf_link(mphy->dev, conf->vif, conf);
318 chandef = mvif->ctx ? &mvif->ctx->def : &mphy->chandef;
319 band = chandef->chan->band;
320
321 if (is_connac2(mphy->dev)) {
322 rateidx = ffs(conf->basic_rates) - 1;
323 goto legacy;
324 }
325
326 if (beacon) {
327 struct cfg80211_bitrate_mask *mask;
328
329 mask = &conf->beacon_tx_rate;
330
331 __bitrate_mask_check(he_mcs, HE_SU);
332 __bitrate_mask_check(vht_mcs, VHT);
333 __bitrate_mask_check(ht_mcs, HT);
334
335 if (hweight32(mask->control[band].legacy) == 1) {
336 rateidx = ffs(mask->control[band].legacy) - 1;
337 goto legacy;
338 }
339 }
340
341 mcast_rate = conf->mcast_rate[band];
342 if (mcast && mcast_rate > 0)
343 rateidx = mcast_rate - 1;
344 else
345 rateidx = ffs(conf->basic_rates) - 1;
346
347 legacy:
348 if (band != NL80211_BAND_2GHZ)
349 offset = 4;
350
351 /* pick the lowest rate for hidden nodes */
352 if (rateidx < 0)
353 rateidx = 0;
354
355 rateidx += offset;
356 if (rateidx >= ARRAY_SIZE(mt76_rates))
357 rateidx = offset;
358
359 rateidx = mt76_rates[rateidx].hw_value;
360 mode = rateidx >> 8;
361 rateidx &= GENMASK(7, 0);
362 out:
363 return FIELD_PREP(MT_TX_RATE_NSS, nss) |
364 FIELD_PREP(MT_TX_RATE_IDX, rateidx) |
365 FIELD_PREP(MT_TX_RATE_MODE, mode);
366 }
367 EXPORT_SYMBOL_GPL(mt76_connac2_mac_tx_rate_val);
368
369 static void
mt76_connac2_mac_write_txwi_8023(__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid)370 mt76_connac2_mac_write_txwi_8023(__le32 *txwi, struct sk_buff *skb,
371 struct mt76_wcid *wcid)
372 {
373 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
374 u8 fc_type, fc_stype;
375 u16 ethertype;
376 bool wmm = false;
377 u32 val;
378
379 if (wcid->sta) {
380 struct ieee80211_sta *sta;
381
382 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv);
383 wmm = sta->wme;
384 }
385
386 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) |
387 FIELD_PREP(MT_TXD1_TID, tid);
388
389 ethertype = get_unaligned_be16(&skb->data[12]);
390 if (ethertype >= ETH_P_802_3_MIN)
391 val |= MT_TXD1_ETH_802_3;
392
393 txwi[1] |= cpu_to_le32(val);
394
395 fc_type = IEEE80211_FTYPE_DATA >> 2;
396 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0;
397
398 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
399 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype);
400
401 txwi[2] |= cpu_to_le32(val);
402
403 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
404 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
405
406 txwi[7] |= cpu_to_le32(val);
407 }
408
409 static void
mt76_connac2_mac_write_txwi_80211(struct mt76_dev * dev,__le32 * txwi,struct sk_buff * skb,struct ieee80211_key_conf * key)410 mt76_connac2_mac_write_txwi_80211(struct mt76_dev *dev, __le32 *txwi,
411 struct sk_buff *skb,
412 struct ieee80211_key_conf *key)
413 {
414 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
415 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
416 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
417 bool multicast = is_multicast_ether_addr(hdr->addr1);
418 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
419 __le16 fc = hdr->frame_control;
420 __le16 sc = hdr->seq_ctrl;
421 u8 fc_type, fc_stype;
422 u32 val;
423
424 if (ieee80211_is_action(fc) &&
425 skb->len >= IEEE80211_MIN_ACTION_SIZE(addba_req.capab) &&
426 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
427 mgmt->u.action.action_code == WLAN_ACTION_ADDBA_REQ) {
428 u16 capab = le16_to_cpu(mgmt->u.action.addba_req.capab);
429
430 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA);
431 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK;
432 } else if (ieee80211_is_back_req(hdr->frame_control)) {
433 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr;
434 u16 control = le16_to_cpu(bar->control);
435
436 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control);
437 }
438
439 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
440 FIELD_PREP(MT_TXD1_HDR_INFO,
441 ieee80211_get_hdrlen_from_skb(skb) / 2) |
442 FIELD_PREP(MT_TXD1_TID, tid);
443
444 txwi[1] |= cpu_to_le32(val);
445
446 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
447 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
448
449 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
450 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
451 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
452
453 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) &&
454 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
455 val |= MT_TXD2_BIP;
456 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME);
457 }
458
459 if (!ieee80211_is_data(fc) || multicast ||
460 info->flags & IEEE80211_TX_CTL_USE_MINRATE)
461 val |= MT_TXD2_FIX_RATE;
462
463 if (ieee80211_has_morefrags(fc) && ieee80211_is_first_frag(sc))
464 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_FIRST);
465 else if (ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc))
466 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_MID);
467 else if (!ieee80211_has_morefrags(fc) && !ieee80211_is_first_frag(sc))
468 val |= FIELD_PREP(MT_TXD2_FRAG, MT_TX_FRAG_LAST);
469
470 txwi[2] |= cpu_to_le32(val);
471
472 if (ieee80211_is_beacon(fc)) {
473 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT);
474 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT);
475 }
476
477 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
478 u16 seqno = le16_to_cpu(sc);
479
480 if (ieee80211_is_back_req(hdr->frame_control)) {
481 struct ieee80211_bar *bar;
482
483 bar = (struct ieee80211_bar *)skb->data;
484 seqno = le16_to_cpu(bar->start_seq_num);
485 }
486
487 val = MT_TXD3_SN_VALID |
488 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
489 txwi[3] |= cpu_to_le32(val);
490 txwi[7] &= ~cpu_to_le32(MT_TXD7_HW_AMSDU);
491 }
492
493 if (mt76_is_mmio(dev)) {
494 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
495 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
496 txwi[7] |= cpu_to_le32(val);
497 } else {
498 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
499 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
500 txwi[8] |= cpu_to_le32(val);
501 }
502 }
503
mt76_connac2_mac_write_txwi(struct mt76_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,struct ieee80211_key_conf * key,int pid,enum mt76_txq_id qid,u32 changed)504 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
505 struct sk_buff *skb, struct mt76_wcid *wcid,
506 struct ieee80211_key_conf *key, int pid,
507 enum mt76_txq_id qid, u32 changed)
508 {
509 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
510 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
511 struct ieee80211_vif *vif = info->control.vif;
512 struct mt76_phy *mphy = &dev->phy;
513 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0, band_idx = 0;
514 u32 val, sz_txd = mt76_is_mmio(dev) ? MT_TXD_SIZE : MT_SDIO_TXD_SIZE;
515 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
516 bool beacon = !!(changed & (BSS_CHANGED_BEACON |
517 BSS_CHANGED_BEACON_ENABLED));
518 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP |
519 BSS_CHANGED_FILS_DISCOVERY));
520 bool amsdu_en = wcid->amsdu;
521
522 if (vif) {
523 struct mt76_vif_link *mvif = (struct mt76_vif_link *)vif->drv_priv;
524
525 omac_idx = mvif->omac_idx;
526 wmm_idx = mvif->wmm_idx;
527 band_idx = mvif->band_idx;
528 }
529
530 if (phy_idx && dev->phys[MT_BAND1])
531 mphy = dev->phys[MT_BAND1];
532
533 if (inband_disc) {
534 p_fmt = MT_TX_TYPE_FW;
535 q_idx = MT_LMAC_ALTX0;
536 } else if (beacon) {
537 p_fmt = MT_TX_TYPE_FW;
538 q_idx = MT_LMAC_BCN0;
539 } else if (qid >= MT_TXQ_PSD) {
540 p_fmt = mt76_is_mmio(dev) ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
541 q_idx = MT_LMAC_ALTX0;
542 } else {
543 p_fmt = mt76_is_mmio(dev) ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
544 q_idx = wmm_idx * MT76_CONNAC_MAX_WMM_SETS +
545 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb));
546
547 /* mt7915 WA only counts WED path */
548 if (is_mt7915(dev) && mtk_wed_device_active(&dev->mmio.wed))
549 wcid->stats.tx_packets++;
550 }
551
552 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
553 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) |
554 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
555 txwi[0] = cpu_to_le32(val);
556
557 val = MT_TXD1_LONG_FORMAT |
558 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
559 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
560 if (!is_connac2(dev))
561 val |= MT_TXD1_VTA;
562 if (phy_idx || band_idx)
563 val |= MT_TXD1_TGID;
564
565 txwi[1] = cpu_to_le32(val);
566 txwi[2] = 0;
567
568 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 15);
569 if (!is_connac2(dev))
570 val |= MT_TXD3_SW_POWER_MGMT;
571 if (key)
572 val |= MT_TXD3_PROTECT_FRAME;
573 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
574 val |= MT_TXD3_NO_ACK;
575
576 txwi[3] = cpu_to_le32(val);
577 txwi[4] = 0;
578
579 val = FIELD_PREP(MT_TXD5_PID, pid);
580 if (pid >= MT_PACKET_ID_FIRST) {
581 val |= MT_TXD5_TX_STATUS_HOST;
582 amsdu_en = 0;
583 }
584
585 txwi[5] = cpu_to_le32(val);
586 txwi[6] = 0;
587 txwi[7] = amsdu_en ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0;
588
589 if (is_8023)
590 mt76_connac2_mac_write_txwi_8023(txwi, skb, wcid);
591 else
592 mt76_connac2_mac_write_txwi_80211(dev, txwi, skb, key);
593
594 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) {
595 /* Fixed rata is available just for 802.11 txd */
596 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
597 bool multicast = ieee80211_is_data(hdr->frame_control) &&
598 is_multicast_ether_addr(hdr->addr1);
599 u16 rate = mt76_connac2_mac_tx_rate_val(mphy,
600 vif ? &vif->bss_conf : NULL,
601 beacon, multicast);
602 u32 val = MT_TXD6_FIXED_BW;
603
604 /* hardware won't add HTC for mgmt/ctrl frame */
605 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD);
606
607 val |= FIELD_PREP(MT_TXD6_TX_RATE, rate);
608 txwi[6] |= cpu_to_le32(val);
609 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
610
611 if (!is_connac2(dev)) {
612 u8 spe_idx = mt76_connac_spe_idx(mphy->antenna_mask);
613
614 if (!spe_idx)
615 spe_idx = 24 + phy_idx;
616 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, spe_idx));
617 }
618
619 txwi[7] &= ~cpu_to_le32(MT_TXD7_HW_AMSDU);
620 }
621 }
622 EXPORT_SYMBOL_GPL(mt76_connac2_mac_write_txwi);
623
mt76_connac2_mac_fill_txs(struct mt76_dev * dev,struct mt76_wcid * wcid,__le32 * txs_data)624 bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
625 __le32 *txs_data)
626 {
627 struct mt76_sta_stats *stats = &wcid->stats;
628 struct ieee80211_supported_band *sband;
629 struct mt76_phy *mphy;
630 struct rate_info rate = {};
631 bool cck = false;
632 u32 txrate, txs, mode, stbc;
633
634 txs = le32_to_cpu(txs_data[0]);
635
636 /* PPDU based reporting */
637 if (mtk_wed_device_active(&dev->mmio.wed) &&
638 FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) {
639 stats->tx_bytes +=
640 le32_get_bits(txs_data[5], MT_TXS5_MPDU_TX_BYTE) -
641 le32_get_bits(txs_data[7], MT_TXS7_MPDU_RETRY_BYTE);
642 stats->tx_failed +=
643 le32_get_bits(txs_data[6], MT_TXS6_MPDU_FAIL_CNT);
644 stats->tx_retries +=
645 le32_get_bits(txs_data[7], MT_TXS7_MPDU_RETRY_CNT);
646
647 if (wcid->sta) {
648 struct ieee80211_sta *sta;
649 u8 tid;
650
651 sta = container_of((void *)wcid, struct ieee80211_sta,
652 drv_priv);
653 tid = FIELD_GET(MT_TXS0_TID, txs);
654
655 ieee80211_refresh_tx_agg_session_timer(sta, tid);
656 }
657 }
658
659 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs);
660
661 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate);
662 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1;
663 stbc = FIELD_GET(MT_TX_RATE_STBC, txrate);
664
665 if (stbc && rate.nss > 1)
666 rate.nss >>= 1;
667
668 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss))
669 stats->tx_nss[rate.nss - 1]++;
670 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs))
671 stats->tx_mcs[rate.mcs]++;
672
673 mode = FIELD_GET(MT_TX_RATE_MODE, txrate);
674 switch (mode) {
675 case MT_PHY_TYPE_CCK:
676 cck = true;
677 fallthrough;
678 case MT_PHY_TYPE_OFDM:
679 mphy = &dev->phy;
680 if (wcid->phy_idx == MT_BAND1 && dev->phys[MT_BAND1])
681 mphy = dev->phys[MT_BAND1];
682
683 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
684 sband = &mphy->sband_5g.sband;
685 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)
686 sband = &mphy->sband_6g.sband;
687 else
688 sband = &mphy->sband_2g.sband;
689
690 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck);
691 rate.legacy = sband->bitrates[rate.mcs].bitrate;
692 break;
693 case MT_PHY_TYPE_HT:
694 case MT_PHY_TYPE_HT_GF:
695 if (rate.mcs > 31)
696 return false;
697
698 rate.flags = RATE_INFO_FLAGS_MCS;
699 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI)
700 rate.flags |= RATE_INFO_FLAGS_SHORT_GI;
701 break;
702 case MT_PHY_TYPE_VHT:
703 if (rate.mcs > 9)
704 return false;
705
706 rate.flags = RATE_INFO_FLAGS_VHT_MCS;
707 break;
708 case MT_PHY_TYPE_HE_SU:
709 case MT_PHY_TYPE_HE_EXT_SU:
710 case MT_PHY_TYPE_HE_TB:
711 case MT_PHY_TYPE_HE_MU:
712 if (rate.mcs > 11)
713 return false;
714
715 rate.he_gi = wcid->rate.he_gi;
716 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate);
717 rate.flags = RATE_INFO_FLAGS_HE_MCS;
718 break;
719 default:
720 return false;
721 }
722
723 stats->tx_mode[mode]++;
724
725 switch (FIELD_GET(MT_TXS0_BW, txs)) {
726 case IEEE80211_STA_RX_BW_160:
727 rate.bw = RATE_INFO_BW_160;
728 stats->tx_bw[3]++;
729 break;
730 case IEEE80211_STA_RX_BW_80:
731 rate.bw = RATE_INFO_BW_80;
732 stats->tx_bw[2]++;
733 break;
734 case IEEE80211_STA_RX_BW_40:
735 rate.bw = RATE_INFO_BW_40;
736 stats->tx_bw[1]++;
737 break;
738 default:
739 rate.bw = RATE_INFO_BW_20;
740 stats->tx_bw[0]++;
741 break;
742 }
743 wcid->rate = rate;
744
745 return true;
746 }
747 EXPORT_SYMBOL_GPL(mt76_connac2_mac_fill_txs);
748
mt76_connac2_mac_add_txs_skb(struct mt76_dev * dev,struct mt76_wcid * wcid,int pid,__le32 * txs_data)749 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
750 int pid, __le32 *txs_data)
751 {
752 struct sk_buff_head list;
753 struct sk_buff *skb;
754
755 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) == MT_TXS_PPDU_FMT)
756 return false;
757
758 mt76_tx_status_lock(dev, &list);
759 skb = mt76_tx_status_skb_get(dev, wcid, pid, &list);
760 if (skb) {
761 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
762
763 if (!(le32_to_cpu(txs_data[0]) & MT_TXS0_ACK_ERROR_MASK))
764 info->flags |= IEEE80211_TX_STAT_ACK;
765
766 info->status.ampdu_len = 1;
767 info->status.ampdu_ack_len =
768 !!(info->flags & IEEE80211_TX_STAT_ACK);
769 info->status.rates[0].idx = -1;
770
771 mt76_connac2_mac_fill_txs(dev, wcid, txs_data);
772 mt76_tx_status_skb_done(dev, skb, &list);
773 }
774 mt76_tx_status_unlock(dev, &list);
775
776 return !!skb;
777 }
778 EXPORT_SYMBOL_GPL(mt76_connac2_mac_add_txs_skb);
779
780 static void
mt76_connac2_mac_decode_he_radiotap_ru(struct mt76_rx_status * status,struct ieee80211_radiotap_he * he,__le32 * rxv)781 mt76_connac2_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
782 struct ieee80211_radiotap_he *he,
783 __le32 *rxv)
784 {
785 u32 ru_h, ru_l;
786 u8 ru, offs = 0;
787
788 ru_l = le32_get_bits(rxv[0], MT_PRXV_HE_RU_ALLOC_L);
789 ru_h = le32_get_bits(rxv[1], MT_PRXV_HE_RU_ALLOC_H);
790 ru = (u8)(ru_l | ru_h << 4);
791
792 status->bw = RATE_INFO_BW_HE_RU;
793
794 switch (ru) {
795 case 0 ... 36:
796 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
797 offs = ru;
798 break;
799 case 37 ... 52:
800 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
801 offs = ru - 37;
802 break;
803 case 53 ... 60:
804 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
805 offs = ru - 53;
806 break;
807 case 61 ... 64:
808 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
809 offs = ru - 61;
810 break;
811 case 65 ... 66:
812 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
813 offs = ru - 65;
814 break;
815 case 67:
816 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
817 break;
818 case 68:
819 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
820 break;
821 }
822
823 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
824 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
825 le16_encode_bits(offs,
826 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
827 }
828
829 static void
mt76_connac2_mac_decode_he_mu_radiotap(struct mt76_dev * dev,struct sk_buff * skb,__le32 * rxv)830 mt76_connac2_mac_decode_he_mu_radiotap(struct mt76_dev *dev, struct sk_buff *skb,
831 __le32 *rxv)
832 {
833 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
834 static struct ieee80211_radiotap_he_mu mu_known = {
835 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) |
836 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) |
837 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) |
838 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN),
839 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN),
840 };
841 struct ieee80211_radiotap_he_mu *he_mu;
842
843 if (is_connac2(dev)) {
844 mu_known.flags1 |= HE_BITS(MU_FLAGS1_SIG_B_COMP_KNOWN);
845 mu_known.flags2 |= HE_BITS(MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN);
846 }
847
848 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
849
850 he_mu = skb_push(skb, sizeof(mu_known));
851 memcpy(he_mu, &mu_known, sizeof(mu_known));
852
853 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f)
854
855 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx);
856 if (status->he_dcm)
857 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm);
858
859 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) |
860 MU_PREP(FLAGS2_SIG_B_SYMS_USERS,
861 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER));
862
863 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0);
864
865 if (status->bw >= RATE_INFO_BW_40) {
866 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN);
867 he_mu->ru_ch2[0] =
868 le32_get_bits(rxv[3], MT_CRXV_HE_RU1);
869 }
870
871 if (status->bw >= RATE_INFO_BW_80) {
872 he_mu->ru_ch1[1] =
873 le32_get_bits(rxv[3], MT_CRXV_HE_RU2);
874 he_mu->ru_ch2[1] =
875 le32_get_bits(rxv[3], MT_CRXV_HE_RU3);
876 }
877 }
878
mt76_connac2_mac_decode_he_radiotap(struct mt76_dev * dev,struct sk_buff * skb,__le32 * rxv,u32 mode)879 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
880 struct sk_buff *skb,
881 __le32 *rxv, u32 mode)
882 {
883 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
884 static const struct ieee80211_radiotap_he known = {
885 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
886 HE_BITS(DATA1_DATA_DCM_KNOWN) |
887 HE_BITS(DATA1_STBC_KNOWN) |
888 HE_BITS(DATA1_CODING_KNOWN) |
889 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
890 HE_BITS(DATA1_DOPPLER_KNOWN) |
891 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
892 HE_BITS(DATA1_BSS_COLOR_KNOWN),
893 .data2 = HE_BITS(DATA2_GI_KNOWN) |
894 HE_BITS(DATA2_TXBF_KNOWN) |
895 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
896 HE_BITS(DATA2_TXOP_KNOWN),
897 };
898 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1;
899 struct ieee80211_radiotap_he *he;
900
901 status->flag |= RX_FLAG_RADIOTAP_HE;
902
903 he = skb_push(skb, sizeof(known));
904 memcpy(he, &known, sizeof(known));
905
906 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) |
907 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]);
908 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
909 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) |
910 le16_encode_bits(ltf_size,
911 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
912 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF)
913 he->data5 |= HE_BITS(DATA5_TXBF);
914 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) |
915 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]);
916
917 switch (mode) {
918 case MT_PHY_TYPE_HE_SU:
919 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
920 HE_BITS(DATA1_UL_DL_KNOWN) |
921 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
922 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
923
924 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) |
925 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
926 break;
927 case MT_PHY_TYPE_HE_EXT_SU:
928 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
929 HE_BITS(DATA1_UL_DL_KNOWN) |
930 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
931
932 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
933 break;
934 case MT_PHY_TYPE_HE_MU:
935 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
936 HE_BITS(DATA1_UL_DL_KNOWN);
937
938 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
939 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]);
940
941 mt76_connac2_mac_decode_he_radiotap_ru(status, he, rxv);
942 mt76_connac2_mac_decode_he_mu_radiotap(dev, skb, rxv);
943 break;
944 case MT_PHY_TYPE_HE_TB:
945 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
946 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
947 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
948 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
949
950 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) |
951 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) |
952 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) |
953 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]);
954
955 mt76_connac2_mac_decode_he_radiotap_ru(status, he, rxv);
956 break;
957 default:
958 break;
959 }
960 }
961 EXPORT_SYMBOL_GPL(mt76_connac2_mac_decode_he_radiotap);
962
963 /* The HW does not translate the mac header to 802.3 for mesh point */
mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif * vif,struct sk_buff * skb,u16 hdr_offset)964 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
965 struct sk_buff *skb, u16 hdr_offset)
966 {
967 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
968 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_offset);
969 __le32 *rxd = (__le32 *)skb->data;
970 struct ieee80211_sta *sta;
971 struct ieee80211_hdr hdr;
972 u16 frame_control;
973
974 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) !=
975 MT_RXD3_NORMAL_U2M)
976 return -EINVAL;
977
978 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4))
979 return -EINVAL;
980
981 sta = container_of((void *)status->wcid, struct ieee80211_sta, drv_priv);
982
983 /* store the info from RXD and ethhdr to avoid being overridden */
984 frame_control = le32_get_bits(rxd[6], MT_RXD6_FRAME_CONTROL);
985 hdr.frame_control = cpu_to_le16(frame_control);
986 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_SEQ_CTRL));
987 hdr.duration_id = 0;
988
989 ether_addr_copy(hdr.addr1, vif->addr);
990 ether_addr_copy(hdr.addr2, sta->addr);
991 switch (frame_control & (IEEE80211_FCTL_TODS |
992 IEEE80211_FCTL_FROMDS)) {
993 case 0:
994 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid);
995 break;
996 case IEEE80211_FCTL_FROMDS:
997 ether_addr_copy(hdr.addr3, eth_hdr->h_source);
998 break;
999 case IEEE80211_FCTL_TODS:
1000 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
1001 break;
1002 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS:
1003 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
1004 ether_addr_copy(hdr.addr4, eth_hdr->h_source);
1005 break;
1006 default:
1007 return -EINVAL;
1008 }
1009
1010 skb_pull(skb, hdr_offset + sizeof(struct ethhdr) - 2);
1011 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) ||
1012 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX))
1013 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header);
1014 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN)
1015 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header);
1016 else
1017 skb_pull(skb, 2);
1018
1019 if (ieee80211_has_order(hdr.frame_control))
1020 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[9],
1021 IEEE80211_HT_CTL_LEN);
1022 if (ieee80211_is_data_qos(hdr.frame_control)) {
1023 __le16 qos_ctrl;
1024
1025 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_QOS_CTL));
1026 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl,
1027 IEEE80211_QOS_CTL_LEN);
1028 }
1029
1030 if (ieee80211_has_a4(hdr.frame_control))
1031 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr));
1032 else
1033 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6);
1034
1035 return 0;
1036 }
1037 EXPORT_SYMBOL_GPL(mt76_connac2_reverse_frag0_hdr_trans);
1038
mt76_connac2_mac_fill_rx_rate(struct mt76_dev * dev,struct mt76_rx_status * status,struct ieee80211_supported_band * sband,__le32 * rxv,u8 * mode)1039 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
1040 struct mt76_rx_status *status,
1041 struct ieee80211_supported_band *sband,
1042 __le32 *rxv, u8 *mode)
1043 {
1044 u32 v0, v2;
1045 u8 stbc, gi, bw, dcm, nss;
1046 int i, idx;
1047 bool cck = false;
1048
1049 v0 = le32_to_cpu(rxv[0]);
1050 v2 = le32_to_cpu(rxv[2]);
1051
1052 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
1053 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;
1054
1055 if (!is_mt7915(dev)) {
1056 stbc = FIELD_GET(MT_PRXV_HT_STBC, v0);
1057 gi = FIELD_GET(MT_PRXV_HT_SGI, v0);
1058 *mode = FIELD_GET(MT_PRXV_TX_MODE, v0);
1059 if (is_connac2(dev))
1060 dcm = !!(idx & MT_PRXV_TX_DCM);
1061 else
1062 dcm = FIELD_GET(MT_PRXV_DCM, v0);
1063 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0);
1064 } else {
1065 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
1066 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
1067 *mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
1068 dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM);
1069 bw = FIELD_GET(MT_CRXV_FRAME_MODE, v2);
1070 }
1071
1072 /* the hardware reports NSTS; report the data NSS for STBC frames */
1073 if (stbc && nss > 1)
1074 nss >>= 1;
1075
1076 switch (*mode) {
1077 case MT_PHY_TYPE_CCK:
1078 cck = true;
1079 fallthrough;
1080 case MT_PHY_TYPE_OFDM:
1081 i = mt76_get_rate(dev, sband, i, cck);
1082 break;
1083 case MT_PHY_TYPE_HT_GF:
1084 case MT_PHY_TYPE_HT:
1085 status->encoding = RX_ENC_HT;
1086 if (gi)
1087 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1088 if (i > 31)
1089 return -EINVAL;
1090 break;
1091 case MT_PHY_TYPE_VHT:
1092 status->nss = nss;
1093 status->encoding = RX_ENC_VHT;
1094 if (gi)
1095 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1096 if (i > 11)
1097 return -EINVAL;
1098 break;
1099 case MT_PHY_TYPE_HE_MU:
1100 case MT_PHY_TYPE_HE_SU:
1101 case MT_PHY_TYPE_HE_EXT_SU:
1102 case MT_PHY_TYPE_HE_TB:
1103 status->nss = nss;
1104 status->encoding = RX_ENC_HE;
1105 i &= GENMASK(3, 0);
1106
1107 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
1108 status->he_gi = gi;
1109
1110 status->he_dcm = dcm;
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115 status->rate_idx = i;
1116
1117 switch (bw) {
1118 case IEEE80211_STA_RX_BW_20:
1119 break;
1120 case IEEE80211_STA_RX_BW_40:
1121 if (*mode == MT_PHY_TYPE_HE_EXT_SU &&
1122 (idx & MT_PRXV_TX_ER_SU_106T)) {
1123 status->bw = RATE_INFO_BW_HE_RU;
1124 status->he_ru =
1125 NL80211_RATE_INFO_HE_RU_ALLOC_106;
1126 } else {
1127 status->bw = RATE_INFO_BW_40;
1128 }
1129 break;
1130 case IEEE80211_STA_RX_BW_80:
1131 status->bw = RATE_INFO_BW_80;
1132 break;
1133 case IEEE80211_STA_RX_BW_160:
1134 status->bw = RATE_INFO_BW_160;
1135 break;
1136 default:
1137 return -EINVAL;
1138 }
1139
1140 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
1141 if (*mode < MT_PHY_TYPE_HE_SU && gi)
1142 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1143
1144 return 0;
1145 }
1146 EXPORT_SYMBOL_GPL(mt76_connac2_mac_fill_rx_rate);
1147
mt76_connac2_tx_check_aggr(struct ieee80211_sta * sta,__le32 * txwi)1148 void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
1149 {
1150 struct mt76_wcid *wcid;
1151 u16 fc, tid;
1152 u32 val;
1153
1154 if (!sta ||
1155 !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he))
1156 return;
1157
1158 tid = le32_get_bits(txwi[1], MT_TXD1_TID);
1159
1160 val = le32_to_cpu(txwi[2]);
1161 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
1162 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
1163 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
1164 return;
1165
1166 wcid = (struct mt76_wcid *)sta->drv_priv;
1167 if (!test_and_set_bit(tid, &wcid->ampdu_state)) {
1168 if (ieee80211_start_tx_ba_session(sta, tid, 0))
1169 clear_bit(tid, &wcid->ampdu_state);
1170 }
1171 }
1172 EXPORT_SYMBOL_GPL(mt76_connac2_tx_check_aggr);
1173
mt76_connac2_txwi_free(struct mt76_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_sta * sta,struct list_head * free_list)1174 void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t,
1175 struct ieee80211_sta *sta,
1176 struct list_head *free_list)
1177 {
1178 struct mt76_wcid *wcid;
1179 __le32 *txwi;
1180 u16 wcid_idx;
1181
1182 mt76_connac_txp_skb_unmap(dev, t);
1183 if (!t->skb)
1184 goto out;
1185
1186 txwi = (__le32 *)mt76_get_txwi_ptr(dev, t);
1187 if (sta) {
1188 wcid = (struct mt76_wcid *)sta->drv_priv;
1189 wcid_idx = wcid->idx;
1190 } else {
1191 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX);
1192 wcid = __mt76_wcid_ptr(dev, wcid_idx);
1193
1194 if (wcid && wcid->sta) {
1195 sta = container_of((void *)wcid, struct ieee80211_sta,
1196 drv_priv);
1197 mt76_wcid_add_poll(dev, wcid);
1198 }
1199 }
1200
1201 if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
1202 mt76_connac2_tx_check_aggr(sta, txwi);
1203
1204 __mt76_tx_complete_skb(dev, wcid_idx, t->skb, free_list);
1205 out:
1206 t->skb = NULL;
1207 mt76_put_txwi(dev, t);
1208 }
1209 EXPORT_SYMBOL_GPL(mt76_connac2_txwi_free);
1210
mt76_connac2_tx_token_put(struct mt76_dev * dev)1211 void mt76_connac2_tx_token_put(struct mt76_dev *dev)
1212 {
1213 struct mt76_txwi_cache *txwi;
1214 int id;
1215
1216 spin_lock_bh(&dev->token_lock);
1217 idr_for_each_entry(&dev->token, txwi, id) {
1218 mt76_connac2_txwi_free(dev, txwi, NULL, NULL);
1219 dev->token_count--;
1220 }
1221 spin_unlock_bh(&dev->token_lock);
1222 idr_destroy(&dev->token);
1223
1224 for (id = 0; id < __MT_MAX_BAND; id++) {
1225 struct mt76_phy *phy = dev->phys[id];
1226 if (phy)
1227 atomic_set(&phy->mgmt_tx_pending, 0);
1228 }
1229 }
1230 EXPORT_SYMBOL_GPL(mt76_connac2_tx_token_put);
1231