1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399-op1.dtsi" 10 11/ { 12 aliases { 13 mmc0 = &sdmmc; 14 mmc1 = &sdhci; 15 }; 16 17 chosen { 18 stdout-path = "serial2:115200n8"; 19 }; 20 21 firmware { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 }; 25 26 /* 27 * Power Tree 28 * 29 * In general an attempt is made to include all rails called out by 30 * the schematic as long as those rails interact in some way with 31 * the AP. AKA: 32 * - Rails that only connect to the EC (or devices that the EC talks to) 33 * are not included. 34 * - Rails _are_ included if the rails go to the AP even if the AP 35 * doesn't currently care about them / they are always on. The idea 36 * here is that it makes it easier to map to the schematic or extend 37 * later. 38 * 39 * If two rails are substantially the same from the AP's point of 40 * view, though, we won't create a full fixed regulator. We'll just 41 * put the child rail as an alias of the parent rail. Sometimes rails 42 * look the same to the AP because one of these is true: 43 * - The EC controls the enable and the EC always enables a rail as 44 * long as the AP is running. 45 * - The rails are actually connected to each other by a jumper and 46 * the distinction is just there to add clarity/flexibility to the 47 * schematic. 48 */ 49 50 ppvar_sys: regulator-ppvar-sys { 51 compatible = "regulator-fixed"; 52 regulator-name = "ppvar_sys"; 53 regulator-always-on; 54 regulator-boot-on; 55 }; 56 57 pp1200_lpddr: regulator-pp1200-lpddr { 58 compatible = "regulator-fixed"; 59 regulator-name = "pp1200_lpddr"; 60 61 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <1200000>; 65 regulator-max-microvolt = <1200000>; 66 67 vin-supply = <&ppvar_sys>; 68 }; 69 70 pp1800: regulator-pp1800 { 71 compatible = "regulator-fixed"; 72 regulator-name = "pp1800"; 73 74 /* Always on when ppvar_sys shows power good */ 75 regulator-always-on; 76 regulator-boot-on; 77 regulator-min-microvolt = <1800000>; 78 regulator-max-microvolt = <1800000>; 79 80 vin-supply = <&ppvar_sys>; 81 }; 82 83 pp3300: regulator-pp3300 { 84 compatible = "regulator-fixed"; 85 regulator-name = "pp3300"; 86 87 /* Always on; plain and simple */ 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 93 vin-supply = <&ppvar_sys>; 94 }; 95 96 pp5000: regulator-pp5000 { 97 compatible = "regulator-fixed"; 98 regulator-name = "pp5000"; 99 100 /* EC turns on w/ pp5000_en; always on for AP */ 101 regulator-always-on; 102 regulator-boot-on; 103 regulator-min-microvolt = <5000000>; 104 regulator-max-microvolt = <5000000>; 105 106 vin-supply = <&ppvar_sys>; 107 }; 108 109 ppvar_bigcpu_pwm: regulator-ppvar-bigcpu-pwm { 110 compatible = "pwm-regulator"; 111 regulator-name = "ppvar_bigcpu_pwm"; 112 113 pwms = <&pwm1 0 3337 0>; 114 pwm-supply = <&ppvar_sys>; 115 pwm-dutycycle-range = <100 0>; 116 pwm-dutycycle-unit = <100>; 117 118 /* EC turns on w/ ap_core_en; always on for AP */ 119 regulator-always-on; 120 regulator-boot-on; 121 regulator-min-microvolt = <800107>; 122 regulator-max-microvolt = <1302232>; 123 }; 124 125 ppvar_bigcpu: ppvar-bigcpu { 126 compatible = "vctrl-regulator"; 127 regulator-name = "ppvar_bigcpu"; 128 129 regulator-min-microvolt = <800107>; 130 regulator-max-microvolt = <1302232>; 131 132 ctrl-supply = <&ppvar_bigcpu_pwm>; 133 ctrl-voltage-range = <800107 1302232>; 134 135 regulator-settling-time-up-us = <322>; 136 }; 137 138 ppvar_litcpu_pwm: regulator-ppvar-litcpu-pwm { 139 compatible = "pwm-regulator"; 140 regulator-name = "ppvar_litcpu_pwm"; 141 142 pwms = <&pwm2 0 3337 0>; 143 pwm-supply = <&ppvar_sys>; 144 pwm-dutycycle-range = <100 0>; 145 pwm-dutycycle-unit = <100>; 146 147 /* EC turns on w/ ap_core_en; always on for AP */ 148 regulator-always-on; 149 regulator-boot-on; 150 regulator-min-microvolt = <797743>; 151 regulator-max-microvolt = <1307837>; 152 }; 153 154 ppvar_litcpu: ppvar-litcpu { 155 compatible = "vctrl-regulator"; 156 regulator-name = "ppvar_litcpu"; 157 158 regulator-min-microvolt = <797743>; 159 regulator-max-microvolt = <1307837>; 160 161 ctrl-supply = <&ppvar_litcpu_pwm>; 162 ctrl-voltage-range = <797743 1307837>; 163 164 regulator-settling-time-up-us = <384>; 165 }; 166 167 ppvar_gpu_pwm: regulator-ppvar-gpu-pwm { 168 compatible = "pwm-regulator"; 169 regulator-name = "ppvar_gpu_pwm"; 170 171 pwms = <&pwm0 0 3337 0>; 172 pwm-supply = <&ppvar_sys>; 173 pwm-dutycycle-range = <100 0>; 174 pwm-dutycycle-unit = <100>; 175 176 /* EC turns on w/ ap_core_en; always on for AP */ 177 regulator-always-on; 178 regulator-boot-on; 179 regulator-min-microvolt = <786384>; 180 regulator-max-microvolt = <1217747>; 181 }; 182 183 ppvar_gpu: ppvar-gpu { 184 compatible = "vctrl-regulator"; 185 regulator-name = "ppvar_gpu"; 186 187 regulator-min-microvolt = <786384>; 188 regulator-max-microvolt = <1217747>; 189 190 ctrl-supply = <&ppvar_gpu_pwm>; 191 ctrl-voltage-range = <786384 1217747>; 192 193 regulator-settling-time-up-us = <390>; 194 }; 195 196 /* EC turns on w/ pp900_ddrpll_en */ 197 pp900_ddrpll: regulator-pp900-ap { 198 }; 199 200 /* EC turns on w/ pp900_pll_en */ 201 pp900_pll: regulator-pp900-ap { 202 }; 203 204 /* EC turns on w/ pp900_pmu_en */ 205 pp900_pmu: regulator-pp900-ap { 206 }; 207 208 /* EC turns on w/ pp1800_s0_en_l */ 209 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: regulator-pp1800 { 210 }; 211 212 /* EC turns on w/ pp1800_avdd_en_l */ 213 pp1800_avdd: regulator-pp1800 { 214 }; 215 216 /* EC turns on w/ pp1800_lid_en_l */ 217 pp1800_lid: pp1800_mic: regulator-pp1800 { 218 }; 219 220 /* EC turns on w/ lpddr_pwr_en */ 221 pp1800_lpddr: regulator-pp1800 { 222 }; 223 224 /* EC turns on w/ pp1800_pmu_en_l */ 225 pp1800_pmu: regulator-pp1800 { 226 }; 227 228 /* EC turns on w/ pp1800_usb_en_l */ 229 pp1800_usb: regulator-pp1800 { 230 }; 231 232 pp3000_sd_slot: regulator-pp3000-sd-slot { 233 compatible = "regulator-fixed"; 234 regulator-name = "pp3000_sd_slot"; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&sd_slot_pwr_en>; 237 238 enable-active-high; 239 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 240 241 vin-supply = <&pp3000>; 242 }; 243 244 /* 245 * Technically, this is a small abuse of 'regulator-gpio'; this 246 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 247 * always on though, so it is sufficient to simply control the mux 248 * here. 249 */ 250 ppvar_sd_card_io: ppvar-sd-card-io { 251 compatible = "regulator-gpio"; 252 regulator-name = "ppvar_sd_card_io"; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 255 256 enable-active-high; 257 enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; 258 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 259 states = <1800000 0x1>, 260 <3000000 0x0>; 261 262 regulator-min-microvolt = <1800000>; 263 regulator-max-microvolt = <3000000>; 264 }; 265 266 /* EC turns on w/ pp3300_trackpad_en_l */ 267 pp3300_trackpad: regulator-pp3300-trackpad { 268 }; 269 270 /* EC turns on w/ usb_a_en */ 271 pp5000_usb_a_vbus: regulator-pp5000 { 272 }; 273 274 ap_rtc_clk: ap-rtc-clk { 275 compatible = "fixed-clock"; 276 clock-frequency = <32768>; 277 clock-output-names = "xin32k"; 278 #clock-cells = <0>; 279 }; 280 281 max98357a: max98357a { 282 compatible = "maxim,max98357a"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&sdmode_en>; 285 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 286 sdmode-delay = <2>; 287 #sound-dai-cells = <0>; 288 status = "okay"; 289 }; 290 291 sound: sound { 292 compatible = "rockchip,rk3399-gru-sound"; 293 rockchip,cpu = <&i2s0 &spdif>; 294 }; 295}; 296 297&cdn_dp { 298 status = "okay"; 299}; 300 301/* 302 * Set some suspend operating points to avoid OVP in suspend 303 * 304 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 305 * from wherever they're at back to the "default" operating point (whatever 306 * voltage we get when we set the PWM pins to "input"). 307 * 308 * This quick transition under light load has the possibility to trigger the 309 * regulator "over voltage protection" (OVP). 310 * 311 * To make extra certain that we don't hit this OVP at suspend time, we'll 312 * transition to a voltage that's much closer to the default (~1.0 V) so that 313 * there will not be a big jump. Technically we only need to get within 200 mV 314 * of the default voltage, but the speed here should be fast enough and we need 315 * suspend/resume to be rock solid. 316 */ 317 318&cluster0_opp { 319 opp05 { 320 opp-suspend; 321 }; 322}; 323 324&cluster1_opp { 325 opp06 { 326 opp-suspend; 327 }; 328}; 329 330&cpu_l0 { 331 cpu-supply = <&ppvar_litcpu>; 332}; 333 334&cpu_l1 { 335 cpu-supply = <&ppvar_litcpu>; 336}; 337 338&cpu_l2 { 339 cpu-supply = <&ppvar_litcpu>; 340}; 341 342&cpu_l3 { 343 cpu-supply = <&ppvar_litcpu>; 344}; 345 346&cpu_b0 { 347 cpu-supply = <&ppvar_bigcpu>; 348}; 349 350&cpu_b1 { 351 cpu-supply = <&ppvar_bigcpu>; 352}; 353 354 355&cru { 356 assigned-clocks = 357 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 358 <&cru PLL_NPLL>, 359 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 360 <&cru PCLK_PERIHP>, 361 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 362 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 363 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 364 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 365 <&cru ACLK_GIC_PRE>, 366 <&cru PCLK_DDR>; 367 assigned-clock-rates = 368 <600000000>, <800000000>, 369 <1000000000>, 370 <150000000>, <75000000>, 371 <37500000>, 372 <100000000>, <100000000>, 373 <50000000>, <800000000>, 374 <100000000>, <50000000>, 375 <400000000>, <400000000>, 376 <200000000>, 377 <200000000>; 378}; 379 380&dfi { 381 status = "okay"; 382}; 383 384&dmc { 385 status = "okay"; 386 387 rockchip,pd-idle-ns = <160>; 388 rockchip,sr-idle-ns = <10240>; 389 rockchip,sr-mc-gate-idle-ns = <40960>; 390 rockchip,srpd-lite-idle-ns = <61440>; 391 rockchip,standby-idle-ns = <81920>; 392 393 rockchip,ddr3_odt_dis_freq = <666000000>; 394 rockchip,lpddr3_odt_dis_freq = <666000000>; 395 rockchip,lpddr4_odt_dis_freq = <666000000>; 396 397 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; 398 rockchip,srpd-lite-idle-dis-freq-hz = <0>; 399 rockchip,standby-idle-dis-freq-hz = <928000000>; 400}; 401 402&dmc_opp_table { 403 opp03 { 404 opp-suspend; 405 }; 406}; 407 408&emmc_phy { 409 status = "okay"; 410}; 411 412&gpu { 413 mali-supply = <&ppvar_gpu>; 414 status = "okay"; 415}; 416 417ap_i2c_ts: &i2c3 { 418 status = "okay"; 419 420 clock-frequency = <400000>; 421 422 /* These are relatively safe rise/fall times */ 423 i2c-scl-falling-time-ns = <50>; 424 i2c-scl-rising-time-ns = <300>; 425}; 426 427ap_i2c_audio: &i2c8 { 428 status = "okay"; 429 430 clock-frequency = <400000>; 431 432 /* These are relatively safe rise/fall times */ 433 i2c-scl-falling-time-ns = <50>; 434 i2c-scl-rising-time-ns = <300>; 435 436 codec: da7219@1a { 437 compatible = "dlg,da7219"; 438 reg = <0x1a>; 439 interrupt-parent = <&gpio1>; 440 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 441 clocks = <&cru SCLK_I2S_8CH_OUT>; 442 clock-names = "mclk"; 443 dlg,micbias-lvl = <2600>; 444 dlg,mic-amp-in-sel = "diff"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&headset_int_l>; 447 VDD-supply = <&pp1800>; 448 VDDMIC-supply = <&pp3300>; 449 VDDIO-supply = <&pp1800>; 450 451 da7219_aad { 452 dlg,adc-1bit-rpt = <1>; 453 dlg,btn-avg = <4>; 454 dlg,btn-cfg = <50>; 455 dlg,mic-det-thr = <500>; 456 dlg,jack-ins-deb = <20>; 457 dlg,jack-det-rate = "32_64"; 458 dlg,jack-rem-deb = <1>; 459 460 dlg,a-d-btn-thr = <0xa>; 461 dlg,d-b-btn-thr = <0x16>; 462 dlg,b-c-btn-thr = <0x21>; 463 dlg,c-mic-btn-thr = <0x3E>; 464 }; 465 }; 466}; 467 468&i2s0 { 469 status = "okay"; 470}; 471 472&io_domains { 473 status = "okay"; 474 475 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 476 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 477 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 478 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 479}; 480 481&pcie0 { 482 status = "okay"; 483 484 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 487 vpcie3v3-supply = <&pp3300_wifi_bt>; 488 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 489 vpcie0v9-supply = <&pp900_pcie>; 490 491 pci_rootport: pcie@0,0 { 492 reg = <0x0000 0 0 0 0>; 493 #address-cells = <3>; 494 #size-cells = <2>; 495 ranges; 496 device_type = "pci"; 497 }; 498}; 499 500&pcie_phy { 501 status = "okay"; 502}; 503 504&pmu_io_domains { 505 status = "okay"; 506 507 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 508}; 509 510&pwm0 { 511 status = "okay"; 512}; 513 514&pwm1 { 515 status = "okay"; 516}; 517 518&pwm2 { 519 status = "okay"; 520}; 521 522&pwm3 { 523 status = "okay"; 524}; 525 526&sdhci { 527 /* 528 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 529 * same (or nearly the same) performance for all eMMC that are intended 530 * to be used. 531 */ 532 assigned-clock-rates = <150000000>; 533 534 bus-width = <8>; 535 mmc-hs400-1_8v; 536 mmc-hs400-enhanced-strobe; 537 non-removable; 538 status = "okay"; 539}; 540 541&sdmmc { 542 status = "okay"; 543 544 /* 545 * Note: configure "sdmmc_cd" as card detect even though it's actually 546 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 547 * should be ignoring card detect anyway. Specifying the pin as 548 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 549 * turned on that the system will still make sure the port is 550 * configured as SDMMC and not JTAG. 551 */ 552 pinctrl-names = "default"; 553 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin 554 &sdmmc_bus4>; 555 556 bus-width = <4>; 557 cap-mmc-highspeed; 558 cap-sd-highspeed; 559 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 560 disable-wp; 561 sd-uhs-sdr12; 562 sd-uhs-sdr25; 563 sd-uhs-sdr50; 564 sd-uhs-sdr104; 565 vmmc-supply = <&pp3000_sd_slot>; 566 vqmmc-supply = <&ppvar_sd_card_io>; 567}; 568 569&spdif { 570 status = "okay"; 571 572 /* 573 * SPDIF is routed internally to DP; we either don't use these pins, or 574 * mux them to something else. 575 */ 576 /delete-property/ pinctrl-0; 577 /delete-property/ pinctrl-names; 578}; 579 580&spi1 { 581 status = "okay"; 582 583 pinctrl-names = "default", "sleep"; 584 pinctrl-1 = <&spi1_sleep>; 585 586 flash@0 { 587 compatible = "jedec,spi-nor"; 588 reg = <0>; 589 590 /* May run faster once verified. */ 591 spi-max-frequency = <10000000>; 592 }; 593}; 594 595&spi2 { 596 status = "okay"; 597}; 598 599&spi5 { 600 status = "okay"; 601 602 cros_ec: ec@0 { 603 compatible = "google,cros-ec-spi"; 604 reg = <0>; 605 interrupt-parent = <&gpio0>; 606 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&ec_ap_int_l>; 609 spi-max-frequency = <3000000>; 610 611 i2c_tunnel: i2c-tunnel { 612 compatible = "google,cros-ec-i2c-tunnel"; 613 google,remote-bus = <4>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 }; 617 618 usbc_extcon0: extcon0 { 619 compatible = "google,extcon-usbc-cros-ec"; 620 google,usb-port-id = <0>; 621 }; 622 }; 623}; 624 625&tsadc { 626 status = "okay"; 627 628 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 629 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 630}; 631 632&tcphy0 { 633 status = "okay"; 634 extcon = <&usbc_extcon0>; 635}; 636 637&u2phy0 { 638 status = "okay"; 639}; 640 641&u2phy0_host { 642 status = "okay"; 643}; 644 645&u2phy1_host { 646 status = "okay"; 647}; 648 649&u2phy0_otg { 650 status = "okay"; 651}; 652 653&u2phy1_otg { 654 status = "okay"; 655}; 656 657&uart2 { 658 status = "okay"; 659}; 660 661&usb_host0_ohci { 662 status = "okay"; 663}; 664 665&usbdrd3_0 { 666 status = "okay"; 667 extcon = <&usbc_extcon0>; 668}; 669 670&usbdrd_dwc3_0 { 671 status = "okay"; 672 dr_mode = "host"; 673}; 674 675&vopb { 676 status = "okay"; 677}; 678 679&vopb_mmu { 680 status = "okay"; 681}; 682 683&vopl { 684 status = "okay"; 685}; 686 687&vopl_mmu { 688 status = "okay"; 689}; 690 691#include <arm/cros-ec-keyboard.dtsi> 692#include <arm/cros-ec-sbs.dtsi> 693 694&pinctrl { 695 /* 696 * pinctrl settings for pins that have no real owners. 697 * 698 * At the moment settings are identical for S0 and S3, but if we later 699 * need to configure things differently for S3 we'll adjust here. 700 */ 701 pinctrl-names = "default"; 702 pinctrl-0 = < 703 &ap_pwroff /* AP will auto-assert this when in S3 */ 704 &clk_32k /* This pin is always 32k on gru boards */ 705 >; 706 707 pcfg_output_low: pcfg-output-low { 708 output-low; 709 }; 710 711 pcfg_output_high: pcfg-output-high { 712 output-high; 713 }; 714 715 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 716 bias-disable; 717 drive-strength = <8>; 718 }; 719 720 backlight-enable { 721 bl_en: bl-en { 722 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 723 }; 724 }; 725 726 cros-ec { 727 ec_ap_int_l: ec-ap-int-l { 728 rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 729 }; 730 }; 731 732 discretes { 733 sd_io_pwr_en: sd-io-pwr-en { 734 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO 735 &pcfg_pull_none>; 736 }; 737 738 sd_pwr_1800_sel: sd-pwr-1800-sel { 739 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 740 &pcfg_pull_none>; 741 }; 742 743 sd_slot_pwr_en: sd-slot-pwr-en { 744 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO 745 &pcfg_pull_none>; 746 }; 747 }; 748 749 codec { 750 /* Has external pullup */ 751 headset_int_l: headset-int-l { 752 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 753 }; 754 755 mic_int: mic-int { 756 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; 757 }; 758 }; 759 760 max98357a { 761 sdmode_en: sdmode-en { 762 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 763 }; 764 }; 765 766 pcie { 767 pcie_clkreqn_cpm: pci-clkreqn-cpm { 768 /* 769 * Since our pcie doesn't support ClockPM(CPM), we want 770 * to hack this as gpio, so the EP could be able to 771 * de-assert it along and make ClockPM(CPM) work. 772 */ 773 rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 774 }; 775 }; 776 777 sdmmc { 778 /* 779 * We run sdmmc at max speed; bump up drive strength. 780 * We also have external pulls, so disable the internal ones. 781 */ 782 sdmmc_bus4: sdmmc-bus4 { 783 rockchip,pins = 784 <4 RK_PB0 1 &pcfg_pull_none_8ma>, 785 <4 RK_PB1 1 &pcfg_pull_none_8ma>, 786 <4 RK_PB2 1 &pcfg_pull_none_8ma>, 787 <4 RK_PB3 1 &pcfg_pull_none_8ma>; 788 }; 789 790 sdmmc_clk: sdmmc-clk { 791 rockchip,pins = 792 <4 RK_PB4 1 &pcfg_pull_none_8ma>; 793 }; 794 795 sdmmc_cmd: sdmmc-cmd { 796 rockchip,pins = 797 <4 RK_PB5 1 &pcfg_pull_none_8ma>; 798 }; 799 800 /* 801 * In our case the official card detect is hooked to ground 802 * to avoid getting access to JTAG just by sticking something 803 * in the SD card slot (see the force_jtag bit in the TRM). 804 * 805 * We still configure it as card detect because it doesn't 806 * hurt and dw_mmc will ignore it. We make sure to disable 807 * the pull though so we don't burn needless power. 808 */ 809 sdmmc_cd: sdmmc-cd { 810 rockchip,pins = 811 <0 RK_PA7 1 &pcfg_pull_none>; 812 }; 813 814 /* This is where we actually hook up CD; has external pull */ 815 sdmmc_cd_pin: sdmmc-cd-pin { 816 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 817 }; 818 }; 819 820 spi1 { 821 spi1_sleep: spi1-sleep { 822 /* 823 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 824 * prevent leakage. 825 */ 826 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, 827 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, 828 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, 829 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 830 }; 831 }; 832 833 touchscreen { 834 touch_int_l: touch-int-l { 835 rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 836 }; 837 838 touch_reset_l: touch-reset-l { 839 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 840 }; 841 }; 842 843 trackpad { 844 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 845 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; 846 }; 847 848 trackpad_int_l: trackpad-int-l { 849 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 850 }; 851 }; 852 853 wifi: wifi { 854 wlan_module_reset_l: wlan-module-reset-l { 855 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 856 }; 857 858 bt_host_wake_l: bt-host-wake-l { 859 /* Kevin has an external pull up, but Gru does not */ 860 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 861 }; 862 }; 863 864 write-protect { 865 ap_fw_wp: ap-fw-wp { 866 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 867 }; 868 }; 869}; 870