1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Chunhui Dai <chunhui.dai@mediatek.com>
5 */
6
7 #include "phy-mtk-hdmi.h"
8 #include "phy-mtk-io.h"
9
10 #define HDMI_CON0 0x00
11 #define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)
12 #define RG_HDMITX_EN_SER_MASK GENMASK(15, 12)
13 #define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16)
14 #define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20)
15 #define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24)
16 #define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28)
17
18 #define HDMI_CON1 0x04
19 #define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18)
20 #define RG_HDMITX_PRED_IMP BIT(22)
21 #define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26)
22
23 #define HDMI_CON2 0x08
24 #define RG_HDMITX_EN_TX_CKLDO BIT(0)
25 #define RG_HDMITX_EN_TX_POSDIV BIT(1)
26 #define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3)
27 #define RG_HDMITX_EN_MBIAS BIT(6)
28 #define RG_HDMITX_MBIAS_LPF_EN BIT(7)
29
30 #define HDMI_CON4 0x10
31 #define RG_HDMITX_RESERVE_MASK GENMASK(31, 0)
32
33 #define HDMI_CON6 0x18
34 #define RG_HTPLL_BR_MASK GENMASK(1, 0)
35 #define RG_HTPLL_BC_MASK GENMASK(3, 2)
36 #define RG_HTPLL_BP_MASK GENMASK(7, 4)
37 #define RG_HTPLL_IR_MASK GENMASK(11, 8)
38 #define RG_HTPLL_IC_MASK GENMASK(15, 12)
39 #define RG_HTPLL_POSDIV_MASK GENMASK(17, 16)
40 #define RG_HTPLL_PREDIV_MASK GENMASK(19, 18)
41 #define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20)
42 #define RG_HTPLL_RLH_EN BIT(22)
43 #define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24)
44 #define RG_HTPLL_EN BIT(31)
45
46 #define HDMI_CON7 0x1c
47 #define RG_HTPLL_AUTOK_EN BIT(23)
48 #define RG_HTPLL_DIVEN_MASK GENMASK(30, 28)
49
mtk_hdmi_pll_prepare(struct clk_hw * hw)50 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
51 {
52 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
53 void __iomem *base = hdmi_phy->regs;
54
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
59 usleep_range(80, 100);
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
63 usleep_range(80, 100);
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
68 usleep_range(80, 100);
69 return 0;
70 }
71
mtk_hdmi_pll_unprepare(struct clk_hw * hw)72 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
73 {
74 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
75 void __iomem *base = hdmi_phy->regs;
76
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
81 usleep_range(80, 100);
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
85 usleep_range(80, 100);
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
87 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
88 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
89 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
90 usleep_range(80, 100);
91 }
92
mtk_hdmi_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)93 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
94 unsigned long parent_rate)
95 {
96 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
97 void __iomem *base = hdmi_phy->regs;
98 u32 pos_div;
99
100 if (rate <= 64000000)
101 pos_div = 3;
102 else if (rate <= 128000000)
103 pos_div = 2;
104 else
105 pos_div = 1;
106
107 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);
108 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
109 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
110 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);
111 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);
112 mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);
113 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);
114 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);
115 mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);
116 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);
117 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);
118 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);
119
120 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);
121 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);
122 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
123 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);
124 mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);
125 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);
126 return 0;
127 }
128
mtk_hdmi_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)129 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
130 unsigned long parent_rate)
131 {
132 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
133 unsigned long out_rate, val;
134 u32 tmp;
135
136 tmp = readl(hdmi_phy->regs + HDMI_CON6);
137 val = FIELD_GET(RG_HTPLL_PREDIV_MASK, tmp);
138 switch (val) {
139 case 0x00:
140 out_rate = parent_rate;
141 break;
142 case 0x01:
143 out_rate = parent_rate / 2;
144 break;
145 default:
146 out_rate = parent_rate / 4;
147 break;
148 }
149
150 val = FIELD_GET(RG_HTPLL_FBKDIV_MASK, tmp);
151 out_rate *= (val + 1) * 2;
152
153 tmp = readl(hdmi_phy->regs + HDMI_CON2);
154 val = FIELD_GET(RG_HDMITX_TX_POSDIV_MASK, tmp);
155 out_rate >>= val;
156
157 if (tmp & RG_HDMITX_EN_TX_POSDIV)
158 out_rate /= 5;
159
160 return out_rate;
161 }
162
163 static const struct clk_ops mtk_hdmi_phy_pll_ops = {
164 .prepare = mtk_hdmi_pll_prepare,
165 .unprepare = mtk_hdmi_pll_unprepare,
166 .set_rate = mtk_hdmi_pll_set_rate,
167 .determine_rate = clk_determine_rate_noop,
168 .recalc_rate = mtk_hdmi_pll_recalc_rate,
169 };
170
mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy * hdmi_phy)171 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
172 {
173 void __iomem *base = hdmi_phy->regs;
174
175 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
176 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
177 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
178 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
179 usleep_range(80, 100);
180 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
181 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
182 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
183 usleep_range(80, 100);
184 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
185 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
186 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
187 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
188 usleep_range(80, 100);
189 }
190
mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy * hdmi_phy)191 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
192 {
193 void __iomem *base = hdmi_phy->regs;
194
195 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
196 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
197 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
198 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
199 usleep_range(80, 100);
200 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
201 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
202 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
203 usleep_range(80, 100);
204 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
205 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
206 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
207 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
208 usleep_range(80, 100);
209 }
210
211 struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
212 .flags = CLK_SET_RATE_GATE,
213 .pll_default_off = true,
214 .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
215 .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
216 .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
217 };
218
219 MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
220 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
221 MODULE_LICENSE("GPL v2");
222