1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RISC-V performance counter support.
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 *
7 * This implementation is based on old RISC-V perf and ARM perf event code
8 * which are in turn based on sparc64 and x86 code.
9 */
10
11 #include <linux/perf/riscv_pmu.h>
12 #include <linux/platform_device.h>
13
14 #define RISCV_PMU_LEGACY_CYCLE 0
15 #define RISCV_PMU_LEGACY_INSTRET 2
16
17 static bool pmu_init_done;
18
pmu_legacy_ctr_get_idx(struct perf_event * event)19 static int pmu_legacy_ctr_get_idx(struct perf_event *event)
20 {
21 struct perf_event_attr *attr = &event->attr;
22
23 if (event->attr.type != PERF_TYPE_HARDWARE)
24 return -ENOENT;
25 if (attr->config == PERF_COUNT_HW_CPU_CYCLES)
26 return RISCV_PMU_LEGACY_CYCLE;
27 else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)
28 return RISCV_PMU_LEGACY_INSTRET;
29 else
30 return -ENOENT;
31 }
32
33 /* For legacy config & counter index are same */
pmu_legacy_event_map(struct perf_event * event,u64 * config)34 static int pmu_legacy_event_map(struct perf_event *event, u64 *config)
35 {
36 return pmu_legacy_ctr_get_idx(event);
37 }
38
39 /* cycle & instret are always 64 bit, one bit less according to SBI spec */
pmu_legacy_ctr_get_width(int idx)40 static int pmu_legacy_ctr_get_width(int idx)
41 {
42 return 63;
43 }
44
pmu_legacy_read_ctr(struct perf_event * event)45 static u64 pmu_legacy_read_ctr(struct perf_event *event)
46 {
47 struct hw_perf_event *hwc = &event->hw;
48 int idx = hwc->idx;
49 u64 val;
50
51 if (idx == RISCV_PMU_LEGACY_CYCLE) {
52 val = riscv_pmu_ctr_read_csr(CSR_CYCLE);
53 if (IS_ENABLED(CONFIG_32BIT))
54 val = (u64)riscv_pmu_ctr_read_csr(CSR_CYCLEH) << 32 | val;
55 } else if (idx == RISCV_PMU_LEGACY_INSTRET) {
56 val = riscv_pmu_ctr_read_csr(CSR_INSTRET);
57 if (IS_ENABLED(CONFIG_32BIT))
58 val = ((u64)riscv_pmu_ctr_read_csr(CSR_INSTRETH)) << 32 | val;
59 } else
60 return 0;
61
62 return val;
63 }
64
pmu_legacy_ctr_start(struct perf_event * event,u64 ival)65 static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival)
66 {
67 struct hw_perf_event *hwc = &event->hw;
68 u64 initial_val = pmu_legacy_read_ctr(event);
69
70 /**
71 * The legacy method doesn't really have a start/stop method.
72 * It also can not update the counter with a initial value.
73 * But we still need to set the prev_count so that read() can compute
74 * the delta. Just use the current counter value to set the prev_count.
75 */
76 local64_set(&hwc->prev_count, initial_val);
77 }
78
pmu_legacy_csr_index(struct perf_event * event)79 static uint8_t pmu_legacy_csr_index(struct perf_event *event)
80 {
81 return event->hw.idx;
82 }
83
pmu_legacy_event_mapped(struct perf_event * event,struct mm_struct * mm)84 static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm)
85 {
86 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
87 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
88 return;
89
90 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
91 }
92
pmu_legacy_event_unmapped(struct perf_event * event,struct mm_struct * mm)93 static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm)
94 {
95 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
96 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
97 return;
98
99 event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
100 }
101
102 /*
103 * This is just a simple implementation to allow legacy implementations
104 * compatible with new RISC-V PMU driver framework.
105 * This driver only allows reading two counters i.e CYCLE & INSTRET.
106 * However, it can not start or stop the counter. Thus, it is not very useful
107 * will be removed in future.
108 */
pmu_legacy_init(struct riscv_pmu * pmu)109 static void pmu_legacy_init(struct riscv_pmu *pmu)
110 {
111 pr_info("Legacy PMU implementation is available\n");
112
113 bitmap_zero(pmu->cmask, RISCV_MAX_COUNTERS);
114 set_bit(RISCV_PMU_LEGACY_CYCLE, pmu->cmask);
115 set_bit(RISCV_PMU_LEGACY_INSTRET, pmu->cmask);
116 pmu->ctr_start = pmu_legacy_ctr_start;
117 pmu->ctr_stop = NULL;
118 pmu->event_map = pmu_legacy_event_map;
119 pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;
120 pmu->ctr_get_width = pmu_legacy_ctr_get_width;
121 pmu->ctr_clear_idx = NULL;
122 pmu->ctr_read = pmu_legacy_read_ctr;
123 pmu->event_mapped = pmu_legacy_event_mapped;
124 pmu->event_unmapped = pmu_legacy_event_unmapped;
125 pmu->csr_index = pmu_legacy_csr_index;
126 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
127 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
128
129 perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
130 }
131
pmu_legacy_device_probe(struct platform_device * pdev)132 static int pmu_legacy_device_probe(struct platform_device *pdev)
133 {
134 struct riscv_pmu *pmu = NULL;
135
136 pmu = riscv_pmu_alloc();
137 if (!pmu)
138 return -ENOMEM;
139 pmu->pmu.parent = &pdev->dev;
140 pmu_legacy_init(pmu);
141
142 return 0;
143 }
144
145 static struct platform_driver pmu_legacy_driver = {
146 .probe = pmu_legacy_device_probe,
147 .driver = {
148 .name = RISCV_PMU_LEGACY_PDEV_NAME,
149 },
150 };
151
riscv_pmu_legacy_devinit(void)152 static int __init riscv_pmu_legacy_devinit(void)
153 {
154 int ret;
155 struct platform_device *pdev;
156
157 if (likely(pmu_init_done))
158 return 0;
159
160 ret = platform_driver_register(&pmu_legacy_driver);
161 if (ret)
162 return ret;
163
164 pdev = platform_device_register_simple(RISCV_PMU_LEGACY_PDEV_NAME, -1, NULL, 0);
165 if (IS_ERR(pdev)) {
166 platform_driver_unregister(&pmu_legacy_driver);
167 return PTR_ERR(pdev);
168 }
169
170 return ret;
171 }
172 late_initcall(riscv_pmu_legacy_devinit);
173
riscv_pmu_legacy_skip_init(void)174 void riscv_pmu_legacy_skip_init(void)
175 {
176 pmu_init_done = true;
177 }
178