1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "hw.h"
18 #include "../pwrseqcmd.h"
19 #include "pwrseq.h"
20 #include "../btcoexist/rtl_btc.h"
21
22 #define LLT_CONFIG 5
23
_rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw * hw)24 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
25 {
26 struct rtl_priv *rtlpriv = rtl_priv(hw);
27 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
28 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
29 struct sk_buff_head free_list;
30 unsigned long flags;
31
32 skb_queue_head_init(&free_list);
33 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
34 while (skb_queue_len(&ring->queue)) {
35 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
36 struct sk_buff *skb = __skb_dequeue(&ring->queue);
37
38 dma_unmap_single(&rtlpci->pdev->dev,
39 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
40 true, HW_DESC_TXBUFF_ADDR),
41 skb->len, DMA_TO_DEVICE);
42 __skb_queue_tail(&free_list, skb);
43 ring->idx = (ring->idx + 1) % ring->entries;
44 }
45 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
46
47 __skb_queue_purge(&free_list);
48 }
49
_rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)50 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
51 u8 set_bits, u8 clear_bits)
52 {
53 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
54 struct rtl_priv *rtlpriv = rtl_priv(hw);
55
56 rtlpci->reg_bcn_ctrl_val |= set_bits;
57 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
58
59 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
60 }
61
_rtl8821ae_stop_tx_beacon(struct ieee80211_hw * hw)62 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
63 {
64 struct rtl_priv *rtlpriv = rtl_priv(hw);
65 u8 tmp1byte;
66
67 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
68 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
70 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
71 tmp1byte &= ~(BIT(0));
72 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
73 }
74
_rtl8821ae_resume_tx_beacon(struct ieee80211_hw * hw)75 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
76 {
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 u8 tmp1byte;
79
80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
83 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
84 tmp1byte |= BIT(0);
85 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
86 }
87
_rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw * hw)88 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
89 {
90 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
91 }
92
_rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw * hw)93 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
94 {
95 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
96 }
97
_rtl8821ae_set_fw_clock_on(struct ieee80211_hw * hw,u8 rpwm_val,bool b_need_turn_off_ckk)98 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
99 u8 rpwm_val, bool b_need_turn_off_ckk)
100 {
101 struct rtl_priv *rtlpriv = rtl_priv(hw);
102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
103 bool b_support_remote_wake_up;
104 u32 count = 0, isr_regaddr, content;
105 bool b_schedule_timer = b_need_turn_off_ckk;
106
107 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
108 (u8 *)(&b_support_remote_wake_up));
109
110 if (!rtlhal->fw_ready)
111 return;
112 if (!rtlpriv->psc.fw_current_inpsmode)
113 return;
114
115 while (1) {
116 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
117 if (rtlhal->fw_clk_change_in_progress) {
118 while (rtlhal->fw_clk_change_in_progress) {
119 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
120 count++;
121 udelay(100);
122 if (count > 1000)
123 goto change_done;
124 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
125 }
126 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
127 } else {
128 rtlhal->fw_clk_change_in_progress = false;
129 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
130 goto change_done;
131 }
132 }
133 change_done:
134 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
135 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
136 (u8 *)(&rpwm_val));
137 if (FW_PS_IS_ACK(rpwm_val)) {
138 isr_regaddr = REG_HISR;
139 content = rtl_read_dword(rtlpriv, isr_regaddr);
140 while (!(content & IMR_CPWM) && (count < 500)) {
141 udelay(50);
142 count++;
143 content = rtl_read_dword(rtlpriv, isr_regaddr);
144 }
145
146 if (content & IMR_CPWM) {
147 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
148 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
149 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
150 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
151 rtlhal->fw_ps_state);
152 }
153 }
154
155 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
156 rtlhal->fw_clk_change_in_progress = false;
157 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
158 if (b_schedule_timer)
159 mod_timer(&rtlpriv->works.fw_clockoff_timer,
160 jiffies + MSECS(10));
161 } else {
162 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
163 rtlhal->fw_clk_change_in_progress = false;
164 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
165 }
166 }
167
_rtl8821ae_set_fw_clock_off(struct ieee80211_hw * hw,u8 rpwm_val)168 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
169 u8 rpwm_val)
170 {
171 struct rtl_priv *rtlpriv = rtl_priv(hw);
172 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
173 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
174 struct rtl8192_tx_ring *ring;
175 enum rf_pwrstate rtstate;
176 bool b_schedule_timer = false;
177 u8 queue;
178
179 if (!rtlhal->fw_ready)
180 return;
181 if (!rtlpriv->psc.fw_current_inpsmode)
182 return;
183 if (!rtlhal->allow_sw_to_change_hwclc)
184 return;
185 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
186 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
187 return;
188
189 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
190 ring = &rtlpci->tx_ring[queue];
191 if (skb_queue_len(&ring->queue)) {
192 b_schedule_timer = true;
193 break;
194 }
195 }
196
197 if (b_schedule_timer) {
198 mod_timer(&rtlpriv->works.fw_clockoff_timer,
199 jiffies + MSECS(10));
200 return;
201 }
202
203 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
204 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
205 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
206 if (!rtlhal->fw_clk_change_in_progress) {
207 rtlhal->fw_clk_change_in_progress = true;
208 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
209 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
210 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
211 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
212 (u8 *)(&rpwm_val));
213 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
214 rtlhal->fw_clk_change_in_progress = false;
215 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
216 } else {
217 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
218 mod_timer(&rtlpriv->works.fw_clockoff_timer,
219 jiffies + MSECS(10));
220 }
221 }
222 }
223
_rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw * hw)224 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
225 {
226 u8 rpwm_val = 0;
227
228 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
229 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
230 }
231
_rtl8821ae_fwlps_leave(struct ieee80211_hw * hw)232 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
233 {
234 struct rtl_priv *rtlpriv = rtl_priv(hw);
235 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
236 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
237 bool fw_current_inps = false;
238 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
239
240 if (ppsc->low_power_enable) {
241 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
242 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
243 rtlhal->allow_sw_to_change_hwclc = false;
244 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
245 (u8 *)(&fw_pwrmode));
246 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
247 (u8 *)(&fw_current_inps));
248 } else {
249 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
251 (u8 *)(&rpwm_val));
252 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
253 (u8 *)(&fw_pwrmode));
254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
255 (u8 *)(&fw_current_inps));
256 }
257 }
258
_rtl8821ae_fwlps_enter(struct ieee80211_hw * hw)259 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
260 {
261 struct rtl_priv *rtlpriv = rtl_priv(hw);
262 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
263 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
264 bool fw_current_inps = true;
265 u8 rpwm_val;
266
267 if (ppsc->low_power_enable) {
268 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
269 rtlpriv->cfg->ops->set_hw_reg(hw,
270 HW_VAR_FW_PSMODE_STATUS,
271 (u8 *)(&fw_current_inps));
272 rtlpriv->cfg->ops->set_hw_reg(hw,
273 HW_VAR_H2C_FW_PWRMODE,
274 (u8 *)(&ppsc->fwctrl_psmode));
275 rtlhal->allow_sw_to_change_hwclc = true;
276 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
277 } else {
278 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
279 rtlpriv->cfg->ops->set_hw_reg(hw,
280 HW_VAR_FW_PSMODE_STATUS,
281 (u8 *)(&fw_current_inps));
282 rtlpriv->cfg->ops->set_hw_reg(hw,
283 HW_VAR_H2C_FW_PWRMODE,
284 (u8 *)(&ppsc->fwctrl_psmode));
285 rtlpriv->cfg->ops->set_hw_reg(hw,
286 HW_VAR_SET_RPWM,
287 (u8 *)(&rpwm_val));
288 }
289 }
290
_rtl8821ae_download_rsvd_page(struct ieee80211_hw * hw,bool dl_whole_packets)291 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
292 bool dl_whole_packets)
293 {
294 struct rtl_priv *rtlpriv = rtl_priv(hw);
295 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
296 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
297 u8 count = 0, dlbcn_count = 0;
298 bool send_beacon = false;
299
300 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
301 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
302
303 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
304 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
305
306 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
307 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
308 tmp_reg422 & (~BIT(6)));
309 if (tmp_reg422 & BIT(6))
310 send_beacon = true;
311
312 do {
313 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
314 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
315 (bcnvalid_reg | BIT(0)));
316 _rtl8821ae_return_beacon_queue_skb(hw);
317
318 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
319 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
320 dl_whole_packets);
321 else
322 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
323 dl_whole_packets);
324
325 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
326 count = 0;
327 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
328 count++;
329 udelay(10);
330 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
331 }
332 dlbcn_count++;
333 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
334
335 if (!(bcnvalid_reg & BIT(0)))
336 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
337 "Download RSVD page failed!\n");
338 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
339 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
340 _rtl8821ae_return_beacon_queue_skb(hw);
341 if (send_beacon) {
342 dlbcn_count = 0;
343 do {
344 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
345 bcnvalid_reg | BIT(0));
346
347 _rtl8821ae_return_beacon_queue_skb(hw);
348
349 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
350 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
351 false);
352 else
353 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
354 false);
355
356 /* check rsvd page download OK. */
357 bcnvalid_reg = rtl_read_byte(rtlpriv,
358 REG_TDECTRL + 2);
359 count = 0;
360 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
361 count++;
362 udelay(10);
363 bcnvalid_reg =
364 rtl_read_byte(rtlpriv,
365 REG_TDECTRL + 2);
366 }
367 dlbcn_count++;
368 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
369
370 if (!(bcnvalid_reg & BIT(0)))
371 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
372 "2 Download RSVD page failed!\n");
373 }
374 }
375
376 if (bcnvalid_reg & BIT(0))
377 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
378
379 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
380 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
381
382 if (send_beacon)
383 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
384
385 if (!rtlhal->enter_pnp_sleep) {
386 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
387 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
388 }
389 }
390
rtl8821ae_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)391 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
392 {
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
395 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
397
398 switch (variable) {
399 case HW_VAR_ETHER_ADDR:
400 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
401 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
402 break;
403 case HW_VAR_BSSID:
404 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
405 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
406 break;
407 case HW_VAR_MEDIA_STATUS:
408 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
409 break;
410 case HW_VAR_SLOT_TIME:
411 *((u8 *)(val)) = mac->slot_time;
412 break;
413 case HW_VAR_BEACON_INTERVAL:
414 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
415 break;
416 case HW_VAR_ATIM_WINDOW:
417 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
418 break;
419 case HW_VAR_RCR:
420 *((u32 *)(val)) = rtlpci->receive_config;
421 break;
422 case HW_VAR_RF_STATE:
423 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
424 break;
425 case HW_VAR_FWLPS_RF_ON:{
426 enum rf_pwrstate rfstate;
427 u32 val_rcr;
428
429 rtlpriv->cfg->ops->get_hw_reg(hw,
430 HW_VAR_RF_STATE,
431 (u8 *)(&rfstate));
432 if (rfstate == ERFOFF) {
433 *((bool *)(val)) = true;
434 } else {
435 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
436 val_rcr &= 0x00070000;
437 if (val_rcr)
438 *((bool *)(val)) = false;
439 else
440 *((bool *)(val)) = true;
441 }
442 break; }
443 case HW_VAR_FW_PSMODE_STATUS:
444 *((bool *)(val)) = ppsc->fw_current_inpsmode;
445 break;
446 case HW_VAR_CORRECT_TSF:{
447 u64 tsf;
448 u32 *ptsf_low = (u32 *)&tsf;
449 u32 *ptsf_high = ((u32 *)&tsf) + 1;
450
451 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
452 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
453
454 *((u64 *)(val)) = tsf;
455
456 break; }
457 case HAL_DEF_WOWLAN:
458 if (ppsc->wo_wlan_mode)
459 *((bool *)(val)) = true;
460 else
461 *((bool *)(val)) = false;
462 break;
463 default:
464 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
465 "switch case %#x not processed\n", variable);
466 break;
467 }
468 }
469
rtl8821ae_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)470 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
471 {
472 struct rtl_priv *rtlpriv = rtl_priv(hw);
473 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
474 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
475 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
476 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
477 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
478 u8 idx;
479
480 switch (variable) {
481 case HW_VAR_ETHER_ADDR:{
482 for (idx = 0; idx < ETH_ALEN; idx++) {
483 rtl_write_byte(rtlpriv, (REG_MACID + idx),
484 val[idx]);
485 }
486 break;
487 }
488 case HW_VAR_BASIC_RATE:{
489 u16 b_rate_cfg = ((u16 *)val)[0];
490 b_rate_cfg = b_rate_cfg & 0x15f;
491 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
492 break;
493 }
494 case HW_VAR_BSSID:{
495 for (idx = 0; idx < ETH_ALEN; idx++) {
496 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
497 val[idx]);
498 }
499 break;
500 }
501 case HW_VAR_SIFS:
502 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
503 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
504
505 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
506 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
507
508 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
509 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
510 break;
511 case HW_VAR_R2T_SIFS:
512 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
513 break;
514 case HW_VAR_SLOT_TIME:{
515 u8 e_aci;
516
517 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
518 "HW_VAR_SLOT_TIME %x\n", val[0]);
519
520 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
521
522 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
523 rtlpriv->cfg->ops->set_hw_reg(hw,
524 HW_VAR_AC_PARAM,
525 (u8 *)(&e_aci));
526 }
527 break; }
528 case HW_VAR_ACK_PREAMBLE:{
529 u8 reg_tmp;
530 u8 short_preamble = (bool)(*(u8 *)val);
531
532 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
533 if (short_preamble) {
534 reg_tmp |= BIT(1);
535 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
536 reg_tmp);
537 } else {
538 reg_tmp &= (~BIT(1));
539 rtl_write_byte(rtlpriv,
540 REG_TRXPTCL_CTL + 2,
541 reg_tmp);
542 }
543 break; }
544 case HW_VAR_WPA_CONFIG:
545 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
546 break;
547 case HW_VAR_AMPDU_MIN_SPACE:{
548 u8 min_spacing_to_set;
549
550 min_spacing_to_set = *((u8 *)val);
551 if (min_spacing_to_set <= 7) {
552
553 mac->min_space_cfg = ((mac->min_space_cfg &
554 0xf8) |
555 min_spacing_to_set);
556
557 *val = min_spacing_to_set;
558
559 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
560 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
561 mac->min_space_cfg);
562
563 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
564 mac->min_space_cfg);
565 }
566 break; }
567 case HW_VAR_SHORTGI_DENSITY:{
568 u8 density_to_set;
569
570 density_to_set = *((u8 *)val);
571 mac->min_space_cfg |= (density_to_set << 3);
572
573 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
574 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
575 mac->min_space_cfg);
576
577 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
578 mac->min_space_cfg);
579
580 break; }
581 case HW_VAR_AMPDU_FACTOR:{
582 u32 ampdu_len = (*((u8 *)val));
583
584 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
585 if (ampdu_len < VHT_AGG_SIZE_128K)
586 ampdu_len =
587 (0x2000 << (*((u8 *)val))) - 1;
588 else
589 ampdu_len = 0x1ffff;
590 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
591 if (ampdu_len < HT_AGG_SIZE_64K)
592 ampdu_len =
593 (0x2000 << (*((u8 *)val))) - 1;
594 else
595 ampdu_len = 0xffff;
596 }
597 ampdu_len |= BIT(31);
598
599 rtl_write_dword(rtlpriv,
600 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
601 break; }
602 case HW_VAR_AC_PARAM:{
603 u8 e_aci = *((u8 *)val);
604
605 rtl8821ae_dm_init_edca_turbo(hw);
606 if (rtlpci->acm_method != EACMWAY2_SW)
607 rtlpriv->cfg->ops->set_hw_reg(hw,
608 HW_VAR_ACM_CTRL,
609 (u8 *)(&e_aci));
610 break; }
611 case HW_VAR_ACM_CTRL:{
612 u8 e_aci = *((u8 *)val);
613 union aci_aifsn *p_aci_aifsn =
614 (union aci_aifsn *)(&mac->ac[0].aifs);
615 u8 acm = p_aci_aifsn->f.acm;
616 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
617
618 acm_ctrl =
619 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
620
621 if (acm) {
622 switch (e_aci) {
623 case AC0_BE:
624 acm_ctrl |= ACMHW_BEQEN;
625 break;
626 case AC2_VI:
627 acm_ctrl |= ACMHW_VIQEN;
628 break;
629 case AC3_VO:
630 acm_ctrl |= ACMHW_VOQEN;
631 break;
632 default:
633 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
634 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
635 acm);
636 break;
637 }
638 } else {
639 switch (e_aci) {
640 case AC0_BE:
641 acm_ctrl &= (~ACMHW_BEQEN);
642 break;
643 case AC2_VI:
644 acm_ctrl &= (~ACMHW_VIQEN);
645 break;
646 case AC3_VO:
647 acm_ctrl &= (~ACMHW_VOQEN);
648 break;
649 default:
650 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
651 "switch case %#x not processed\n",
652 e_aci);
653 break;
654 }
655 }
656
657 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
658 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
659 acm_ctrl);
660 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
661 break; }
662 case HW_VAR_RCR:
663 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
664 rtlpci->receive_config = ((u32 *)(val))[0];
665 break;
666 case HW_VAR_RETRY_LIMIT:{
667 u8 retry_limit = ((u8 *)(val))[0];
668
669 rtl_write_word(rtlpriv, REG_RL,
670 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
671 retry_limit << RETRY_LIMIT_LONG_SHIFT);
672 break; }
673 case HW_VAR_DUAL_TSF_RST:
674 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
675 break;
676 case HW_VAR_EFUSE_BYTES:
677 rtlefuse->efuse_usedbytes = *((u16 *)val);
678 break;
679 case HW_VAR_EFUSE_USAGE:
680 rtlefuse->efuse_usedpercentage = *((u8 *)val);
681 break;
682 case HW_VAR_IO_CMD:
683 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
684 break;
685 case HW_VAR_SET_RPWM:{
686 u8 rpwm_val;
687
688 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
689 udelay(1);
690
691 if (rpwm_val & BIT(7)) {
692 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
693 (*(u8 *)val));
694 } else {
695 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
696 ((*(u8 *)val) | BIT(7)));
697 }
698
699 break; }
700 case HW_VAR_H2C_FW_PWRMODE:
701 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
702 break;
703 case HW_VAR_FW_PSMODE_STATUS:
704 ppsc->fw_current_inpsmode = *((bool *)val);
705 break;
706 case HW_VAR_INIT_RTS_RATE:
707 break;
708 case HW_VAR_RESUME_CLK_ON:
709 _rtl8821ae_set_fw_ps_rf_on(hw);
710 break;
711 case HW_VAR_FW_LPS_ACTION:{
712 bool b_enter_fwlps = *((bool *)val);
713
714 if (b_enter_fwlps)
715 _rtl8821ae_fwlps_enter(hw);
716 else
717 _rtl8821ae_fwlps_leave(hw);
718 break; }
719 case HW_VAR_H2C_FW_JOINBSSRPT:{
720 u8 mstatus = (*(u8 *)val);
721
722 if (mstatus == RT_MEDIA_CONNECT) {
723 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
724 NULL);
725 _rtl8821ae_download_rsvd_page(hw, false);
726 }
727 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
728
729 break; }
730 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
731 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
732 break;
733 case HW_VAR_AID:{
734 u16 u2btmp;
735 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
736 u2btmp &= 0xC000;
737 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
738 mac->assoc_id));
739 break; }
740 case HW_VAR_CORRECT_TSF:{
741 u8 btype_ibss = ((u8 *)(val))[0];
742
743 if (btype_ibss)
744 _rtl8821ae_stop_tx_beacon(hw);
745
746 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
747
748 rtl_write_dword(rtlpriv, REG_TSFTR,
749 (u32)(mac->tsf & 0xffffffff));
750 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
751 (u32)((mac->tsf >> 32) & 0xffffffff));
752
753 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
754
755 if (btype_ibss)
756 _rtl8821ae_resume_tx_beacon(hw);
757 break; }
758 case HW_VAR_NAV_UPPER: {
759 u32 us_nav_upper = *(u32 *)val;
760
761 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
762 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
763 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
764 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
765 break;
766 }
767 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
768 ((u8)((us_nav_upper +
769 HAL_92C_NAV_UPPER_UNIT - 1) /
770 HAL_92C_NAV_UPPER_UNIT)));
771 break; }
772 case HW_VAR_KEEP_ALIVE: {
773 u8 array[2];
774 array[0] = 0xff;
775 array[1] = *((u8 *)val);
776 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
777 array);
778 break; }
779 default:
780 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
781 "switch case %#x not processed\n", variable);
782 break;
783 }
784 }
785
_rtl8821ae_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)786 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
787 {
788 struct rtl_priv *rtlpriv = rtl_priv(hw);
789 bool status = true;
790 long count = 0;
791 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
792 _LLT_OP(_LLT_WRITE_ACCESS);
793
794 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
795
796 do {
797 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
798 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
799 break;
800
801 if (count > POLLING_LLT_THRESHOLD) {
802 pr_err("Failed to polling write LLT done at address %d!\n",
803 address);
804 status = false;
805 break;
806 }
807 } while (++count);
808
809 return status;
810 }
811
_rtl8821ae_llt_table_init(struct ieee80211_hw * hw)812 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
813 {
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815 unsigned short i;
816 u8 txpktbuf_bndy;
817 u32 rqpn;
818 u8 maxpage;
819 bool status;
820
821 maxpage = 255;
822 txpktbuf_bndy = 0xF7;
823 rqpn = 0x80e60808;
824
825 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
826 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
827
828 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
829
830 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
831 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
832
833 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
834 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
835
836 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
837 status = _rtl8821ae_llt_write(hw, i, i + 1);
838 if (!status)
839 return status;
840 }
841
842 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
843 if (!status)
844 return status;
845
846 for (i = txpktbuf_bndy; i < maxpage; i++) {
847 status = _rtl8821ae_llt_write(hw, i, (i + 1));
848 if (!status)
849 return status;
850 }
851
852 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
853 if (!status)
854 return status;
855
856 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
857
858 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
859
860 return true;
861 }
862
_rtl8821ae_gen_refresh_led_state(struct ieee80211_hw * hw)863 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
864 {
865 struct rtl_priv *rtlpriv = rtl_priv(hw);
866 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
867 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
868 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
869
870 if (rtlpriv->rtlhal.up_first_time)
871 return;
872
873 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
874 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
875 rtl8812ae_sw_led_on(hw, pin0);
876 else
877 rtl8821ae_sw_led_on(hw, pin0);
878 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
879 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
880 rtl8812ae_sw_led_on(hw, pin0);
881 else
882 rtl8821ae_sw_led_on(hw, pin0);
883 else
884 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
885 rtl8812ae_sw_led_off(hw, pin0);
886 else
887 rtl8821ae_sw_led_off(hw, pin0);
888 }
889
_rtl8821ae_init_mac(struct ieee80211_hw * hw)890 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
891 {
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
894 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
895
896 u8 bytetmp = 0;
897 u16 wordtmp = 0;
898 bool mac_func_enable = rtlhal->mac_func_enable;
899
900 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
901
902 /*Auto Power Down to CHIP-off State*/
903 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
904 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
905
906 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
907 /* HW Power on sequence*/
908 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
909 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
910 RTL8812_NIC_ENABLE_FLOW)) {
911 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
912 "init 8812 MAC Fail as power on failure\n");
913 return false;
914 }
915 } else {
916 /* HW Power on sequence */
917 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
918 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
919 RTL8821A_NIC_ENABLE_FLOW)){
920 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
921 "init 8821 MAC Fail as power on failure\n");
922 return false;
923 }
924 }
925
926 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
927 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
928
929 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
930 bytetmp = 0xff;
931 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
932 mdelay(2);
933
934 bytetmp = 0xff;
935 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
936 mdelay(2);
937
938 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
939 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
940 if (bytetmp & BIT(0)) {
941 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
942 bytetmp |= BIT(6);
943 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
944 }
945 }
946
947 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
948 bytetmp &= ~BIT(4);
949 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
950
951 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
952
953 if (!mac_func_enable) {
954 if (!_rtl8821ae_llt_table_init(hw))
955 return false;
956 }
957
958 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
959 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
960
961 /* Enable FW Beamformer Interrupt */
962 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
963 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
964
965 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
966 wordtmp &= 0xf;
967 wordtmp |= 0xF5B1;
968 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
969
970 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
971 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
972 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
973 /*low address*/
974 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
975 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
976 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
977 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
978 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
979 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
980 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
981 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
982 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
983 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
984 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
985 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
986 rtl_write_dword(rtlpriv, REG_HQ_DESA,
987 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
988 rtl_write_dword(rtlpriv, REG_RX_DESA,
989 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
990
991 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
992
993 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
994
995 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
996
997 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
998 _rtl8821ae_gen_refresh_led_state(hw);
999
1000 return true;
1001 }
1002
_rtl8821ae_hw_configure(struct ieee80211_hw * hw)1003 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1004 {
1005 struct rtl_priv *rtlpriv = rtl_priv(hw);
1006 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1007 u32 reg_rrsr;
1008
1009 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1010
1011 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1012 /* ARFB table 9 for 11ac 5G 2SS */
1013 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1014 /* ARFB table 10 for 11ac 5G 1SS */
1015 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1016 /* ARFB table 11 for 11ac 24G 1SS */
1017 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1018 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1019 /* ARFB table 12 for 11ac 24G 1SS */
1020 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1021 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1022 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1023 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1024 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1025
1026 /*Set retry limit*/
1027 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1028
1029 /* Set Data / Response auto rate fallback retry count*/
1030 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1031 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1032 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1033 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1034
1035 rtlpci->reg_bcn_ctrl_val = 0x1d;
1036 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1037
1038 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1039 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1040
1041 /* AGGR_BK_TIME Reg51A 0x16 */
1042 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1043
1044 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1045 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1046
1047 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1048 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1049 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1050 }
1051
_rtl8821ae_mdio_read(struct rtl_priv * rtlpriv,u8 addr)1052 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1053 {
1054 u16 ret = 0;
1055 u8 tmp = 0, count = 0;
1056
1057 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1058 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1059 count = 0;
1060 while (tmp && count < 20) {
1061 udelay(10);
1062 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1063 count++;
1064 }
1065 if (0 == tmp)
1066 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1067
1068 return ret;
1069 }
1070
_rtl8821ae_mdio_write(struct rtl_priv * rtlpriv,u8 addr,u16 data)1071 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1072 {
1073 u8 tmp = 0, count = 0;
1074
1075 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1076 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1077 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1078 count = 0;
1079 while (tmp && count < 20) {
1080 udelay(10);
1081 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1082 count++;
1083 }
1084 }
1085
_rtl8821ae_dbi_read(struct rtl_priv * rtlpriv,u16 addr)1086 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1087 {
1088 u16 read_addr = addr & 0xfffc;
1089 u8 tmp = 0, count = 0, ret = 0;
1090
1091 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1092 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1093 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1094 count = 0;
1095 while (tmp && count < 20) {
1096 udelay(10);
1097 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1098 count++;
1099 }
1100 if (0 == tmp) {
1101 read_addr = REG_DBI_RDATA + addr % 4;
1102 ret = rtl_read_byte(rtlpriv, read_addr);
1103 }
1104 return ret;
1105 }
1106
_rtl8821ae_dbi_write(struct rtl_priv * rtlpriv,u16 addr,u8 data)1107 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1108 {
1109 u8 tmp = 0, count = 0;
1110 u16 write_addr, remainder = addr % 4;
1111
1112 write_addr = REG_DBI_WDATA + remainder;
1113 rtl_write_byte(rtlpriv, write_addr, data);
1114
1115 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1116 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1117
1118 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1119
1120 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1121 count = 0;
1122 while (tmp && count < 20) {
1123 udelay(10);
1124 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1125 count++;
1126 }
1127 }
1128
_rtl8821ae_enable_aspm_back_door(struct ieee80211_hw * hw)1129 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1130 {
1131 struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1133 u8 tmp;
1134
1135 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1136 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1137 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1138
1139 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1140 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1141 }
1142
1143 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1144 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1145 ASPM_L1_LATENCY << 3);
1146
1147 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1148 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1149
1150 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1151 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1152 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1153 }
1154 }
1155
rtl8821ae_enable_hw_security_config(struct ieee80211_hw * hw)1156 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1157 {
1158 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159 u8 sec_reg_value;
1160 u8 tmp;
1161
1162 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1163 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1164 rtlpriv->sec.pairwise_enc_algorithm,
1165 rtlpriv->sec.group_enc_algorithm);
1166
1167 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1168 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1169 "not open hw encryption\n");
1170 return;
1171 }
1172
1173 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1174
1175 if (rtlpriv->sec.use_defaultkey) {
1176 sec_reg_value |= SCR_TXUSEDK;
1177 sec_reg_value |= SCR_RXUSEDK;
1178 }
1179
1180 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1181
1182 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1183 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1184
1185 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1186 "The SECR-value %x\n", sec_reg_value);
1187
1188 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1189 }
1190
1191 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1192 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1193 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1194 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1195 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1196 /* ----------------------------------------------------------- */
1197
rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw * hw)1198 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1199 {
1200 struct rtl_priv *rtlpriv = rtl_priv(hw);
1201 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1202 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1203 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1204
1205 rtlpriv->cfg->ops->set_hw_reg(hw,
1206 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1207
1208 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1209 "Initialize MacId media status: from %d to %d\n",
1210 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1211 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1212 }
1213
_rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw * hw)1214 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1215 {
1216 struct rtl_priv *rtlpriv = rtl_priv(hw);
1217 u8 tmp;
1218
1219 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1220 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1221 if (!(tmp & BIT(2))) {
1222 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1223 mdelay(100);
1224 }
1225
1226 /* read reg 0x350 Bit[25] if 1 : RX hang */
1227 /* read reg 0x350 Bit[24] if 1 : TX hang */
1228 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1229 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1230 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1231 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1232 return true;
1233 } else {
1234 return false;
1235 }
1236 }
1237
_rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw * hw,bool mac_power_on,bool in_watchdog)1238 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1239 bool mac_power_on,
1240 bool in_watchdog)
1241 {
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1244 u8 tmp;
1245 bool release_mac_rx_pause;
1246 u8 backup_pcie_dma_pause;
1247
1248 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1249
1250 /* 1. Disable register write lock. 0x1c[1] = 0 */
1251 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1252 tmp &= ~(BIT(1));
1253 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1254 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1255 /* write 0xCC bit[2] = 1'b1 */
1256 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1257 tmp |= BIT(2);
1258 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1259 }
1260
1261 /* 2. Check and pause TRX DMA */
1262 /* write 0x284 bit[18] = 1'b1 */
1263 /* write 0x301 = 0xFF */
1264 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1265 if (tmp & BIT(2)) {
1266 /* Already pause before the function for another purpose. */
1267 release_mac_rx_pause = false;
1268 } else {
1269 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1270 release_mac_rx_pause = true;
1271 }
1272 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1273 if (backup_pcie_dma_pause != 0xFF)
1274 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1275
1276 if (mac_power_on) {
1277 /* 3. reset TRX function */
1278 /* write 0x100 = 0x00 */
1279 rtl_write_byte(rtlpriv, REG_CR, 0);
1280 }
1281
1282 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1283 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1284 tmp &= ~(BIT(0));
1285 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1286
1287 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1288 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1289 tmp |= BIT(0);
1290 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1291
1292 if (mac_power_on) {
1293 /* 6. enable TRX function */
1294 /* write 0x100 = 0xFF */
1295 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1296
1297 /* We should init LLT & RQPN and
1298 * prepare Tx/Rx descriptor address later
1299 * because MAC function is reset.*/
1300 }
1301
1302 /* 7. Restore PCIe autoload down bit */
1303 /* 8812AE does not have the definition. */
1304 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1305 /* write 0xF8 bit[17] = 1'b1 */
1306 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1307 tmp |= BIT(1);
1308 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1309 }
1310
1311 /* In MAC power on state, BB and RF may be in ON state,
1312 * if we release TRx DMA here.
1313 * it will cause packets to be started to Tx/Rx,
1314 * so we release Tx/Rx DMA later.*/
1315 if (!mac_power_on/* || in_watchdog*/) {
1316 /* 8. release TRX DMA */
1317 /* write 0x284 bit[18] = 1'b0 */
1318 /* write 0x301 = 0x00 */
1319 if (release_mac_rx_pause) {
1320 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1321 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1322 tmp & (~BIT(2)));
1323 }
1324 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1325 backup_pcie_dma_pause);
1326 }
1327
1328 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1329 /* 9. lock system register */
1330 /* write 0xCC bit[2] = 1'b0 */
1331 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1332 tmp &= ~(BIT(2));
1333 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1334 }
1335 return true;
1336 }
1337
_rtl8821ae_get_wakeup_reason(struct ieee80211_hw * hw)1338 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1339 {
1340 struct rtl_priv *rtlpriv = rtl_priv(hw);
1341 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1342 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1343 u8 fw_reason = 0;
1344
1345 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1346
1347 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1348 fw_reason);
1349
1350 ppsc->wakeup_reason = 0;
1351
1352 rtlhal->last_suspend_sec = ktime_get_real_seconds();
1353
1354 switch (fw_reason) {
1355 case FW_WOW_V2_PTK_UPDATE_EVENT:
1356 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1357 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1358 "It's a WOL PTK Key update event!\n");
1359 break;
1360 case FW_WOW_V2_GTK_UPDATE_EVENT:
1361 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1362 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1363 "It's a WOL GTK Key update event!\n");
1364 break;
1365 case FW_WOW_V2_DISASSOC_EVENT:
1366 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1367 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1368 "It's a disassociation event!\n");
1369 break;
1370 case FW_WOW_V2_DEAUTH_EVENT:
1371 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1372 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1373 "It's a deauth event!\n");
1374 break;
1375 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1376 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1377 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1378 "It's a Fw disconnect decision (AP lost) event!\n");
1379 break;
1380 case FW_WOW_V2_MAGIC_PKT_EVENT:
1381 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1382 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1383 "It's a magic packet event!\n");
1384 break;
1385 case FW_WOW_V2_UNICAST_PKT_EVENT:
1386 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1387 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1388 "It's an unicast packet event!\n");
1389 break;
1390 case FW_WOW_V2_PATTERN_PKT_EVENT:
1391 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1392 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1393 "It's a pattern match event!\n");
1394 break;
1395 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1396 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1397 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1398 "It's an RTD3 Ssid match event!\n");
1399 break;
1400 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1401 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1402 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1403 "It's an RealWoW wake packet event!\n");
1404 break;
1405 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1406 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1407 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1408 "It's an RealWoW ack lost event!\n");
1409 break;
1410 default:
1411 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1412 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1413 fw_reason);
1414 break;
1415 }
1416 }
1417
_rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw * hw)1418 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1419 {
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1421 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1422
1423 /*low address*/
1424 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1425 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1426 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1427 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1428 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1429 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1430 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1431 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1432 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1433 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1434 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1435 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1436 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1437 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1438 rtl_write_dword(rtlpriv, REG_RX_DESA,
1439 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1440 }
1441
_rtl8821ae_init_llt_table(struct ieee80211_hw * hw,u32 boundary)1442 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1443 {
1444 bool status = true;
1445 u32 i;
1446 u32 txpktbuf_bndy = boundary;
1447 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1448
1449 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1450 status = _rtl8821ae_llt_write(hw, i , i + 1);
1451 if (!status)
1452 return status;
1453 }
1454
1455 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1456 if (!status)
1457 return status;
1458
1459 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1460 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1461 if (!status)
1462 return status;
1463 }
1464
1465 return _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, txpktbuf_bndy);
1466 }
1467
_rtl8821ae_dynamic_rqpn(struct ieee80211_hw * hw,u32 boundary,u16 npq_rqpn_value,u32 rqpn_val)1468 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1469 u16 npq_rqpn_value, u32 rqpn_val)
1470 {
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472 u8 tmp;
1473 bool ret = true;
1474 u16 count = 0, tmp16;
1475 bool support_remote_wakeup;
1476
1477 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1478 (u8 *)(&support_remote_wakeup));
1479
1480 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1481 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1482 boundary, npq_rqpn_value, rqpn_val);
1483
1484 /* stop PCIe DMA
1485 * 1. 0x301[7:0] = 0xFE */
1486 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1487
1488 /* wait TXFF empty
1489 * 2. polling till 0x41A[15:0]=0x07FF */
1490 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1491 while ((tmp16 & 0x07FF) != 0x07FF) {
1492 udelay(100);
1493 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1494 count++;
1495 if ((count % 200) == 0) {
1496 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1497 "Tx queue is not empty for 20ms!\n");
1498 }
1499 if (count >= 1000) {
1500 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1501 "Wait for Tx FIFO empty timeout!\n");
1502 break;
1503 }
1504 }
1505
1506 /* TX pause
1507 * 3. reg 0x522=0xFF */
1508 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1509
1510 /* Wait TX State Machine OK
1511 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1512 count = 0;
1513 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1514 udelay(100);
1515 count++;
1516 if (count >= 500) {
1517 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1518 "Wait for TX State Machine ready timeout !!\n");
1519 break;
1520 }
1521 }
1522
1523 /* stop RX DMA path
1524 * 5. 0x284[18] = 1
1525 * 6. wait till 0x284[17] == 1
1526 * wait RX DMA idle */
1527 count = 0;
1528 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1529 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1530 do {
1531 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1532 udelay(10);
1533 count++;
1534 } while (!(tmp & BIT(1)) && count < 100);
1535
1536 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1537 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1538 count, tmp);
1539
1540 /* reset BB
1541 * 7. 0x02 [0] = 0 */
1542 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1543 tmp &= ~(BIT(0));
1544 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1545
1546 /* Reset TRX MAC
1547 * 8. 0x100 = 0x00
1548 * Delay (1ms) */
1549 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1550 udelay(1000);
1551
1552 /* Disable MAC Security Engine
1553 * 9. 0x100 bit[9]=0 */
1554 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1555 tmp &= ~(BIT(1));
1556 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1557
1558 /* To avoid DD-Tim Circuit hang
1559 * 10. 0x553 bit[5]=1 */
1560 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1561 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1562
1563 /* Enable MAC Security Engine
1564 * 11. 0x100 bit[9]=1 */
1565 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1566 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1567
1568 /* Enable TRX MAC
1569 * 12. 0x100 = 0xFF
1570 * Delay (1ms) */
1571 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1572 udelay(1000);
1573
1574 /* Enable BB
1575 * 13. 0x02 [0] = 1 */
1576 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1577 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1578
1579 /* beacon setting
1580 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1581 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1582 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1583 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1584
1585 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1586 * WMAC_LBK_BF_HD */
1587 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1588 (u8)boundary);
1589
1590 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1591
1592 /* init LLT
1593 * 17. init LLT */
1594 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1595 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
1596 "Failed to init LLT table!\n");
1597 return false;
1598 }
1599
1600 /* reallocate RQPN
1601 * 18. reallocate RQPN and init LLT */
1602 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1603 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1604
1605 /* release Tx pause
1606 * 19. 0x522=0x00 */
1607 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1608
1609 /* enable PCIE DMA
1610 * 20. 0x301[7:0] = 0x00
1611 * 21. 0x284[18] = 0 */
1612 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1613 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1614 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1615
1616 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1617 return ret;
1618 }
1619
_rtl8821ae_simple_initialize_adapter(struct ieee80211_hw * hw)1620 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1621 {
1622 struct rtl_priv *rtlpriv = rtl_priv(hw);
1623 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1624 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1625
1626 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1627 /* Re-download normal Fw. */
1628 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1629 #endif
1630
1631 /* Re-Initialize LLT table. */
1632 if (rtlhal->re_init_llt_table) {
1633 u32 rqpn = 0x80e70808;
1634 u8 rqpn_npq = 0, boundary = 0xF8;
1635 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1636 rqpn = 0x80e90808;
1637 boundary = 0xFA;
1638 }
1639 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1640 rtlhal->re_init_llt_table = false;
1641 }
1642
1643 ppsc->rfpwr_state = ERFON;
1644 }
1645
_rtl8821ae_enable_l1off(struct ieee80211_hw * hw)1646 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1647 {
1648 u8 tmp = 0;
1649 struct rtl_priv *rtlpriv = rtl_priv(hw);
1650
1651 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1652
1653 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1654 if (!(tmp & (BIT(2) | BIT(3)))) {
1655 rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1656 "0x160(%#x)return!!\n", tmp);
1657 return;
1658 }
1659
1660 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1661 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1662
1663 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1664 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1665
1666 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1667 }
1668
_rtl8821ae_enable_ltr(struct ieee80211_hw * hw)1669 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1670 {
1671 u8 tmp = 0;
1672 struct rtl_priv *rtlpriv = rtl_priv(hw);
1673
1674 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1675
1676 /* Check 0x98[10] */
1677 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1678 if (!(tmp & BIT(2))) {
1679 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1680 "<---0x99(%#x) return!!\n", tmp);
1681 return;
1682 }
1683
1684 /* LTR idle latency, 0x90 for 144us */
1685 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1686
1687 /* LTR active latency, 0x3c for 60us */
1688 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1689
1690 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1691 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1692
1693 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1694 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1695 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1696
1697 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1698 }
1699
_rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw * hw)1700 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1701 {
1702 struct rtl_priv *rtlpriv = rtl_priv(hw);
1703 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1704 bool init_finished = true;
1705 u8 tmp = 0;
1706
1707 /* Get Fw wake up reason. */
1708 _rtl8821ae_get_wakeup_reason(hw);
1709
1710 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1711 * The root cause has not been found. */
1712 if (_rtl8821ae_check_pcie_dma_hang(hw))
1713 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1714
1715 /* Prepare Tx/Rx Desc Hw address. */
1716 _rtl8821ae_init_trx_desc_hw_address(hw);
1717
1718 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1719 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1720 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1721
1722 /* Check wake up event.
1723 * We should check wake packet bit before disable wowlan by H2C or
1724 * Fw will clear the bit. */
1725 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1726 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1727 "Read REG_FTISR 0x13f = %#X\n", tmp);
1728
1729 /* Set the WoWLAN related function control disable. */
1730 rtl8821ae_set_fw_wowlan_mode(hw, false);
1731 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1732
1733 if (rtlhal->hw_rof_enable) {
1734 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1735 if (tmp & BIT(1)) {
1736 /* Clear GPIO9 ISR */
1737 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1738 init_finished = false;
1739 } else {
1740 init_finished = true;
1741 }
1742 }
1743
1744 if (init_finished) {
1745 _rtl8821ae_simple_initialize_adapter(hw);
1746
1747 /* Release Pcie Interface Tx DMA. */
1748 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1749 /* Release Pcie RX DMA */
1750 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1751
1752 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1753 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1754
1755 _rtl8821ae_enable_l1off(hw);
1756 _rtl8821ae_enable_ltr(hw);
1757 }
1758
1759 return init_finished;
1760 }
1761
_rtl8812ae_bb8812_config_1t(struct ieee80211_hw * hw)1762 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1763 {
1764 /* BB OFDM RX Path_A */
1765 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1766 /* BB OFDM TX Path_A */
1767 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1768 /* BB CCK R/Rx Path_A */
1769 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1770 /* MCS support */
1771 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1772 /* RF Path_B HSSI OFF */
1773 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1774 /* RF Path_B Power Down */
1775 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1776 /* ADDA Path_B OFF */
1777 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1778 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1779 }
1780
_rtl8821ae_poweroff_adapter(struct ieee80211_hw * hw)1781 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1782 {
1783 struct rtl_priv *rtlpriv = rtl_priv(hw);
1784 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1785 u8 u1b_tmp;
1786
1787 rtlhal->mac_func_enable = false;
1788
1789 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1790 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1791 /* 1. Run LPS WL RFOFF flow */
1792 /* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1793 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1794 */
1795 rtl_hal_pwrseqcmdparsing(rtlpriv,
1796 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1797 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1798 }
1799 /* 2. 0x1F[7:0] = 0 */
1800 /* turn off RF */
1801 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1802 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1803 rtlhal->fw_ready) {
1804 rtl8821ae_firmware_selfreset(hw);
1805 }
1806
1807 /* Reset MCU. Suggested by Filen. */
1808 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1809 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1810
1811 /* g. MCUFWDL 0x80[1:0]=0 */
1812 /* reset MCU ready status */
1813 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1814
1815 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1816 /* HW card disable configuration. */
1817 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1818 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1819 } else {
1820 /* HW card disable configuration. */
1821 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1822 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1823 }
1824
1825 /* Reset MCU IO Wrapper */
1826 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1827 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1828 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1829 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1830
1831 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1832 /* lock ISO/CLK/Power control register */
1833 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1834 }
1835
rtl8821ae_hw_init(struct ieee80211_hw * hw)1836 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1837 {
1838 struct rtl_priv *rtlpriv = rtl_priv(hw);
1839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1840 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1841 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1842 bool rtstatus = true;
1843 int err;
1844 u8 tmp_u1b;
1845 bool support_remote_wakeup;
1846 u32 nav_upper = WIFI_NAV_UPPER_US;
1847
1848 rtlhal->being_init_adapter = true;
1849 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1850 (u8 *)(&support_remote_wakeup));
1851 rtlpriv->intf_ops->disable_aspm(hw);
1852
1853 /*YP wowlan not considered*/
1854
1855 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1856 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1857 rtlhal->mac_func_enable = true;
1858 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1859 "MAC has already power on.\n");
1860 } else {
1861 rtlhal->mac_func_enable = false;
1862 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1863 }
1864
1865 if (support_remote_wakeup &&
1866 rtlhal->wake_from_pnp_sleep &&
1867 rtlhal->mac_func_enable) {
1868 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1869 rtlhal->being_init_adapter = false;
1870 return 0;
1871 }
1872 }
1873
1874 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1875 _rtl8821ae_reset_pcie_interface_dma(hw,
1876 rtlhal->mac_func_enable,
1877 false);
1878 rtlhal->mac_func_enable = false;
1879 }
1880
1881 /* Reset MAC/BB/RF status if it is not powered off
1882 * before calling initialize Hw flow to prevent
1883 * from interface and MAC status mismatch.
1884 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1885 if (rtlhal->mac_func_enable) {
1886 _rtl8821ae_poweroff_adapter(hw);
1887 rtlhal->mac_func_enable = false;
1888 }
1889
1890 rtstatus = _rtl8821ae_init_mac(hw);
1891 if (!rtstatus) {
1892 pr_err("Init MAC failed\n");
1893 err = 1;
1894 return err;
1895 }
1896
1897 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1898 tmp_u1b &= 0x7F;
1899 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1900
1901 err = rtl8821ae_download_fw(hw, false);
1902 if (err) {
1903 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1904 "Failed to download FW. Init HW without FW now\n");
1905 err = 1;
1906 rtlhal->fw_ready = false;
1907 return err;
1908 } else {
1909 rtlhal->fw_ready = true;
1910 }
1911 ppsc->fw_current_inpsmode = false;
1912 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1913 rtlhal->fw_clk_change_in_progress = false;
1914 rtlhal->allow_sw_to_change_hwclc = false;
1915 rtlhal->last_hmeboxnum = 0;
1916
1917 /*SIC_Init(Adapter);
1918 if(rtlhal->AMPDUBurstMode)
1919 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1920
1921 rtl8821ae_phy_mac_config(hw);
1922 /* because last function modify RCR, so we update
1923 * rcr var here, or TP will unstable for receive_config
1924 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1925 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1926 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1927 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1928 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1929 rtl8821ae_phy_bb_config(hw);
1930
1931 rtl8821ae_phy_rf_config(hw);
1932
1933 if (rtlpriv->phy.rf_type == RF_1T1R &&
1934 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1935 _rtl8812ae_bb8812_config_1t(hw);
1936
1937 _rtl8821ae_hw_configure(hw);
1938
1939 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1940
1941 /*set wireless mode*/
1942
1943 rtlhal->mac_func_enable = true;
1944
1945 rtl_cam_reset_all_entry(hw);
1946
1947 rtl8821ae_enable_hw_security_config(hw);
1948
1949 ppsc->rfpwr_state = ERFON;
1950
1951 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1952 _rtl8821ae_enable_aspm_back_door(hw);
1953 rtlpriv->intf_ops->enable_aspm(hw);
1954
1955 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1956 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1957 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1958
1959 rtl8821ae_bt_hw_init(hw);
1960 rtlpriv->rtlhal.being_init_adapter = false;
1961
1962 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1963
1964 /* rtl8821ae_dm_check_txpower_tracking(hw); */
1965 /* rtl8821ae_phy_lc_calibrate(hw); */
1966 if (support_remote_wakeup)
1967 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
1968
1969 /* Release Rx DMA*/
1970 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1971 if (tmp_u1b & BIT(2)) {
1972 /* Release Rx DMA if needed*/
1973 tmp_u1b &= ~BIT(2);
1974 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1975 }
1976
1977 /* Release Tx/Rx PCIE DMA if*/
1978 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1979
1980 rtl8821ae_dm_init(hw);
1981 rtl8821ae_macid_initialize_mediastatus(hw);
1982
1983 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__);
1984 return err;
1985 }
1986
_rtl8821ae_read_chip_version(struct ieee80211_hw * hw)1987 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1988 {
1989 struct rtl_priv *rtlpriv = rtl_priv(hw);
1990 struct rtl_phy *rtlphy = &rtlpriv->phy;
1991 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1992 enum version_8821ae version = VERSION_UNKNOWN;
1993 u32 value32;
1994
1995 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1996 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1997 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
1998
1999 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2000 rtlphy->rf_type = RF_2T2R;
2001 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2002 rtlphy->rf_type = RF_1T1R;
2003
2004 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2005 "RF_Type is %x!!\n", rtlphy->rf_type);
2006
2007 if (value32 & TRP_VAUX_EN) {
2008 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2009 if (rtlphy->rf_type == RF_2T2R)
2010 version = VERSION_TEST_CHIP_2T2R_8812;
2011 else
2012 version = VERSION_TEST_CHIP_1T1R_8812;
2013 } else
2014 version = VERSION_TEST_CHIP_8821;
2015 } else {
2016 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2017 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2018
2019 if (rtlphy->rf_type == RF_2T2R)
2020 version =
2021 (enum version_8821ae)(CHIP_8812
2022 | NORMAL_CHIP |
2023 RF_TYPE_2T2R);
2024 else
2025 version = (enum version_8821ae)(CHIP_8812
2026 | NORMAL_CHIP);
2027
2028 version = (enum version_8821ae)(version | (rtl_id << 12));
2029 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2030 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2031
2032 version = (enum version_8821ae)(CHIP_8821
2033 | NORMAL_CHIP | rtl_id);
2034 }
2035 }
2036
2037 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2038 /*WL_HWROF_EN.*/
2039 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2040 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2041 }
2042
2043 switch (version) {
2044 case VERSION_TEST_CHIP_1T1R_8812:
2045 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2046 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2047 break;
2048 case VERSION_TEST_CHIP_2T2R_8812:
2049 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2050 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2051 break;
2052 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2053 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2054 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2055 break;
2056 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2057 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2058 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2059 break;
2060 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2061 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2062 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2063 break;
2064 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2065 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2066 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2067 break;
2068 case VERSION_TEST_CHIP_8821:
2069 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2070 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2071 break;
2072 case VERSION_NORMAL_TSMC_CHIP_8821:
2073 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2074 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2075 break;
2076 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2077 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2078 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2079 break;
2080 default:
2081 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2082 "Chip Version ID: Unknown (0x%X)\n", version);
2083 break;
2084 }
2085
2086 return version;
2087 }
2088
_rtl8821ae_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)2089 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2090 enum nl80211_iftype type)
2091 {
2092 struct rtl_priv *rtlpriv = rtl_priv(hw);
2093 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2094 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2095 bt_msr &= 0xfc;
2096
2097 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2098 rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
2099 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2100
2101 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2102 type == NL80211_IFTYPE_STATION) {
2103 _rtl8821ae_stop_tx_beacon(hw);
2104 _rtl8821ae_enable_bcn_sub_func(hw);
2105 } else if (type == NL80211_IFTYPE_ADHOC ||
2106 type == NL80211_IFTYPE_AP) {
2107 _rtl8821ae_resume_tx_beacon(hw);
2108 _rtl8821ae_disable_bcn_sub_func(hw);
2109 } else {
2110 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2111 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2112 type);
2113 }
2114
2115 switch (type) {
2116 case NL80211_IFTYPE_UNSPECIFIED:
2117 bt_msr |= MSR_NOLINK;
2118 ledaction = LED_CTL_LINK;
2119 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2120 "Set Network type to NO LINK!\n");
2121 break;
2122 case NL80211_IFTYPE_ADHOC:
2123 bt_msr |= MSR_ADHOC;
2124 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2125 "Set Network type to Ad Hoc!\n");
2126 break;
2127 case NL80211_IFTYPE_STATION:
2128 bt_msr |= MSR_INFRA;
2129 ledaction = LED_CTL_LINK;
2130 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2131 "Set Network type to STA!\n");
2132 break;
2133 case NL80211_IFTYPE_AP:
2134 bt_msr |= MSR_AP;
2135 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2136 "Set Network type to AP!\n");
2137 break;
2138 default:
2139 pr_err("Network type %d not support!\n", type);
2140 return 1;
2141 }
2142
2143 rtl_write_byte(rtlpriv, MSR, bt_msr);
2144 rtlpriv->cfg->ops->led_control(hw, ledaction);
2145 if ((bt_msr & MSR_MASK) == MSR_AP)
2146 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2147 else
2148 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2149
2150 return 0;
2151 }
2152
rtl8821ae_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)2153 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2154 {
2155 struct rtl_priv *rtlpriv = rtl_priv(hw);
2156 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2157 u32 reg_rcr = rtlpci->receive_config;
2158
2159 if (rtlpriv->psc.rfpwr_state != ERFON)
2160 return;
2161
2162 if (check_bssid) {
2163 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2164 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2165 (u8 *)(®_rcr));
2166 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2167 } else if (!check_bssid) {
2168 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2169 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2170 rtlpriv->cfg->ops->set_hw_reg(hw,
2171 HW_VAR_RCR, (u8 *)(®_rcr));
2172 }
2173 }
2174
rtl8821ae_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)2175 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2176 {
2177 struct rtl_priv *rtlpriv = rtl_priv(hw);
2178
2179 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__);
2180
2181 if (_rtl8821ae_set_media_status(hw, type))
2182 return -EOPNOTSUPP;
2183
2184 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2185 if (type != NL80211_IFTYPE_AP)
2186 rtl8821ae_set_check_bssid(hw, true);
2187 } else {
2188 rtl8821ae_set_check_bssid(hw, false);
2189 }
2190
2191 return 0;
2192 }
2193
2194 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
rtl8821ae_set_qos(struct ieee80211_hw * hw,int aci)2195 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2196 {
2197 struct rtl_priv *rtlpriv = rtl_priv(hw);
2198 rtl8821ae_dm_init_edca_turbo(hw);
2199 switch (aci) {
2200 case AC1_BK:
2201 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2202 break;
2203 case AC0_BE:
2204 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2205 break;
2206 case AC2_VI:
2207 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2208 break;
2209 case AC3_VO:
2210 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2211 break;
2212 default:
2213 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2214 break;
2215 }
2216 }
2217
rtl8821ae_clear_interrupt(struct ieee80211_hw * hw)2218 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2219 {
2220 struct rtl_priv *rtlpriv = rtl_priv(hw);
2221 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2222
2223 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2224
2225 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2226 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2227
2228 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2229 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2230 }
2231
rtl8821ae_enable_interrupt(struct ieee80211_hw * hw)2232 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2233 {
2234 struct rtl_priv *rtlpriv = rtl_priv(hw);
2235 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2236
2237 if (rtlpci->int_clear)
2238 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2239
2240 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2241 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2242 rtlpci->irq_enabled = true;
2243 /* there are some C2H CMDs have been sent before
2244 system interrupt is enabled, e.g., C2H, CPWM.
2245 *So we need to clear all C2H events that FW has
2246 notified, otherwise FW won't schedule any commands anymore.
2247 */
2248 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2249 /*enable system interrupt*/
2250 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2251 }
2252
rtl8821ae_disable_interrupt(struct ieee80211_hw * hw)2253 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2254 {
2255 struct rtl_priv *rtlpriv = rtl_priv(hw);
2256 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2257
2258 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2259 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2260 rtlpci->irq_enabled = false;
2261 /*synchronize_irq(rtlpci->pdev->irq);*/
2262 }
2263
_rtl8821ae_clear_pci_pme_status(struct ieee80211_hw * hw)2264 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2265 {
2266 struct rtl_priv *rtlpriv = rtl_priv(hw);
2267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2268 struct pci_dev *pdev = rtlpci->pdev;
2269 u16 pmcs_reg;
2270 u8 pm_cap;
2271
2272 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2273 if (!pm_cap) {
2274 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
2275 "Cannot find PME Capability\n");
2276 return;
2277 }
2278
2279 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pmcs_reg);
2280 if (pmcs_reg & PCI_PM_CTRL_PME_STATUS) {
2281 /* Clear PME_Status with write */
2282 pci_write_config_word(pdev, pm_cap + PCI_PM_CTRL, pmcs_reg);
2283 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pmcs_reg);
2284 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2285 "Cleared PME status, PMCS reg = 0x%4x\n", pmcs_reg);
2286 } else {
2287 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2288 "PMCS reg = 0x%4x\n", pmcs_reg);
2289 }
2290 }
2291
rtl8821ae_card_disable(struct ieee80211_hw * hw)2292 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2293 {
2294 struct rtl_priv *rtlpriv = rtl_priv(hw);
2295 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2296 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2297 struct rtl_mac *mac = rtl_mac(rtlpriv);
2298 enum nl80211_iftype opmode;
2299 bool support_remote_wakeup;
2300 u8 tmp;
2301 u32 count = 0;
2302
2303 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2304 (u8 *)(&support_remote_wakeup));
2305
2306 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2307
2308 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2309 || !rtlhal->enter_pnp_sleep) {
2310 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2311 mac->link_state = MAC80211_NOLINK;
2312 opmode = NL80211_IFTYPE_UNSPECIFIED;
2313 _rtl8821ae_set_media_status(hw, opmode);
2314 _rtl8821ae_poweroff_adapter(hw);
2315 } else {
2316 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2317 /* 3 <1> Prepare for configuring wowlan related infomations */
2318 /* Clear Fw WoWLAN event. */
2319 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2320
2321 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2322 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2323 #endif
2324 /* Dynamically adjust Tx packet boundary
2325 * for download reserved page packet.
2326 * reserve 30 pages for rsvd page */
2327 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2328 rtlhal->re_init_llt_table = true;
2329
2330 /* 3 <2> Set Fw related H2C cmd. */
2331
2332 /* Set WoWLAN related security information. */
2333 rtl8821ae_set_fw_global_info_cmd(hw);
2334
2335 _rtl8821ae_download_rsvd_page(hw, true);
2336
2337 /* Just enable AOAC related functions when we connect to AP. */
2338 printk("mac->link_state = %d\n", mac->link_state);
2339 if (mac->link_state >= MAC80211_LINKED &&
2340 mac->opmode == NL80211_IFTYPE_STATION) {
2341 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2342 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2343 RT_MEDIA_CONNECT);
2344
2345 rtl8821ae_set_fw_wowlan_mode(hw, true);
2346 /* Enable Fw Keep alive mechanism. */
2347 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2348
2349 /* Enable disconnect decision control. */
2350 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2351 }
2352
2353 /* 3 <3> Hw Configurations */
2354
2355 /* Wait until Rx DMA Finished before host sleep.
2356 * FW Pause Rx DMA may happen when received packet doing DMA.
2357 */
2358 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2359
2360 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2361 count = 0;
2362 while (!(tmp & BIT(1)) && (count++ < 100)) {
2363 udelay(10);
2364 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2365 }
2366 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2367 "Wait Rx DMA Finished before host sleep. count=%d\n",
2368 count);
2369
2370 /* reset trx ring */
2371 rtlpriv->intf_ops->reset_trx_ring(hw);
2372
2373 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2374
2375 _rtl8821ae_clear_pci_pme_status(hw);
2376 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2377 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2378 /* prevent 8051 to be reset by PERST */
2379 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2380 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2381 }
2382
2383 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2384 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2385 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2386 /* For wowlan+LPS+32k. */
2387 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2388 /* Set the WoWLAN related function control enable.
2389 * It should be the last H2C cmd in the WoWLAN flow. */
2390 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2391
2392 /* Stop Pcie Interface Tx DMA. */
2393 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2394 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2395
2396 /* Wait for TxDMA idle. */
2397 count = 0;
2398 do {
2399 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2400 udelay(10);
2401 count++;
2402 } while ((tmp != 0) && (count < 100));
2403 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2404 "Wait Tx DMA Finished before host sleep. count=%d\n",
2405 count);
2406
2407 if (rtlhal->hw_rof_enable) {
2408 printk("hw_rof_enable\n");
2409 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2410 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2411 }
2412 }
2413 /* after power off we should do iqk again */
2414 rtlpriv->phy.iqk_initialized = false;
2415 }
2416
rtl8821ae_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)2417 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2418 struct rtl_int *intvec)
2419 {
2420 struct rtl_priv *rtlpriv = rtl_priv(hw);
2421 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2422
2423 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2424 rtl_write_dword(rtlpriv, ISR, intvec->inta);
2425
2426 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2427 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
2428 }
2429
rtl8821ae_set_beacon_related_registers(struct ieee80211_hw * hw)2430 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2431 {
2432 struct rtl_priv *rtlpriv = rtl_priv(hw);
2433 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2434 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2435 u16 bcn_interval, atim_window;
2436
2437 bcn_interval = mac->beacon_interval;
2438 atim_window = 2; /*FIX MERGE */
2439 rtl8821ae_disable_interrupt(hw);
2440 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2441 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2442 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2443 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2444 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2445 rtl_write_byte(rtlpriv, 0x606, 0x30);
2446 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2447 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2448 rtl8821ae_enable_interrupt(hw);
2449 }
2450
rtl8821ae_set_beacon_interval(struct ieee80211_hw * hw)2451 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2452 {
2453 struct rtl_priv *rtlpriv = rtl_priv(hw);
2454 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2455 u16 bcn_interval = mac->beacon_interval;
2456
2457 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
2458 "beacon_interval:%d\n", bcn_interval);
2459 rtl8821ae_disable_interrupt(hw);
2460 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2461 rtl8821ae_enable_interrupt(hw);
2462 }
2463
rtl8821ae_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)2464 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2465 u32 add_msr, u32 rm_msr)
2466 {
2467 struct rtl_priv *rtlpriv = rtl_priv(hw);
2468 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2469
2470 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
2471 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2472
2473 if (add_msr)
2474 rtlpci->irq_mask[0] |= add_msr;
2475 if (rm_msr)
2476 rtlpci->irq_mask[0] &= (~rm_msr);
2477 rtl8821ae_disable_interrupt(hw);
2478 rtl8821ae_enable_interrupt(hw);
2479 }
2480
_rtl8821ae_get_chnl_group(u8 chnl)2481 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2482 {
2483 u8 group = 0;
2484
2485 if (chnl <= 14) {
2486 if (1 <= chnl && chnl <= 2)
2487 group = 0;
2488 else if (3 <= chnl && chnl <= 5)
2489 group = 1;
2490 else if (6 <= chnl && chnl <= 8)
2491 group = 2;
2492 else if (9 <= chnl && chnl <= 11)
2493 group = 3;
2494 else /*if (12 <= chnl && chnl <= 14)*/
2495 group = 4;
2496 } else {
2497 if (36 <= chnl && chnl <= 42)
2498 group = 0;
2499 else if (44 <= chnl && chnl <= 48)
2500 group = 1;
2501 else if (50 <= chnl && chnl <= 58)
2502 group = 2;
2503 else if (60 <= chnl && chnl <= 64)
2504 group = 3;
2505 else if (100 <= chnl && chnl <= 106)
2506 group = 4;
2507 else if (108 <= chnl && chnl <= 114)
2508 group = 5;
2509 else if (116 <= chnl && chnl <= 122)
2510 group = 6;
2511 else if (124 <= chnl && chnl <= 130)
2512 group = 7;
2513 else if (132 <= chnl && chnl <= 138)
2514 group = 8;
2515 else if (140 <= chnl && chnl <= 144)
2516 group = 9;
2517 else if (149 <= chnl && chnl <= 155)
2518 group = 10;
2519 else if (157 <= chnl && chnl <= 161)
2520 group = 11;
2521 else if (165 <= chnl && chnl <= 171)
2522 group = 12;
2523 else if (173 <= chnl && chnl <= 177)
2524 group = 13;
2525 else
2526 WARN_ONCE(true,
2527 "rtl8821ae: 5G, Channel %d in Group not found\n",
2528 chnl);
2529 }
2530 return group;
2531 }
2532
_rtl8821ae_read_power_value_fromprom(struct ieee80211_hw * hw,struct txpower_info_2g * pwrinfo24g,struct txpower_info_5g * pwrinfo5g,bool autoload_fail,u8 * hwinfo)2533 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2534 struct txpower_info_2g *pwrinfo24g,
2535 struct txpower_info_5g *pwrinfo5g,
2536 bool autoload_fail,
2537 u8 *hwinfo)
2538 {
2539 struct rtl_priv *rtlpriv = rtl_priv(hw);
2540 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0;
2541
2542 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2543 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2544 (eeaddr + 1), hwinfo[eeaddr + 1]);
2545 if (hwinfo[eeaddr + 1] == 0xFF) /*YJ,add,120316*/
2546 autoload_fail = true;
2547
2548 if (autoload_fail) {
2549 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2550 "auto load fail : Use Default value!\n");
2551 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2552 /*2.4G default value*/
2553 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2554 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2555 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2556 }
2557 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2558 if (txcount == 0) {
2559 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
2560 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
2561 } else {
2562 pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE;
2563 pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE;
2564 pwrinfo24g->cck_diff[rfpath][txcount] = 0xFE;
2565 pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE;
2566 }
2567 }
2568 /*5G default value*/
2569 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2570 pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A;
2571
2572 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2573 if (txcount == 0) {
2574 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
2575 pwrinfo5g->bw20_diff[rfpath][0] = 0x00;
2576 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2577 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2578 } else {
2579 pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE;
2580 pwrinfo5g->bw20_diff[rfpath][0] = 0xFE;
2581 pwrinfo5g->bw40_diff[rfpath][0] = 0xFE;
2582 pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2583 pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2584 }
2585 }
2586 }
2587 return;
2588 }
2589
2590 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2591
2592 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2593 /*2.4G default value*/
2594 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2595 pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++];
2596 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
2597 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2598 }
2599 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2600 pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2601 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
2602 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2603 }
2604 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2605 if (txcount == 0) {
2606 pwrinfo24g->bw40_diff[rfpath][txcount] = 0;
2607 /*bit sign number to 8 bit sign number*/
2608 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2609 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2610 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2611 /*bit sign number to 8 bit sign number*/
2612 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2613 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2614 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2615
2616 pwrinfo24g->cck_diff[rfpath][txcount] = 0;
2617 eeaddr++;
2618 } else {
2619 pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2620 if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3))
2621 pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0;
2622
2623 pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2624 if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2625 pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2626
2627 eeaddr++;
2628
2629 pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2630 if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2631 pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2632
2633 pwrinfo24g->cck_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2634 if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3))
2635 pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0;
2636
2637 eeaddr++;
2638 }
2639 }
2640
2641 /*5G default value*/
2642 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2643 pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2644 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
2645 pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE;
2646 }
2647
2648 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2649 if (txcount == 0) {
2650 pwrinfo5g->bw40_diff[rfpath][txcount] = 0;
2651
2652 pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4;
2653 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2654 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2655
2656 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f);
2657 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2658 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2659
2660 eeaddr++;
2661 } else {
2662 pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2663 if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3))
2664 pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0;
2665
2666 pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2667 if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2668 pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2669
2670 eeaddr++;
2671 }
2672 }
2673
2674 pwrinfo5g->ofdm_diff[rfpath][1] = (hwinfo[eeaddr] & 0xf0) >> 4;
2675 pwrinfo5g->ofdm_diff[rfpath][2] = (hwinfo[eeaddr] & 0x0f);
2676
2677 eeaddr++;
2678
2679 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f);
2680
2681 eeaddr++;
2682
2683 for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) {
2684 if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2685 pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2686 }
2687 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2688 pwrinfo5g->bw80_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2689 /* 4bit sign number to 8 bit sign number */
2690 if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3))
2691 pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0;
2692 /* 4bit sign number to 8 bit sign number */
2693 pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2694 if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3))
2695 pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0;
2696
2697 eeaddr++;
2698 }
2699 }
2700 }
2701 #if 0
2702 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2703 bool autoload_fail,
2704 u8 *hwinfo)
2705 {
2706 struct rtl_priv *rtlpriv = rtl_priv(hw);
2707 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2708 struct txpower_info_2g pwrinfo24g;
2709 struct txpower_info_5g pwrinfo5g;
2710 u8 rf_path, index;
2711 u8 i;
2712
2713 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2714 &pwrinfo5g, autoload_fail, hwinfo);
2715
2716 for (rf_path = 0; rf_path < 2; rf_path++) {
2717 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2718 index = _rtl8821ae_get_chnl_group(i + 1);
2719
2720 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2721 rtlefuse->txpwrlevel_cck[rf_path][i] =
2722 pwrinfo24g.index_cck_base[rf_path][5];
2723 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2724 pwrinfo24g.index_bw40_base[rf_path][index];
2725 } else {
2726 rtlefuse->txpwrlevel_cck[rf_path][i] =
2727 pwrinfo24g.index_cck_base[rf_path][index];
2728 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2729 pwrinfo24g.index_bw40_base[rf_path][index];
2730 }
2731 }
2732
2733 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2734 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2735 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2736 pwrinfo5g.index_bw40_base[rf_path][index];
2737 }
2738 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2739 u8 upper, lower;
2740 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2741 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2742 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2743
2744 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2745 }
2746 for (i = 0; i < MAX_TX_COUNT; i++) {
2747 rtlefuse->txpwr_cckdiff[rf_path][i] =
2748 pwrinfo24g.cck_diff[rf_path][i];
2749 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2750 pwrinfo24g.ofdm_diff[rf_path][i];
2751 rtlefuse->txpwr_ht20diff[rf_path][i] =
2752 pwrinfo24g.bw20_diff[rf_path][i];
2753 rtlefuse->txpwr_ht40diff[rf_path][i] =
2754 pwrinfo24g.bw40_diff[rf_path][i];
2755
2756 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2757 pwrinfo5g.ofdm_diff[rf_path][i];
2758 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2759 pwrinfo5g.bw20_diff[rf_path][i];
2760 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2761 pwrinfo5g.bw40_diff[rf_path][i];
2762 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2763 pwrinfo5g.bw80_diff[rf_path][i];
2764 }
2765 }
2766
2767 if (!autoload_fail) {
2768 rtlefuse->eeprom_regulatory =
2769 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2770 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2771 rtlefuse->eeprom_regulatory = 0;
2772 } else {
2773 rtlefuse->eeprom_regulatory = 0;
2774 }
2775
2776 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2777 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2778 }
2779 #endif
2780 static noinline_for_stack void
_rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)2781 _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2782 bool autoload_fail, u8 *hwinfo)
2783 {
2784 struct rtl_priv *rtlpriv = rtl_priv(hw);
2785 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2786 struct txpower_info_2g pwrinfo24g;
2787 struct txpower_info_5g pwrinfo5g;
2788 u8 rf_path, index;
2789 u8 i;
2790
2791 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2792 &pwrinfo5g, autoload_fail, hwinfo);
2793
2794 for (rf_path = 0; rf_path < 2; rf_path++) {
2795 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2796 index = _rtl8821ae_get_chnl_group(i + 1);
2797
2798 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2799 rtlefuse->txpwrlevel_cck[rf_path][i] =
2800 pwrinfo24g.index_cck_base[rf_path][5];
2801 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2802 pwrinfo24g.index_bw40_base[rf_path][index];
2803 } else {
2804 rtlefuse->txpwrlevel_cck[rf_path][i] =
2805 pwrinfo24g.index_cck_base[rf_path][index];
2806 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2807 pwrinfo24g.index_bw40_base[rf_path][index];
2808 }
2809 }
2810
2811 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2812 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2813 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2814 pwrinfo5g.index_bw40_base[rf_path][index];
2815 }
2816 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2817 u8 upper, lower;
2818 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2819 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2820 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2821
2822 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2823 }
2824 for (i = 0; i < MAX_TX_COUNT; i++) {
2825 rtlefuse->txpwr_cckdiff[rf_path][i] =
2826 pwrinfo24g.cck_diff[rf_path][i];
2827 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2828 pwrinfo24g.ofdm_diff[rf_path][i];
2829 rtlefuse->txpwr_ht20diff[rf_path][i] =
2830 pwrinfo24g.bw20_diff[rf_path][i];
2831 rtlefuse->txpwr_ht40diff[rf_path][i] =
2832 pwrinfo24g.bw40_diff[rf_path][i];
2833
2834 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2835 pwrinfo5g.ofdm_diff[rf_path][i];
2836 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2837 pwrinfo5g.bw20_diff[rf_path][i];
2838 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2839 pwrinfo5g.bw40_diff[rf_path][i];
2840 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2841 pwrinfo5g.bw80_diff[rf_path][i];
2842 }
2843 }
2844 /*bit0~2*/
2845 if (!autoload_fail) {
2846 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2847 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2848 rtlefuse->eeprom_regulatory = 0;
2849 } else {
2850 rtlefuse->eeprom_regulatory = 0;
2851 }
2852
2853 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2854 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2855 }
2856
_rtl8812ae_read_pa_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)2857 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2858 bool autoload_fail)
2859 {
2860 struct rtl_priv *rtlpriv = rtl_priv(hw);
2861 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2862
2863 if (!autoload_fail) {
2864 rtlhal->pa_type_2g = hwinfo[0XBC];
2865 rtlhal->lna_type_2g = hwinfo[0XBD];
2866 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2867 rtlhal->pa_type_2g = 0;
2868 rtlhal->lna_type_2g = 0;
2869 }
2870 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2871 (rtlhal->pa_type_2g & BIT(4))) ?
2872 1 : 0;
2873 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2874 (rtlhal->lna_type_2g & BIT(3))) ?
2875 1 : 0;
2876
2877 rtlhal->pa_type_5g = hwinfo[0XBC];
2878 rtlhal->lna_type_5g = hwinfo[0XBF];
2879 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2880 rtlhal->pa_type_5g = 0;
2881 rtlhal->lna_type_5g = 0;
2882 }
2883 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2884 (rtlhal->pa_type_5g & BIT(0))) ?
2885 1 : 0;
2886 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2887 (rtlhal->lna_type_5g & BIT(3))) ?
2888 1 : 0;
2889 } else {
2890 rtlhal->external_pa_2g = 0;
2891 rtlhal->external_lna_2g = 0;
2892 rtlhal->external_pa_5g = 0;
2893 rtlhal->external_lna_5g = 0;
2894 }
2895 }
2896
_rtl8812ae_read_amplifier_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)2897 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
2898 bool autoload_fail)
2899 {
2900 struct rtl_priv *rtlpriv = rtl_priv(hw);
2901 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2902
2903 u8 ext_type_pa_2g_a = (hwinfo[0XBD] & BIT(2)) >> 2; /* 0XBD[2] */
2904 u8 ext_type_pa_2g_b = (hwinfo[0XBD] & BIT(6)) >> 6; /* 0XBD[6] */
2905 u8 ext_type_pa_5g_a = (hwinfo[0XBF] & BIT(2)) >> 2; /* 0XBF[2] */
2906 u8 ext_type_pa_5g_b = (hwinfo[0XBF] & BIT(6)) >> 6; /* 0XBF[6] */
2907 /* 0XBD[1:0] */
2908 u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0;
2909 /* 0XBD[5:4] */
2910 u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4;
2911 /* 0XBF[1:0] */
2912 u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0;
2913 /* 0XBF[5:4] */
2914 u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4;
2915
2916 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
2917
2918 /* [2.4G] Path A and B are both extPA */
2919 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
2920 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a;
2921
2922 /* [5G] Path A and B are both extPA */
2923 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
2924 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a;
2925
2926 /* [2.4G] Path A and B are both extLNA */
2927 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2928 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
2929
2930 /* [5G] Path A and B are both extLNA */
2931 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2932 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
2933 }
2934
_rtl8821ae_read_pa_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)2935 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2936 bool autoload_fail)
2937 {
2938 struct rtl_priv *rtlpriv = rtl_priv(hw);
2939 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2940
2941 if (!autoload_fail) {
2942 rtlhal->pa_type_2g = hwinfo[0XBC];
2943 rtlhal->lna_type_2g = hwinfo[0XBD];
2944 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2945 rtlhal->pa_type_2g = 0;
2946 rtlhal->lna_type_2g = 0;
2947 }
2948 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2949 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2950
2951 rtlhal->pa_type_5g = hwinfo[0XBC];
2952 rtlhal->lna_type_5g = hwinfo[0XBF];
2953 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2954 rtlhal->pa_type_5g = 0;
2955 rtlhal->lna_type_5g = 0;
2956 }
2957 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
2958 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
2959 } else {
2960 rtlhal->external_pa_2g = 0;
2961 rtlhal->external_lna_2g = 0;
2962 rtlhal->external_pa_5g = 0;
2963 rtlhal->external_lna_5g = 0;
2964 }
2965 }
2966
_rtl8821ae_read_rfe_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)2967 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
2968 bool autoload_fail)
2969 {
2970 struct rtl_priv *rtlpriv = rtl_priv(hw);
2971 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2972
2973 if (!autoload_fail) {
2974 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
2975 if (rtlhal->external_lna_5g) {
2976 if (rtlhal->external_pa_5g) {
2977 if (rtlhal->external_lna_2g &&
2978 rtlhal->external_pa_2g)
2979 rtlhal->rfe_type = 3;
2980 else
2981 rtlhal->rfe_type = 0;
2982 } else {
2983 rtlhal->rfe_type = 2;
2984 }
2985 } else {
2986 rtlhal->rfe_type = 4;
2987 }
2988 } else {
2989 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
2990
2991 if (rtlhal->rfe_type == 4 &&
2992 (rtlhal->external_pa_5g ||
2993 rtlhal->external_pa_2g ||
2994 rtlhal->external_lna_5g ||
2995 rtlhal->external_lna_2g)) {
2996 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2997 rtlhal->rfe_type = 2;
2998 }
2999 }
3000 } else {
3001 rtlhal->rfe_type = 0x04;
3002 }
3003
3004 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3005 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3006 }
3007
_rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)3008 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3009 bool auto_load_fail, u8 *hwinfo)
3010 {
3011 struct rtl_priv *rtlpriv = rtl_priv(hw);
3012 u8 value;
3013
3014 if (!auto_load_fail) {
3015 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3016 if (((value & 0xe0) >> 5) == 0x1)
3017 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3018 else
3019 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3020 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3021
3022 value = hwinfo[EEPROM_RF_BT_SETTING];
3023 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3024 } else {
3025 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3026 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3027 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3028 }
3029 /*move BT_InitHalVars() to init_sw_vars*/
3030 }
3031
_rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)3032 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3033 bool auto_load_fail, u8 *hwinfo)
3034 {
3035 struct rtl_priv *rtlpriv = rtl_priv(hw);
3036 u8 value;
3037 u32 tmpu_32;
3038
3039 if (!auto_load_fail) {
3040 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3041 if (tmpu_32 & BIT(18))
3042 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3043 else
3044 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3045 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3046
3047 value = hwinfo[EEPROM_RF_BT_SETTING];
3048 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3049 } else {
3050 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3051 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3052 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3053 }
3054 /*move BT_InitHalVars() to init_sw_vars*/
3055 }
3056
_rtl8821ae_read_adapter_info(struct ieee80211_hw * hw,bool b_pseudo_test)3057 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3058 {
3059 struct rtl_priv *rtlpriv = rtl_priv(hw);
3060 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3061 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3062 static const int params[] = {
3063 RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3064 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3065 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3066 COUNTRY_CODE_WORLD_WIDE_13
3067 };
3068 u8 *hwinfo;
3069
3070 if (b_pseudo_test) {
3071 ;/* need add */
3072 }
3073
3074 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3075 if (!hwinfo)
3076 return;
3077
3078 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3079 goto exit;
3080
3081 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3082 hwinfo);
3083
3084 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3085 _rtl8812ae_read_amplifier_type(hw, hwinfo,
3086 rtlefuse->autoload_failflag);
3087 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3088 rtlefuse->autoload_failflag, hwinfo);
3089 } else {
3090 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3091 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3092 rtlefuse->autoload_failflag, hwinfo);
3093 }
3094
3095 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3096 /*board type*/
3097 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3098 if (rtlhal->external_lna_2g != 0)
3099 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3100 if (rtlhal->external_lna_5g != 0)
3101 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3102 if (rtlhal->external_pa_2g != 0)
3103 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3104 if (rtlhal->external_pa_5g != 0)
3105 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3106
3107 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3108 rtlefuse->board_type |= ODM_BOARD_BT;
3109
3110 rtlhal->board_type = rtlefuse->board_type;
3111 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3112 "board_type = 0x%x\n", rtlefuse->board_type);
3113
3114 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3115 if (rtlefuse->eeprom_channelplan == 0xff)
3116 rtlefuse->eeprom_channelplan = 0x7F;
3117
3118 /* set channel plan from efuse */
3119 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3120
3121 /*parse xtal*/
3122 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3123 if (rtlefuse->crystalcap == 0xFF)
3124 rtlefuse->crystalcap = 0x20;
3125
3126 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3127 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3128 rtlefuse->autoload_failflag) {
3129 rtlefuse->apk_thermalmeterignore = true;
3130 rtlefuse->eeprom_thermalmeter = 0xff;
3131 }
3132
3133 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3134 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3135 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3136
3137 if (!rtlefuse->autoload_failflag) {
3138 rtlefuse->antenna_div_cfg =
3139 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3140 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3141 rtlefuse->antenna_div_cfg = 0;
3142
3143 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3144 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3145 rtlefuse->antenna_div_cfg = 0;
3146
3147 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3148 if (rtlefuse->antenna_div_type == 0xff)
3149 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3150 } else {
3151 rtlefuse->antenna_div_cfg = 0;
3152 rtlefuse->antenna_div_type = 0;
3153 }
3154
3155 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3156 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3157 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3158
3159 rtlpriv->ledctl.led_opendrain = true;
3160
3161 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3162 switch (rtlefuse->eeprom_oemid) {
3163 case RT_CID_DEFAULT:
3164 break;
3165 case EEPROM_CID_TOSHIBA:
3166 rtlhal->oem_id = RT_CID_TOSHIBA;
3167 break;
3168 case EEPROM_CID_CCX:
3169 rtlhal->oem_id = RT_CID_CCX;
3170 break;
3171 case EEPROM_CID_QMI:
3172 rtlhal->oem_id = RT_CID_819X_QMI;
3173 break;
3174 case EEPROM_CID_WHQL:
3175 break;
3176 default:
3177 break;
3178 }
3179 }
3180 exit:
3181 kfree(hwinfo);
3182 }
3183
3184 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3185 {
3186 struct rtl_priv *rtlpriv = rtl_priv(hw);
3187 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3188 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3189
3190 rtlpriv->ledctl.led_opendrain = true;
3191 switch (rtlhal->oem_id) {
3192 case RT_CID_819X_HP:
3193 rtlpriv->ledctl.led_opendrain = true;
3194 break;
3195 case RT_CID_819X_LENOVO:
3196 case RT_CID_DEFAULT:
3197 case RT_CID_TOSHIBA:
3198 case RT_CID_CCX:
3199 case RT_CID_819X_ACER:
3200 case RT_CID_WHQL:
3201 default:
3202 break;
3203 }
3204 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
3205 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3206 }*/
3207
rtl8821ae_read_eeprom_info(struct ieee80211_hw * hw)3208 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3209 {
3210 struct rtl_priv *rtlpriv = rtl_priv(hw);
3211 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3212 struct rtl_phy *rtlphy = &rtlpriv->phy;
3213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3214 u8 tmp_u1b;
3215
3216 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3217 if (get_rf_type(rtlphy) == RF_1T1R)
3218 rtlpriv->dm.rfpath_rxenable[0] = true;
3219 else
3220 rtlpriv->dm.rfpath_rxenable[0] =
3221 rtlpriv->dm.rfpath_rxenable[1] = true;
3222 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3223 rtlhal->version);
3224
3225 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3226 if (tmp_u1b & BIT(4)) {
3227 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3228 rtlefuse->epromtype = EEPROM_93C46;
3229 } else {
3230 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3231 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3232 }
3233
3234 if (tmp_u1b & BIT(5)) {
3235 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3236 rtlefuse->autoload_failflag = false;
3237 _rtl8821ae_read_adapter_info(hw, false);
3238 } else {
3239 pr_err("Autoload ERR!!\n");
3240 }
3241 /*hal_ReadRFType_8812A()*/
3242 /* _rtl8821ae_hal_customized_behavior(hw); */
3243 }
3244
rtl8821ae_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)3245 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3246 struct ieee80211_sta *sta)
3247 {
3248 struct rtl_priv *rtlpriv = rtl_priv(hw);
3249 struct rtl_phy *rtlphy = &rtlpriv->phy;
3250 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3251 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3252 u32 ratr_value;
3253 u8 ratr_index = 0;
3254 u8 b_nmode = mac->ht_enable;
3255 u16 shortgi_rate;
3256 u32 tmp_ratr_value;
3257 u32 ratr_mask;
3258 u8 curtxbw_40mhz = mac->bw_40;
3259 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3260 1 : 0;
3261 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3262 1 : 0;
3263 enum wireless_mode wirelessmode = mac->mode;
3264
3265 if (rtlhal->current_bandtype == BAND_ON_5G)
3266 ratr_value = sta->deflink.supp_rates[1] << 4;
3267 else
3268 ratr_value = sta->deflink.supp_rates[0];
3269 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3270 ratr_value = 0xfff;
3271 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
3272 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
3273 switch (wirelessmode) {
3274 case WIRELESS_MODE_B:
3275 if (ratr_value & 0x0000000c)
3276 ratr_value &= 0x0000000d;
3277 else
3278 ratr_value &= 0x0000000f;
3279 break;
3280 case WIRELESS_MODE_G:
3281 ratr_value &= 0x00000FF5;
3282 break;
3283 case WIRELESS_MODE_N_24G:
3284 case WIRELESS_MODE_N_5G:
3285 b_nmode = 1;
3286
3287 if (get_rf_type(rtlphy) == RF_1T2R ||
3288 get_rf_type(rtlphy) == RF_1T1R)
3289 ratr_mask = 0x000ff005;
3290 else
3291 ratr_mask = 0x0f0ff005;
3292
3293 ratr_value &= ratr_mask;
3294 break;
3295 default:
3296 if (rtlphy->rf_type == RF_1T2R)
3297 ratr_value &= 0x000ff0ff;
3298 else
3299 ratr_value &= 0x0f0ff0ff;
3300
3301 break;
3302 }
3303
3304 if ((rtlpriv->btcoexist.bt_coexistence) &&
3305 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3306 (rtlpriv->btcoexist.bt_cur_state) &&
3307 (rtlpriv->btcoexist.bt_ant_isolation) &&
3308 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3309 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3310 ratr_value &= 0x0fffcfc0;
3311 else
3312 ratr_value &= 0x0FFFFFFF;
3313
3314 if (b_nmode && ((curtxbw_40mhz &&
3315 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3316 b_curshortgi_20mhz))) {
3317 ratr_value |= 0x10000000;
3318 tmp_ratr_value = (ratr_value >> 12);
3319
3320 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3321 if ((1 << shortgi_rate) & tmp_ratr_value)
3322 break;
3323 }
3324
3325 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3326 (shortgi_rate << 4) | (shortgi_rate);
3327 }
3328
3329 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3330
3331 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3332 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3333 }
3334
_rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)3335 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3336 {
3337 u8 i, j, tmp_rate;
3338 u32 rate_bitmap = 0;
3339
3340 for (i = j = 0; i < 4; i += 2, j += 10) {
3341 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3342
3343 switch (tmp_rate) {
3344 case 2:
3345 rate_bitmap = rate_bitmap | (0x03ff << j);
3346 break;
3347 case 1:
3348 rate_bitmap = rate_bitmap | (0x01ff << j);
3349 break;
3350 case 0:
3351 rate_bitmap = rate_bitmap | (0x00ff << j);
3352 break;
3353 default:
3354 break;
3355 }
3356 }
3357
3358 return rate_bitmap;
3359 }
3360
_rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,u32 ratr_bitmap)3361 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3362 enum wireless_mode wirelessmode,
3363 u32 ratr_bitmap)
3364 {
3365 struct rtl_priv *rtlpriv = rtl_priv(hw);
3366 struct rtl_phy *rtlphy = &rtlpriv->phy;
3367 u32 ret_bitmap = ratr_bitmap;
3368
3369 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3370 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3371 ret_bitmap = ratr_bitmap;
3372 else if (wirelessmode == WIRELESS_MODE_AC_5G
3373 || wirelessmode == WIRELESS_MODE_AC_24G) {
3374 if (rtlphy->rf_type == RF_1T1R)
3375 ret_bitmap = ratr_bitmap & (~BIT21);
3376 else
3377 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3378 }
3379
3380 return ret_bitmap;
3381 }
3382
_rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,u32 ratr_bitmap)3383 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3384 u32 ratr_bitmap)
3385 {
3386 u8 ret = 0;
3387 if (wirelessmode < WIRELESS_MODE_N_24G)
3388 ret = 0;
3389 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3390 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3391 ret = 3;
3392 else /* Mix, 1SS */
3393 ret = 2;
3394 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3395 ret = 1;
3396 } /* VHT */
3397
3398 return ret << 4;
3399 }
3400
_rtl8821ae_get_ra_ldpc(struct ieee80211_hw * hw,u8 mac_id,struct rtl_sta_info * sta_entry,enum wireless_mode wirelessmode)3401 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3402 u8 mac_id, struct rtl_sta_info *sta_entry,
3403 enum wireless_mode wirelessmode)
3404 {
3405 u8 b_ldpc = 0;
3406 /*not support ldpc, do not open*/
3407 return b_ldpc << 2;
3408 }
3409
_rtl8821ae_get_ra_rftype(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,u32 ratr_bitmap)3410 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3411 enum wireless_mode wirelessmode,
3412 u32 ratr_bitmap)
3413 {
3414 struct rtl_priv *rtlpriv = rtl_priv(hw);
3415 struct rtl_phy *rtlphy = &rtlpriv->phy;
3416 u8 rf_type = RF_1T1R;
3417
3418 if (rtlphy->rf_type == RF_1T1R)
3419 rf_type = RF_1T1R;
3420 else if (wirelessmode == WIRELESS_MODE_AC_5G
3421 || wirelessmode == WIRELESS_MODE_AC_24G
3422 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3423 if (ratr_bitmap & 0xffc00000)
3424 rf_type = RF_2T2R;
3425 } else if (wirelessmode == WIRELESS_MODE_N_5G
3426 || wirelessmode == WIRELESS_MODE_N_24G) {
3427 if (ratr_bitmap & 0xfff00000)
3428 rf_type = RF_2T2R;
3429 }
3430
3431 return rf_type;
3432 }
3433
_rtl8821ae_get_ra_shortgi(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 mac_id)3434 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3435 u8 mac_id)
3436 {
3437 bool b_short_gi = false;
3438 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3439 1 : 0;
3440 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3441 1 : 0;
3442 u8 b_curshortgi_80mhz = 0;
3443 b_curshortgi_80mhz = (sta->deflink.vht_cap.cap &
3444 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3445
3446 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3447 b_short_gi = false;
3448
3449 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3450 || b_curshortgi_20mhz)
3451 b_short_gi = true;
3452
3453 return b_short_gi;
3454 }
3455
rtl8821ae_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)3456 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3457 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3458 {
3459 struct rtl_priv *rtlpriv = rtl_priv(hw);
3460 struct rtl_phy *rtlphy = &rtlpriv->phy;
3461 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3462 struct rtl_sta_info *sta_entry = NULL;
3463 u32 ratr_bitmap;
3464 u8 ratr_index;
3465 enum wireless_mode wirelessmode = 0;
3466 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3467 ? 1 : 0;
3468 bool b_shortgi = false;
3469 u8 rate_mask[7];
3470 u8 macid = 0;
3471 u8 mimo_ps = IEEE80211_SMPS_OFF;
3472 u8 rf_type;
3473
3474 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3475 wirelessmode = sta_entry->wireless_mode;
3476
3477 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3478 "wireless mode = 0x%x\n", wirelessmode);
3479 if (mac->opmode == NL80211_IFTYPE_STATION ||
3480 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3481 curtxbw_40mhz = mac->bw_40;
3482 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3483 mac->opmode == NL80211_IFTYPE_ADHOC)
3484 macid = sta->aid + 1;
3485 if (wirelessmode == WIRELESS_MODE_N_5G ||
3486 wirelessmode == WIRELESS_MODE_AC_5G ||
3487 wirelessmode == WIRELESS_MODE_A)
3488 ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
3489 else
3490 ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_2GHZ];
3491
3492 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3493 ratr_bitmap = 0xfff;
3494
3495 if (wirelessmode == WIRELESS_MODE_N_24G
3496 || wirelessmode == WIRELESS_MODE_N_5G)
3497 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
3498 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
3499 else if (wirelessmode == WIRELESS_MODE_AC_24G
3500 || wirelessmode == WIRELESS_MODE_AC_5G
3501 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3502 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3503 sta->deflink.vht_cap.vht_mcs.rx_mcs_map) << 12;
3504
3505 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3506 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3507
3508 /*mac id owner*/
3509 switch (wirelessmode) {
3510 case WIRELESS_MODE_B:
3511 ratr_index = RATR_INX_WIRELESS_B;
3512 if (ratr_bitmap & 0x0000000c)
3513 ratr_bitmap &= 0x0000000d;
3514 else
3515 ratr_bitmap &= 0x0000000f;
3516 break;
3517 case WIRELESS_MODE_G:
3518 ratr_index = RATR_INX_WIRELESS_GB;
3519
3520 if (rssi_level == 1)
3521 ratr_bitmap &= 0x00000f00;
3522 else if (rssi_level == 2)
3523 ratr_bitmap &= 0x00000ff0;
3524 else
3525 ratr_bitmap &= 0x00000ff5;
3526 break;
3527 case WIRELESS_MODE_A:
3528 ratr_index = RATR_INX_WIRELESS_G;
3529 ratr_bitmap &= 0x00000ff0;
3530 break;
3531 case WIRELESS_MODE_N_24G:
3532 case WIRELESS_MODE_N_5G:
3533 if (wirelessmode == WIRELESS_MODE_N_24G)
3534 ratr_index = RATR_INX_WIRELESS_NGB;
3535 else
3536 ratr_index = RATR_INX_WIRELESS_NG;
3537
3538 if (mimo_ps == IEEE80211_SMPS_STATIC
3539 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3540 if (rssi_level == 1)
3541 ratr_bitmap &= 0x000f0000;
3542 else if (rssi_level == 2)
3543 ratr_bitmap &= 0x000ff000;
3544 else
3545 ratr_bitmap &= 0x000ff005;
3546 } else {
3547 if (rf_type == RF_1T1R) {
3548 if (curtxbw_40mhz) {
3549 if (rssi_level == 1)
3550 ratr_bitmap &= 0x000f0000;
3551 else if (rssi_level == 2)
3552 ratr_bitmap &= 0x000ff000;
3553 else
3554 ratr_bitmap &= 0x000ff015;
3555 } else {
3556 if (rssi_level == 1)
3557 ratr_bitmap &= 0x000f0000;
3558 else if (rssi_level == 2)
3559 ratr_bitmap &= 0x000ff000;
3560 else
3561 ratr_bitmap &= 0x000ff005;
3562 }
3563 } else {
3564 if (curtxbw_40mhz) {
3565 if (rssi_level == 1)
3566 ratr_bitmap &= 0x0fff0000;
3567 else if (rssi_level == 2)
3568 ratr_bitmap &= 0x0ffff000;
3569 else
3570 ratr_bitmap &= 0x0ffff015;
3571 } else {
3572 if (rssi_level == 1)
3573 ratr_bitmap &= 0x0fff0000;
3574 else if (rssi_level == 2)
3575 ratr_bitmap &= 0x0ffff000;
3576 else
3577 ratr_bitmap &= 0x0ffff005;
3578 }
3579 }
3580 }
3581 break;
3582
3583 case WIRELESS_MODE_AC_24G:
3584 ratr_index = RATR_INX_WIRELESS_AC_24N;
3585 if (rssi_level == 1)
3586 ratr_bitmap &= 0xfc3f0000;
3587 else if (rssi_level == 2)
3588 ratr_bitmap &= 0xfffff000;
3589 else
3590 ratr_bitmap &= 0xffffffff;
3591 break;
3592
3593 case WIRELESS_MODE_AC_5G:
3594 ratr_index = RATR_INX_WIRELESS_AC_5N;
3595
3596 if (rf_type == RF_1T1R) {
3597 if (rssi_level == 1) /*add by Gary for ac-series*/
3598 ratr_bitmap &= 0x003f8000;
3599 else if (rssi_level == 2)
3600 ratr_bitmap &= 0x003ff000;
3601 else
3602 ratr_bitmap &= 0x003ff010;
3603 } else {
3604 if (rssi_level == 1)
3605 ratr_bitmap &= 0xfe3f8000;
3606 else if (rssi_level == 2)
3607 ratr_bitmap &= 0xfffff000;
3608 else
3609 ratr_bitmap &= 0xfffff010;
3610 }
3611 break;
3612
3613 default:
3614 ratr_index = RATR_INX_WIRELESS_NGB;
3615
3616 if (rf_type == RF_1T2R)
3617 ratr_bitmap &= 0x000ff0ff;
3618 else
3619 ratr_bitmap &= 0x0f8ff0ff;
3620 break;
3621 }
3622
3623 ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3624 sta_entry->ratr_index = ratr_index;
3625 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3626 ratr_bitmap);
3627
3628 rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3629 "ratr_bitmap :%x\n", ratr_bitmap);
3630
3631 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3632 (ratr_index << 28)); */
3633
3634 rate_mask[0] = macid;
3635 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3636 rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3)
3637 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3638 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3639
3640 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3641 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3642 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3643 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3644
3645 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3646 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3647 ratr_index, ratr_bitmap,
3648 rate_mask[0], rate_mask[1],
3649 rate_mask[2], rate_mask[3],
3650 rate_mask[4], rate_mask[5],
3651 rate_mask[6]);
3652 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3653 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3654 }
3655
rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)3656 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3657 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3658 {
3659 struct rtl_priv *rtlpriv = rtl_priv(hw);
3660 if (rtlpriv->dm.useramask)
3661 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
3662 else
3663 /*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD,
3664 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3665 rtl8821ae_update_hal_rate_table(hw, sta);
3666 }
3667
rtl8821ae_update_channel_access_setting(struct ieee80211_hw * hw)3668 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3669 {
3670 struct rtl_priv *rtlpriv = rtl_priv(hw);
3671 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3672 u16 wireless_mode = mac->mode;
3673 u8 sifs_timer, r2t_sifs;
3674
3675 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3676 (u8 *)&mac->slot_time);
3677 if (wireless_mode == WIRELESS_MODE_G)
3678 sifs_timer = 0x0a;
3679 else
3680 sifs_timer = 0x0e;
3681 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3682
3683 r2t_sifs = 0xa;
3684
3685 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3686 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3687 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3688 if (mac->vendor == PEER_ATH)
3689 r2t_sifs = 0x8;
3690 else
3691 r2t_sifs = 0xa;
3692 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3693 r2t_sifs = 0xa;
3694 }
3695
3696 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3697 }
3698
rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)3699 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3700 {
3701 struct rtl_priv *rtlpriv = rtl_priv(hw);
3702 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3703 struct rtl_phy *rtlphy = &rtlpriv->phy;
3704 enum rf_pwrstate e_rfpowerstate_toset;
3705 u8 u1tmp = 0;
3706 bool b_actuallyset = false;
3707
3708 if (rtlpriv->rtlhal.being_init_adapter)
3709 return false;
3710
3711 if (ppsc->swrf_processing)
3712 return false;
3713
3714 spin_lock(&rtlpriv->locks.rf_ps_lock);
3715 if (ppsc->rfchange_inprogress) {
3716 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3717 return false;
3718 } else {
3719 ppsc->rfchange_inprogress = true;
3720 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3721 }
3722
3723 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3724 rtl_read_byte(rtlpriv,
3725 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3726
3727 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3728
3729 if (rtlphy->polarity_ctl)
3730 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3731 else
3732 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3733
3734 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3735 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3736 "GPIOChangeRF - HW Radio ON, RF ON\n");
3737
3738 e_rfpowerstate_toset = ERFON;
3739 ppsc->hwradiooff = false;
3740 b_actuallyset = true;
3741 } else if ((!ppsc->hwradiooff)
3742 && (e_rfpowerstate_toset == ERFOFF)) {
3743 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3744 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3745
3746 e_rfpowerstate_toset = ERFOFF;
3747 ppsc->hwradiooff = true;
3748 b_actuallyset = true;
3749 }
3750
3751 if (b_actuallyset) {
3752 spin_lock(&rtlpriv->locks.rf_ps_lock);
3753 ppsc->rfchange_inprogress = false;
3754 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3755 } else {
3756 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3757 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3758
3759 spin_lock(&rtlpriv->locks.rf_ps_lock);
3760 ppsc->rfchange_inprogress = false;
3761 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3762 }
3763
3764 *valid = 1;
3765 return !ppsc->hwradiooff;
3766 }
3767
rtl8821ae_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)3768 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3769 u8 *p_macaddr, bool is_group, u8 enc_algo,
3770 bool is_wepkey, bool clear_all)
3771 {
3772 struct rtl_priv *rtlpriv = rtl_priv(hw);
3773 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3774 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3775 u8 *macaddr = p_macaddr;
3776 u32 entry_id = 0;
3777 bool is_pairwise = false;
3778
3779 static u8 cam_const_addr[4][6] = {
3780 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3781 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3782 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3783 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3784 };
3785 static u8 cam_const_broad[] = {
3786 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3787 };
3788
3789 if (clear_all) {
3790 u8 idx = 0;
3791 u8 cam_offset = 0;
3792 u8 clear_number = 5;
3793
3794 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3795
3796 for (idx = 0; idx < clear_number; idx++) {
3797 rtl_cam_mark_invalid(hw, cam_offset + idx);
3798 rtl_cam_empty_entry(hw, cam_offset + idx);
3799
3800 if (idx < 5) {
3801 memset(rtlpriv->sec.key_buf[idx], 0,
3802 MAX_KEY_LEN);
3803 rtlpriv->sec.key_len[idx] = 0;
3804 }
3805 }
3806 } else {
3807 switch (enc_algo) {
3808 case WEP40_ENCRYPTION:
3809 enc_algo = CAM_WEP40;
3810 break;
3811 case WEP104_ENCRYPTION:
3812 enc_algo = CAM_WEP104;
3813 break;
3814 case TKIP_ENCRYPTION:
3815 enc_algo = CAM_TKIP;
3816 break;
3817 case AESCCMP_ENCRYPTION:
3818 enc_algo = CAM_AES;
3819 break;
3820 default:
3821 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3822 "switch case %#x not processed\n", enc_algo);
3823 enc_algo = CAM_TKIP;
3824 break;
3825 }
3826
3827 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3828 macaddr = cam_const_addr[key_index];
3829 entry_id = key_index;
3830 } else {
3831 if (is_group) {
3832 macaddr = cam_const_broad;
3833 entry_id = key_index;
3834 } else {
3835 if (mac->opmode == NL80211_IFTYPE_AP) {
3836 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3837 if (entry_id >= TOTAL_CAM_ENTRY) {
3838 pr_err("an not find free hwsecurity cam entry\n");
3839 return;
3840 }
3841 } else {
3842 entry_id = CAM_PAIRWISE_KEY_POSITION;
3843 }
3844
3845 key_index = PAIRWISE_KEYIDX;
3846 is_pairwise = true;
3847 }
3848 }
3849
3850 if (rtlpriv->sec.key_len[key_index] == 0) {
3851 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3852 "delete one entry, entry_id is %d\n",
3853 entry_id);
3854 if (mac->opmode == NL80211_IFTYPE_AP)
3855 rtl_cam_del_entry(hw, p_macaddr);
3856 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3857 } else {
3858 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3859 "add one entry\n");
3860 if (is_pairwise) {
3861 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3862 "set Pairwise key\n");
3863
3864 rtl_cam_add_one_entry(hw, macaddr, key_index,
3865 entry_id, enc_algo,
3866 CAM_CONFIG_NO_USEDK,
3867 rtlpriv->sec.key_buf[key_index]);
3868 } else {
3869 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3870 "set group key\n");
3871
3872 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3873 rtl_cam_add_one_entry(hw,
3874 rtlefuse->dev_addr,
3875 PAIRWISE_KEYIDX,
3876 CAM_PAIRWISE_KEY_POSITION,
3877 enc_algo,
3878 CAM_CONFIG_NO_USEDK,
3879 rtlpriv->sec.key_buf
3880 [entry_id]);
3881 }
3882
3883 rtl_cam_add_one_entry(hw, macaddr, key_index,
3884 entry_id, enc_algo,
3885 CAM_CONFIG_NO_USEDK,
3886 rtlpriv->sec.key_buf[entry_id]);
3887 }
3888 }
3889 }
3890 }
3891
rtl8821ae_bt_reg_init(struct ieee80211_hw * hw)3892 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
3893 {
3894 struct rtl_priv *rtlpriv = rtl_priv(hw);
3895
3896 /* 0:Low, 1:High, 2:From Efuse. */
3897 rtlpriv->btcoexist.reg_bt_iso = 2;
3898 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3899 rtlpriv->btcoexist.reg_bt_sco = 3;
3900 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3901 rtlpriv->btcoexist.reg_bt_sco = 0;
3902 }
3903
rtl8821ae_bt_hw_init(struct ieee80211_hw * hw)3904 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
3905 {
3906 struct rtl_priv *rtlpriv = rtl_priv(hw);
3907
3908 if (rtlpriv->cfg->ops->get_btc_status())
3909 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3910 }
3911
rtl8821ae_suspend(struct ieee80211_hw * hw)3912 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3913 {
3914 }
3915
rtl8821ae_resume(struct ieee80211_hw * hw)3916 void rtl8821ae_resume(struct ieee80211_hw *hw)
3917 {
3918 }
3919
3920 /* Turn on AAP (RCR:bit 0) for promiscuous mode. */
rtl8821ae_allow_all_destaddr(struct ieee80211_hw * hw,bool allow_all_da,bool write_into_reg)3921 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3922 bool allow_all_da, bool write_into_reg)
3923 {
3924 struct rtl_priv *rtlpriv = rtl_priv(hw);
3925 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3926
3927 if (allow_all_da) /* Set BIT0 */
3928 rtlpci->receive_config |= RCR_AAP;
3929 else /* Clear BIT0 */
3930 rtlpci->receive_config &= ~RCR_AAP;
3931
3932 if (write_into_reg)
3933 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3934
3935 rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
3936 "receive_config=0x%08X, write_into_reg=%d\n",
3937 rtlpci->receive_config, write_into_reg);
3938 }
3939
3940 /* WKFMCAMAddAllEntry8812 */
rtl8821ae_add_wowlan_pattern(struct ieee80211_hw * hw,struct rtl_wow_pattern * rtl_pattern,u8 index)3941 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
3942 struct rtl_wow_pattern *rtl_pattern,
3943 u8 index)
3944 {
3945 struct rtl_priv *rtlpriv = rtl_priv(hw);
3946 u32 cam = 0;
3947 u8 addr = 0;
3948 u16 rxbuf_addr;
3949 u8 tmp, count = 0;
3950 u16 cam_start;
3951 u16 offset;
3952
3953 /* Count the WFCAM entry start offset. */
3954
3955 /* RX page size = 128 byte */
3956 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
3957 /* We should start from the boundary */
3958 cam_start = offset * 128;
3959
3960 /* Enable Rx packet buffer access. */
3961 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
3962 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
3963 /* Set Rx packet buffer offset.
3964 * RXBufer pointer increases 1,
3965 * we can access 8 bytes in Rx packet buffer.
3966 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
3967 * RXBufer addr = (CAM start offset +
3968 * per entry offset of a WKFM CAM)/8
3969 * * index: The index of the wake up frame mask
3970 * * WKFMCAM_SIZE: the total size of one WKFM CAM
3971 * * per entry offset of a WKFM CAM: Addr*4 bytes
3972 */
3973 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
3974 /* Set R/W start offset */
3975 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
3976
3977 if (addr == 0) {
3978 cam = BIT(31) | rtl_pattern->crc;
3979
3980 if (rtl_pattern->type == UNICAST_PATTERN)
3981 cam |= BIT(24);
3982 else if (rtl_pattern->type == MULTICAST_PATTERN)
3983 cam |= BIT(25);
3984 else if (rtl_pattern->type == BROADCAST_PATTERN)
3985 cam |= BIT(26);
3986
3987 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
3988 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
3989 "WRITE entry[%d] 0x%x: %x\n", addr,
3990 REG_PKTBUF_DBG_DATA_L, cam);
3991
3992 /* Write to Rx packet buffer. */
3993 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
3994 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
3995 cam = rtl_pattern->mask[addr - 2];
3996
3997 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
3998 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
3999 "WRITE entry[%d] 0x%x: %x\n", addr,
4000 REG_PKTBUF_DBG_DATA_L, cam);
4001
4002 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4003 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4004 cam = rtl_pattern->mask[addr - 2];
4005
4006 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4007 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4008 "WRITE entry[%d] 0x%x: %x\n", addr,
4009 REG_PKTBUF_DBG_DATA_H, cam);
4010
4011 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4012 }
4013
4014 count = 0;
4015 do {
4016 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4017 udelay(2);
4018 count++;
4019 } while (tmp && count < 100);
4020
4021 WARN_ONCE((count >= 100),
4022 "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4023 tmp);
4024 }
4025 /* Disable Rx packet buffer access. */
4026 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4027 DISABLE_TRXPKT_BUF_ACCESS);
4028 }
4029