1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/bitops.h>
8 #include <linux/clk.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
15
16 #include <linux/phy/phy.h>
17 #include <linux/phy/phy-mipi-dphy.h>
18
19 #define REG_WAKEUP_TIME_NS 800
20 #define DPHY_PLL_RATE_HZ 108000000
21 #define POLL_TIMEOUT_US 1000
22
23 /* DPHY registers */
24 #define DPHY_PMA_CMN(reg) (reg)
25 #define DPHY_PMA_LCLK(reg) (0x100 + (reg))
26 #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
27 #define DPHY_PMA_RCLK(reg) (0x600 + (reg))
28 #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
29 #define DPHY_PCS(reg) (0xb00 + (reg))
30
31 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
32 #define DPHY_CMN_SSM_EN BIT(0)
33 #define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1)
34 #define DPHY_CMN_TX_MODE_EN BIT(9)
35
36 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
37 #define DPHY_CMN_PWM_DIV(x) ((x) << 20)
38 #define DPHY_CMN_PWM_LOW(x) ((x) << 10)
39 #define DPHY_CMN_PWM_HIGH(x) (x)
40
41 #define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
42 #define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
43 #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
44
45 #define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
46 #define DPHY_CMN_IPDIV_FROM_REG BIT(0)
47 #define DPHY_CMN_IPDIV(x) ((x) << 1)
48 #define DPHY_CMN_OPDIV_FROM_REG BIT(6)
49 #define DPHY_CMN_OPDIV(x) ((x) << 7)
50
51 #define DPHY_BAND_CFG DPHY_PCS(0x0)
52 #define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0)
53 #define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5)
54
55 #define DPHY_PSM_CFG DPHY_PCS(0x4)
56 #define DPHY_PSM_CFG_FROM_REG BIT(0)
57 #define DPHY_PSM_CLK_DIV(x) ((x) << 1)
58
59 #define DPHY_TX_J721E_WIZ_PLL_CTRL 0xF04
60 #define DPHY_TX_J721E_WIZ_STATUS 0xF08
61 #define DPHY_TX_J721E_WIZ_RST_CTRL 0xF0C
62 #define DPHY_TX_J721E_WIZ_PSM_FREQ 0xF10
63
64 #define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0)
65 #define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8)
66 #define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16)
67 #define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31)
68 #define DPHY_TX_WIZ_PLL_LOCK BIT(31)
69 #define DPHY_TX_WIZ_O_CMN_READY BIT(31)
70
71 struct cdns_dphy_cfg {
72 u8 pll_ipdiv;
73 u8 pll_opdiv;
74 u16 pll_fbdiv;
75 u32 hs_clk_rate;
76 unsigned int nlanes;
77 };
78
79 enum cdns_dphy_clk_lane_cfg {
80 DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
81 DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
82 DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
83 DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
84 };
85
86 struct cdns_dphy;
87 struct cdns_dphy_ops {
88 int (*probe)(struct cdns_dphy *dphy);
89 void (*remove)(struct cdns_dphy *dphy);
90 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
91 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
92 enum cdns_dphy_clk_lane_cfg cfg);
93 void (*set_pll_cfg)(struct cdns_dphy *dphy,
94 const struct cdns_dphy_cfg *cfg);
95 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
96 int (*wait_for_pll_lock)(struct cdns_dphy *dphy);
97 int (*wait_for_cmn_ready)(struct cdns_dphy *dphy);
98 };
99
100 struct cdns_dphy {
101 struct cdns_dphy_cfg cfg;
102 void __iomem *regs;
103 struct clk *psm_clk;
104 struct clk *pll_ref_clk;
105 const struct cdns_dphy_ops *ops;
106 struct phy *phy;
107 bool is_configured;
108 bool is_powered;
109 };
110
111 /* Order of bands is important since the index is the band number. */
112 static const unsigned int tx_bands[] = {
113 80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770,
114 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
115 };
116
cdns_dphy_get_pll_cfg(struct cdns_dphy * dphy,struct cdns_dphy_cfg * cfg,struct phy_configure_opts_mipi_dphy * opts)117 static int cdns_dphy_get_pll_cfg(struct cdns_dphy *dphy,
118 struct cdns_dphy_cfg *cfg,
119 struct phy_configure_opts_mipi_dphy *opts)
120 {
121 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
122 u64 dlane_bps;
123
124 memset(cfg, 0, sizeof(*cfg));
125
126 if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
127 return -EINVAL;
128 else if (pll_ref_hz < 19200000)
129 cfg->pll_ipdiv = 1;
130 else if (pll_ref_hz < 38400000)
131 cfg->pll_ipdiv = 2;
132 else if (pll_ref_hz < 76800000)
133 cfg->pll_ipdiv = 4;
134 else
135 cfg->pll_ipdiv = 8;
136
137 dlane_bps = opts->hs_clk_rate;
138
139 if (dlane_bps > 2500000000UL || dlane_bps < 80000000UL)
140 return -EINVAL;
141 else if (dlane_bps >= 1250000000)
142 cfg->pll_opdiv = 1;
143 else if (dlane_bps >= 630000000)
144 cfg->pll_opdiv = 2;
145 else if (dlane_bps >= 320000000)
146 cfg->pll_opdiv = 4;
147 else if (dlane_bps >= 160000000)
148 cfg->pll_opdiv = 8;
149 else if (dlane_bps >= 80000000)
150 cfg->pll_opdiv = 16;
151
152 cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
153 cfg->pll_ipdiv,
154 pll_ref_hz);
155
156 cfg->hs_clk_rate = div_u64((u64)pll_ref_hz * cfg->pll_fbdiv,
157 2 * cfg->pll_opdiv * cfg->pll_ipdiv);
158
159 return 0;
160 }
161
cdns_dphy_setup_psm(struct cdns_dphy * dphy)162 static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
163 {
164 unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
165 unsigned long psm_div;
166
167 if (!psm_clk_hz || psm_clk_hz > 100000000)
168 return -EINVAL;
169
170 psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
171 if (dphy->ops->set_psm_div)
172 dphy->ops->set_psm_div(dphy, psm_div);
173
174 return 0;
175 }
176
cdns_dphy_set_clk_lane_cfg(struct cdns_dphy * dphy,enum cdns_dphy_clk_lane_cfg cfg)177 static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
178 enum cdns_dphy_clk_lane_cfg cfg)
179 {
180 if (dphy->ops->set_clk_lane_cfg)
181 dphy->ops->set_clk_lane_cfg(dphy, cfg);
182 }
183
cdns_dphy_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)184 static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
185 const struct cdns_dphy_cfg *cfg)
186 {
187 if (dphy->ops->set_pll_cfg)
188 dphy->ops->set_pll_cfg(dphy, cfg);
189 }
190
cdns_dphy_get_wakeup_time_ns(struct cdns_dphy * dphy)191 static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
192 {
193 return dphy->ops->get_wakeup_time_ns(dphy);
194 }
195
cdns_dphy_wait_for_pll_lock(struct cdns_dphy * dphy)196 static int cdns_dphy_wait_for_pll_lock(struct cdns_dphy *dphy)
197 {
198 return dphy->ops->wait_for_pll_lock ? dphy->ops->wait_for_pll_lock(dphy) : 0;
199 }
200
cdns_dphy_wait_for_cmn_ready(struct cdns_dphy * dphy)201 static int cdns_dphy_wait_for_cmn_ready(struct cdns_dphy *dphy)
202 {
203 return dphy->ops->wait_for_cmn_ready ? dphy->ops->wait_for_cmn_ready(dphy) : 0;
204 }
205
cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy * dphy)206 static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
207 {
208 /* Default wakeup time is 800 ns (in a simulated environment). */
209 return 800;
210 }
211
cdns_dphy_ref_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)212 static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
213 const struct cdns_dphy_cfg *cfg)
214 {
215 u32 fbdiv_low, fbdiv_high;
216
217 fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
218 fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
219
220 writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
221 DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
222 DPHY_CMN_OPDIV(cfg->pll_opdiv),
223 dphy->regs + DPHY_CMN_OPIPDIV);
224 writel(DPHY_CMN_FBDIV_FROM_REG |
225 DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
226 dphy->regs + DPHY_CMN_FBDIV);
227 writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
228 DPHY_CMN_PWM_DIV(0x8),
229 dphy->regs + DPHY_CMN_PWM);
230 }
231
cdns_dphy_ref_set_psm_div(struct cdns_dphy * dphy,u8 div)232 static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
233 {
234 writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
235 dphy->regs + DPHY_PSM_CFG);
236 }
237
cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy * dphy)238 static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy)
239 {
240 /* Minimum wakeup time as per MIPI D-PHY spec v1.2 */
241 return 1000000;
242 }
243
cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy * dphy,const struct cdns_dphy_cfg * cfg)244 static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy,
245 const struct cdns_dphy_cfg *cfg)
246 {
247
248 /*
249 * set the PWM and PLL Byteclk divider settings to recommended values
250 * which is same as that of in ref ops
251 */
252 writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
253 DPHY_CMN_PWM_DIV(0x8),
254 dphy->regs + DPHY_CMN_PWM);
255
256 writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) |
257 FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) |
258 FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)),
259 dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL);
260
261 writel(DPHY_TX_J721E_WIZ_LANE_RSTB,
262 dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL);
263 }
264
cdns_dphy_j721e_set_psm_div(struct cdns_dphy * dphy,u8 div)265 static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div)
266 {
267 writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ);
268 }
269
cdns_dphy_j721e_wait_for_pll_lock(struct cdns_dphy * dphy)270 static int cdns_dphy_j721e_wait_for_pll_lock(struct cdns_dphy *dphy)
271 {
272 u32 status;
273
274 return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status,
275 status & DPHY_TX_WIZ_PLL_LOCK, 0, POLL_TIMEOUT_US);
276 }
277
cdns_dphy_j721e_wait_for_cmn_ready(struct cdns_dphy * dphy)278 static int cdns_dphy_j721e_wait_for_cmn_ready(struct cdns_dphy *dphy)
279 {
280 u32 status;
281
282 return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status,
283 status & DPHY_TX_WIZ_O_CMN_READY, 0,
284 POLL_TIMEOUT_US);
285 }
286
287 /*
288 * This is the reference implementation of DPHY hooks. Specific integration of
289 * this IP may have to re-implement some of them depending on how they decided
290 * to wire things in the SoC.
291 */
292 static const struct cdns_dphy_ops ref_dphy_ops = {
293 .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
294 .set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
295 .set_psm_div = cdns_dphy_ref_set_psm_div,
296 };
297
298 static const struct cdns_dphy_ops j721e_dphy_ops = {
299 .get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns,
300 .set_pll_cfg = cdns_dphy_j721e_set_pll_cfg,
301 .set_psm_div = cdns_dphy_j721e_set_psm_div,
302 .wait_for_pll_lock = cdns_dphy_j721e_wait_for_pll_lock,
303 .wait_for_cmn_ready = cdns_dphy_j721e_wait_for_cmn_ready,
304 };
305
cdns_dphy_config_from_opts(struct phy * phy,struct phy_configure_opts_mipi_dphy * opts,struct cdns_dphy_cfg * cfg)306 static int cdns_dphy_config_from_opts(struct phy *phy,
307 struct phy_configure_opts_mipi_dphy *opts,
308 struct cdns_dphy_cfg *cfg)
309 {
310 struct cdns_dphy *dphy = phy_get_drvdata(phy);
311 int ret;
312
313 ret = phy_mipi_dphy_config_validate(opts);
314 if (ret)
315 return ret;
316
317 ret = cdns_dphy_get_pll_cfg(dphy, cfg, opts);
318 if (ret)
319 return ret;
320
321 opts->hs_clk_rate = cfg->hs_clk_rate;
322 opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
323
324 return 0;
325 }
326
cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)327 static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)
328 {
329 unsigned int rate;
330 int i;
331
332 rate = hs_clk_rate / 1000000UL;
333
334 if (rate < tx_bands[0])
335 return -EOPNOTSUPP;
336
337 for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) {
338 if (rate >= tx_bands[i] && rate < tx_bands[i + 1])
339 return i;
340 }
341
342 return -EOPNOTSUPP;
343 }
344
cdns_dphy_validate(struct phy * phy,enum phy_mode mode,int submode,union phy_configure_opts * opts)345 static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
346 union phy_configure_opts *opts)
347 {
348 struct cdns_dphy_cfg cfg = { 0 };
349
350 if (mode != PHY_MODE_MIPI_DPHY)
351 return -EINVAL;
352
353 return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
354 }
355
cdns_dphy_configure(struct phy * phy,union phy_configure_opts * opts)356 static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
357 {
358 struct cdns_dphy *dphy = phy_get_drvdata(phy);
359 int ret;
360
361 ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &dphy->cfg);
362 if (!ret)
363 dphy->is_configured = true;
364
365 return ret;
366 }
367
cdns_dphy_power_on(struct phy * phy)368 static int cdns_dphy_power_on(struct phy *phy)
369 {
370 struct cdns_dphy *dphy = phy_get_drvdata(phy);
371 int ret;
372 u32 reg;
373
374 if (!dphy->is_configured || dphy->is_powered)
375 return -EINVAL;
376
377 clk_prepare_enable(dphy->psm_clk);
378 clk_prepare_enable(dphy->pll_ref_clk);
379
380 /*
381 * Configure the internal PSM clk divider so that the DPHY has a
382 * 1MHz clk (or something close).
383 */
384 ret = cdns_dphy_setup_psm(dphy);
385 if (ret) {
386 dev_err(&dphy->phy->dev, "Failed to setup PSM with error %d\n", ret);
387 goto err_power_on;
388 }
389
390 /*
391 * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
392 * and 8 data lanes, each clk lane can be attache different set of
393 * data lanes. The 2 groups are named 'left' and 'right', so here we
394 * just say that we want the 'left' clk lane to drive the 'left' data
395 * lanes.
396 */
397 cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
398
399 /*
400 * Configure the DPHY PLL that will be used to generate the TX byte
401 * clk.
402 */
403 cdns_dphy_set_pll_cfg(dphy, &dphy->cfg);
404
405 ret = cdns_dphy_tx_get_band_ctrl(dphy->cfg.hs_clk_rate);
406 if (ret < 0) {
407 dev_err(&dphy->phy->dev, "Failed to get band control value with error %d\n", ret);
408 goto err_power_on;
409 }
410
411 reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, ret) |
412 FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, ret);
413 writel(reg, dphy->regs + DPHY_BAND_CFG);
414
415 /* Start TX state machine. */
416 reg = readl(dphy->regs + DPHY_CMN_SSM);
417 writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
418 dphy->regs + DPHY_CMN_SSM);
419
420 ret = cdns_dphy_wait_for_pll_lock(dphy);
421 if (ret) {
422 dev_err(&dphy->phy->dev, "Failed to lock PLL with error %d\n", ret);
423 goto err_power_on;
424 }
425
426 ret = cdns_dphy_wait_for_cmn_ready(dphy);
427 if (ret) {
428 dev_err(&dphy->phy->dev, "O_CMN_READY signal failed to assert with error %d\n",
429 ret);
430 goto err_power_on;
431 }
432
433 dphy->is_powered = true;
434
435 return 0;
436
437 err_power_on:
438 clk_disable_unprepare(dphy->pll_ref_clk);
439 clk_disable_unprepare(dphy->psm_clk);
440
441 return ret;
442 }
443
cdns_dphy_power_off(struct phy * phy)444 static int cdns_dphy_power_off(struct phy *phy)
445 {
446 struct cdns_dphy *dphy = phy_get_drvdata(phy);
447 u32 reg;
448
449 clk_disable_unprepare(dphy->pll_ref_clk);
450 clk_disable_unprepare(dphy->psm_clk);
451
452 /* Stop TX state machine. */
453 reg = readl(dphy->regs + DPHY_CMN_SSM);
454 writel(reg & ~DPHY_CMN_SSM_EN, dphy->regs + DPHY_CMN_SSM);
455
456 dphy->is_powered = false;
457
458 return 0;
459 }
460
461 static const struct phy_ops cdns_dphy_ops = {
462 .configure = cdns_dphy_configure,
463 .validate = cdns_dphy_validate,
464 .power_on = cdns_dphy_power_on,
465 .power_off = cdns_dphy_power_off,
466 };
467
cdns_dphy_probe(struct platform_device * pdev)468 static int cdns_dphy_probe(struct platform_device *pdev)
469 {
470 struct phy_provider *phy_provider;
471 struct cdns_dphy *dphy;
472 int ret;
473
474 dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
475 if (!dphy)
476 return -ENOMEM;
477 dev_set_drvdata(&pdev->dev, dphy);
478
479 dphy->ops = of_device_get_match_data(&pdev->dev);
480 if (!dphy->ops)
481 return -EINVAL;
482
483 dphy->regs = devm_platform_ioremap_resource(pdev, 0);
484 if (IS_ERR(dphy->regs))
485 return PTR_ERR(dphy->regs);
486
487 dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
488 if (IS_ERR(dphy->psm_clk))
489 return PTR_ERR(dphy->psm_clk);
490
491 dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
492 if (IS_ERR(dphy->pll_ref_clk))
493 return PTR_ERR(dphy->pll_ref_clk);
494
495 if (dphy->ops->probe) {
496 ret = dphy->ops->probe(dphy);
497 if (ret)
498 return ret;
499 }
500
501 dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
502 if (IS_ERR(dphy->phy)) {
503 dev_err(&pdev->dev, "failed to create PHY\n");
504 if (dphy->ops->remove)
505 dphy->ops->remove(dphy);
506 return PTR_ERR(dphy->phy);
507 }
508
509 phy_set_drvdata(dphy->phy, dphy);
510 phy_provider = devm_of_phy_provider_register(&pdev->dev,
511 of_phy_simple_xlate);
512
513 return PTR_ERR_OR_ZERO(phy_provider);
514 }
515
cdns_dphy_remove(struct platform_device * pdev)516 static void cdns_dphy_remove(struct platform_device *pdev)
517 {
518 struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
519
520 if (dphy->ops->remove)
521 dphy->ops->remove(dphy);
522 }
523
524 static const struct of_device_id cdns_dphy_of_match[] = {
525 { .compatible = "cdns,dphy", .data = &ref_dphy_ops },
526 { .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops },
527 { /* sentinel */ },
528 };
529 MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
530
531 static struct platform_driver cdns_dphy_platform_driver = {
532 .probe = cdns_dphy_probe,
533 .remove = cdns_dphy_remove,
534 .driver = {
535 .name = "cdns-mipi-dphy",
536 .of_match_table = cdns_dphy_of_match,
537 },
538 };
539 module_platform_driver(cdns_dphy_platform_driver);
540
541 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
542 MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
543 MODULE_LICENSE("GPL");
544