1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7 #ifndef __DRV_CLK_MTK_PLL_H
8 #define __DRV_CLK_MTK_PLL_H
9
10 #include <linux/clk-provider.h>
11 #include <linux/types.h>
12
13 struct clk_ops;
14 struct clk_hw_onecell_data;
15 struct device_node;
16
17 struct mtk_pll_div_table {
18 u32 div;
19 unsigned long freq;
20 };
21
22 #define HAVE_RST_BAR BIT(0)
23 #define PLL_AO BIT(1)
24 #define POSTDIV_MASK GENMASK(2, 0)
25
26 struct mtk_pll_data {
27 int id;
28 const char *name;
29 u32 reg;
30 u32 pwr_reg;
31 u32 en_mask;
32 u32 fenc_sta_ofs;
33 u32 pd_reg;
34 u32 tuner_reg;
35 u32 tuner_en_reg;
36 u8 tuner_en_bit;
37 int pd_shift;
38 unsigned int flags;
39 const struct clk_ops *ops;
40 u32 rst_bar_mask;
41 unsigned long fmin;
42 unsigned long fmax;
43 int pcwbits;
44 int pcwibits;
45 u32 pcw_reg;
46 int pcw_shift;
47 u32 pcw_chg_reg;
48 const struct mtk_pll_div_table *div_table;
49 const char *parent_name;
50 u32 en_reg;
51 u32 en_set_reg;
52 u32 en_clr_reg;
53 u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
54 u8 pcw_chg_bit;
55 u8 fenc_sta_bit;
56 };
57
58 /*
59 * MediaTek PLLs are configured through their pcw value. The pcw value describes
60 * a divider in the PLL feedback loop which consists of 7 bits for the integer
61 * part and the remaining bits (if present) for the fractional part. Also they
62 * have a 3 bit power-of-two post divider.
63 */
64
65 struct mtk_clk_pll {
66 struct clk_hw hw;
67 void __iomem *base_addr;
68 void __iomem *pd_addr;
69 void __iomem *pwr_addr;
70 void __iomem *tuner_addr;
71 void __iomem *tuner_en_addr;
72 void __iomem *pcw_addr;
73 void __iomem *pcw_chg_addr;
74 void __iomem *en_addr;
75 void __iomem *en_set_addr;
76 void __iomem *en_clr_addr;
77 void __iomem *fenc_addr;
78 const struct mtk_pll_data *data;
79 };
80
81 int mtk_clk_register_plls(struct device_node *node,
82 const struct mtk_pll_data *plls, int num_plls,
83 struct clk_hw_onecell_data *clk_data);
84 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
85 struct clk_hw_onecell_data *clk_data);
86
87 extern const struct clk_ops mtk_pll_ops;
88 extern const struct clk_ops mtk_pll_fenc_clr_set_ops;
89
to_mtk_clk_pll(struct clk_hw * hw)90 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
91 {
92 return container_of(hw, struct mtk_clk_pll, hw);
93 }
94
95 int mtk_pll_is_prepared(struct clk_hw *hw);
96
97 int mtk_pll_prepare(struct clk_hw *hw);
98
99 void mtk_pll_unprepare(struct clk_hw *hw);
100
101 unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
102
103 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
104 u32 freq, u32 fin);
105 int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long parent_rate);
107 int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req);
108
109 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
110 const struct mtk_pll_data *data,
111 void __iomem *base,
112 const struct clk_ops *pll_ops);
113 struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
114 void __iomem *base);
115 void mtk_clk_unregister_pll(struct clk_hw *hw);
116
117 __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
118 const struct mtk_pll_data *data);
119
120 #endif /* __DRV_CLK_MTK_PLL_H */
121