xref: /linux/drivers/gpio/gpio-pl061.c (revision fcb117e0758d1462128a50c5788555e03b48833b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2008, 2009 Provigent Ltd.
4  *
5  * Author: Baruch Siach <baruch@tkos.co.il>
6  *
7  * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
8  *
9  * Data sheet: ARM DDI 0190B, September 2000
10  */
11 #include <linux/amba/bus.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/errno.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/module.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pm.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 
29 #define GPIODIR 0x400
30 #define GPIOIS  0x404
31 #define GPIOIBE 0x408
32 #define GPIOIEV 0x40C
33 #define GPIOIE  0x410
34 #define GPIORIS 0x414
35 #define GPIOMIS 0x418
36 #define GPIOIC  0x41C
37 
38 #define PL061_GPIO_NR	8
39 
40 #ifdef CONFIG_PM
41 struct pl061_context_save_regs {
42 	u8 gpio_data;
43 	u8 gpio_dir;
44 	u8 gpio_is;
45 	u8 gpio_ibe;
46 	u8 gpio_iev;
47 	u8 gpio_ie;
48 };
49 #endif
50 
51 struct pl061 {
52 	raw_spinlock_t		lock;
53 
54 	void __iomem		*base;
55 	struct gpio_chip	gc;
56 	int			parent_irq;
57 
58 #ifdef CONFIG_PM
59 	struct pl061_context_save_regs csave_regs;
60 #endif
61 };
62 
pl061_get_direction(struct gpio_chip * gc,unsigned offset)63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
64 {
65 	struct pl061 *pl061 = gpiochip_get_data(gc);
66 
67 	if (readb(pl061->base + GPIODIR) & BIT(offset))
68 		return GPIO_LINE_DIRECTION_OUT;
69 
70 	return GPIO_LINE_DIRECTION_IN;
71 }
72 
pl061_direction_input(struct gpio_chip * gc,unsigned offset)73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
74 {
75 	struct pl061 *pl061 = gpiochip_get_data(gc);
76 	unsigned long flags;
77 	unsigned char gpiodir;
78 
79 	raw_spin_lock_irqsave(&pl061->lock, flags);
80 	gpiodir = readb(pl061->base + GPIODIR);
81 	gpiodir &= ~(BIT(offset));
82 	writeb(gpiodir, pl061->base + GPIODIR);
83 	raw_spin_unlock_irqrestore(&pl061->lock, flags);
84 
85 	return 0;
86 }
87 
pl061_direction_output(struct gpio_chip * gc,unsigned offset,int value)88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
89 		int value)
90 {
91 	struct pl061 *pl061 = gpiochip_get_data(gc);
92 	unsigned long flags;
93 	unsigned char gpiodir;
94 
95 	raw_spin_lock_irqsave(&pl061->lock, flags);
96 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
97 	gpiodir = readb(pl061->base + GPIODIR);
98 	gpiodir |= BIT(offset);
99 	writeb(gpiodir, pl061->base + GPIODIR);
100 
101 	/*
102 	 * gpio value is set again, because pl061 doesn't allow to set value of
103 	 * a gpio pin before configuring it in OUT mode.
104 	 */
105 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
106 	raw_spin_unlock_irqrestore(&pl061->lock, flags);
107 
108 	return 0;
109 }
110 
pl061_get_value(struct gpio_chip * gc,unsigned offset)111 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
112 {
113 	struct pl061 *pl061 = gpiochip_get_data(gc);
114 
115 	return !!readb(pl061->base + (BIT(offset + 2)));
116 }
117 
pl061_set_value(struct gpio_chip * gc,unsigned int offset,int value)118 static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value)
119 {
120 	struct pl061 *pl061 = gpiochip_get_data(gc);
121 
122 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
123 
124 	return 0;
125 }
126 
pl061_irq_type(struct irq_data * d,unsigned trigger)127 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
128 {
129 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
130 	struct pl061 *pl061 = gpiochip_get_data(gc);
131 	int offset = irqd_to_hwirq(d);
132 	unsigned long flags;
133 	u8 gpiois, gpioibe, gpioiev;
134 	u8 bit = BIT(offset);
135 
136 	if (offset < 0 || offset >= PL061_GPIO_NR)
137 		return -EINVAL;
138 
139 	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
140 	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
141 	{
142 		dev_err(gc->parent,
143 			"trying to configure line %d for both level and edge "
144 			"detection, choose one!\n",
145 			offset);
146 		return -EINVAL;
147 	}
148 
149 
150 	raw_spin_lock_irqsave(&pl061->lock, flags);
151 
152 	gpioiev = readb(pl061->base + GPIOIEV);
153 	gpiois = readb(pl061->base + GPIOIS);
154 	gpioibe = readb(pl061->base + GPIOIBE);
155 
156 	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
157 		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
158 
159 		/* Disable edge detection */
160 		gpioibe &= ~bit;
161 		/* Enable level detection */
162 		gpiois |= bit;
163 		/* Select polarity */
164 		if (polarity)
165 			gpioiev |= bit;
166 		else
167 			gpioiev &= ~bit;
168 		irq_set_handler_locked(d, handle_level_irq);
169 		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
170 			offset,
171 			polarity ? "HIGH" : "LOW");
172 	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
173 		/* Disable level detection */
174 		gpiois &= ~bit;
175 		/* Select both edges, setting this makes GPIOEV be ignored */
176 		gpioibe |= bit;
177 		irq_set_handler_locked(d, handle_edge_irq);
178 		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
179 	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
180 		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
181 		bool rising = trigger & IRQ_TYPE_EDGE_RISING;
182 
183 		/* Disable level detection */
184 		gpiois &= ~bit;
185 		/* Clear detection on both edges */
186 		gpioibe &= ~bit;
187 		/* Select edge */
188 		if (rising)
189 			gpioiev |= bit;
190 		else
191 			gpioiev &= ~bit;
192 		irq_set_handler_locked(d, handle_edge_irq);
193 		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
194 			offset,
195 			rising ? "RISING" : "FALLING");
196 	} else {
197 		/* No trigger: disable everything */
198 		gpiois &= ~bit;
199 		gpioibe &= ~bit;
200 		gpioiev &= ~bit;
201 		irq_set_handler_locked(d, handle_bad_irq);
202 		dev_warn(gc->parent, "no trigger selected for line %d\n",
203 			 offset);
204 	}
205 
206 	writeb(gpiois, pl061->base + GPIOIS);
207 	writeb(gpioibe, pl061->base + GPIOIBE);
208 	writeb(gpioiev, pl061->base + GPIOIEV);
209 
210 	raw_spin_unlock_irqrestore(&pl061->lock, flags);
211 
212 	return 0;
213 }
214 
pl061_irq_handler(struct irq_desc * desc)215 static void pl061_irq_handler(struct irq_desc *desc)
216 {
217 	unsigned long pending;
218 	int offset;
219 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
220 	struct pl061 *pl061 = gpiochip_get_data(gc);
221 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
222 
223 	chained_irq_enter(irqchip, desc);
224 
225 	pending = readb(pl061->base + GPIOMIS);
226 	if (pending) {
227 		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
228 			generic_handle_domain_irq(gc->irq.domain,
229 						  offset);
230 	}
231 
232 	chained_irq_exit(irqchip, desc);
233 }
234 
pl061_irq_mask(struct irq_data * d)235 static void pl061_irq_mask(struct irq_data *d)
236 {
237 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
238 	struct pl061 *pl061 = gpiochip_get_data(gc);
239 	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
240 	u8 gpioie;
241 
242 	raw_spin_lock(&pl061->lock);
243 	gpioie = readb(pl061->base + GPIOIE) & ~mask;
244 	writeb(gpioie, pl061->base + GPIOIE);
245 	raw_spin_unlock(&pl061->lock);
246 
247 	gpiochip_disable_irq(gc, d->hwirq);
248 }
249 
pl061_irq_unmask(struct irq_data * d)250 static void pl061_irq_unmask(struct irq_data *d)
251 {
252 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 	struct pl061 *pl061 = gpiochip_get_data(gc);
254 	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
255 	u8 gpioie;
256 
257 	gpiochip_enable_irq(gc, d->hwirq);
258 
259 	raw_spin_lock(&pl061->lock);
260 	gpioie = readb(pl061->base + GPIOIE) | mask;
261 	writeb(gpioie, pl061->base + GPIOIE);
262 	raw_spin_unlock(&pl061->lock);
263 }
264 
265 /**
266  * pl061_irq_ack() - ACK an edge IRQ
267  * @d: IRQ data for this IRQ
268  *
269  * This gets called from the edge IRQ handler to ACK the edge IRQ
270  * in the GPIOIC (interrupt-clear) register. For level IRQs this is
271  * not needed: these go away when the level signal goes away.
272  */
pl061_irq_ack(struct irq_data * d)273 static void pl061_irq_ack(struct irq_data *d)
274 {
275 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
276 	struct pl061 *pl061 = gpiochip_get_data(gc);
277 	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
278 
279 	raw_spin_lock(&pl061->lock);
280 	writeb(mask, pl061->base + GPIOIC);
281 	raw_spin_unlock(&pl061->lock);
282 }
283 
pl061_irq_set_wake(struct irq_data * d,unsigned int state)284 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
285 {
286 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
287 	struct pl061 *pl061 = gpiochip_get_data(gc);
288 
289 	return irq_set_irq_wake(pl061->parent_irq, state);
290 }
291 
pl061_irq_print_chip(struct irq_data * data,struct seq_file * p)292 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p)
293 {
294 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
295 
296 	seq_puts(p, dev_name(gc->parent));
297 }
298 
299 static const struct irq_chip pl061_irq_chip = {
300 	.irq_ack		= pl061_irq_ack,
301 	.irq_mask		= pl061_irq_mask,
302 	.irq_unmask		= pl061_irq_unmask,
303 	.irq_set_type		= pl061_irq_type,
304 	.irq_set_wake		= pl061_irq_set_wake,
305 	.irq_print_chip		= pl061_irq_print_chip,
306 	.flags			= IRQCHIP_IMMUTABLE,
307 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
308 };
309 
pl061_probe(struct amba_device * adev,const struct amba_id * id)310 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
311 {
312 	struct device *dev = &adev->dev;
313 	struct pl061 *pl061;
314 	struct gpio_irq_chip *girq;
315 	int ret, irq;
316 
317 	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
318 	if (pl061 == NULL)
319 		return -ENOMEM;
320 
321 	pl061->base = devm_ioremap_resource(dev, &adev->res);
322 	if (IS_ERR(pl061->base))
323 		return PTR_ERR(pl061->base);
324 
325 	raw_spin_lock_init(&pl061->lock);
326 	pl061->gc.request = gpiochip_generic_request;
327 	pl061->gc.free = gpiochip_generic_free;
328 	pl061->gc.base = -1;
329 	pl061->gc.get_direction = pl061_get_direction;
330 	pl061->gc.direction_input = pl061_direction_input;
331 	pl061->gc.direction_output = pl061_direction_output;
332 	pl061->gc.get = pl061_get_value;
333 	pl061->gc.set_rv = pl061_set_value;
334 	pl061->gc.ngpio = PL061_GPIO_NR;
335 	pl061->gc.label = dev_name(dev);
336 	pl061->gc.parent = dev;
337 	pl061->gc.owner = THIS_MODULE;
338 
339 	/*
340 	 * irq_chip support
341 	 */
342 	writeb(0, pl061->base + GPIOIE); /* disable irqs */
343 	irq = adev->irq[0];
344 	if (!irq)
345 		dev_warn(&adev->dev, "IRQ support disabled\n");
346 	pl061->parent_irq = irq;
347 
348 	girq = &pl061->gc.irq;
349 	gpio_irq_chip_set_chip(girq, &pl061_irq_chip);
350 	girq->parent_handler = pl061_irq_handler;
351 	girq->num_parents = 1;
352 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
353 				     GFP_KERNEL);
354 	if (!girq->parents)
355 		return -ENOMEM;
356 	girq->parents[0] = irq;
357 	girq->default_type = IRQ_TYPE_NONE;
358 	girq->handler = handle_bad_irq;
359 
360 	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
361 	if (ret)
362 		return ret;
363 
364 	amba_set_drvdata(adev, pl061);
365 	dev_info(dev, "PL061 GPIO chip registered\n");
366 
367 	return 0;
368 }
369 
370 #ifdef CONFIG_PM
pl061_suspend(struct device * dev)371 static int pl061_suspend(struct device *dev)
372 {
373 	struct pl061 *pl061 = dev_get_drvdata(dev);
374 	int offset;
375 
376 	pl061->csave_regs.gpio_data = 0;
377 	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
378 	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
379 	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
380 	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
381 	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
382 
383 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
384 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
385 			pl061->csave_regs.gpio_data |=
386 				pl061_get_value(&pl061->gc, offset) << offset;
387 	}
388 
389 	return 0;
390 }
391 
pl061_resume(struct device * dev)392 static int pl061_resume(struct device *dev)
393 {
394 	struct pl061 *pl061 = dev_get_drvdata(dev);
395 	int offset;
396 
397 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
398 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
399 			pl061_direction_output(&pl061->gc, offset,
400 					pl061->csave_regs.gpio_data &
401 					(BIT(offset)));
402 		else
403 			pl061_direction_input(&pl061->gc, offset);
404 	}
405 
406 	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
407 	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
408 	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
409 	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
410 
411 	return 0;
412 }
413 
414 static const struct dev_pm_ops pl061_dev_pm_ops = {
415 	.suspend = pl061_suspend,
416 	.resume = pl061_resume,
417 	.freeze = pl061_suspend,
418 	.restore = pl061_resume,
419 };
420 #endif
421 
422 static const struct amba_id pl061_ids[] = {
423 	{
424 		.id	= 0x00041061,
425 		.mask	= 0x000fffff,
426 	},
427 	{ 0, 0 },
428 };
429 MODULE_DEVICE_TABLE(amba, pl061_ids);
430 
431 static struct amba_driver pl061_gpio_driver = {
432 	.drv = {
433 		.name	= "pl061_gpio",
434 #ifdef CONFIG_PM
435 		.pm	= &pl061_dev_pm_ops,
436 #endif
437 	},
438 	.id_table	= pl061_ids,
439 	.probe		= pl061_probe,
440 };
441 module_amba_driver(pl061_gpio_driver);
442 
443 MODULE_DESCRIPTION("Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)");
444 MODULE_LICENSE("GPL v2");
445