1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/phy/phy.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/units.h>
17
18 #define BIT_WRITEABLE_SHIFT 16
19 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
20 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
21 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
22
23 /* RK3528 COMBO PHY REG */
24 #define RK3528_PHYREG5 0x14
25 #define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
26 #define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
27 #define RK3528_PHYREG6 0x18
28 #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
29 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
30 #define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4)
31 #define RK3528_PHYREG6_SSC_UPWARD 0
32 #define RK3528_PHYREG6_SSC_DOWNWARD 1
33
34 #define RK3528_PHYREG40 0x100
35 #define RK3528_PHYREG40_SSC_EN BIT(20)
36 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
37 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
38
39 #define RK3528_PHYREG42 0x108
40 #define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29)
41 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0
42 #define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1
43 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7)
44 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9
45 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4)
46 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
47 #define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0)
48 #define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0
49
50 #define RK3528_PHYREG80 0x200
51 #define RK3528_PHYREG80_CTLE_EN BIT(17)
52
53 #define RK3528_PHYREG81 0x204
54 #define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5)
55 #define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0)
56 #define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7
57
58 #define RK3528_PHYREG83 0x20c
59 #define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0)
60 #define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6
61
62 #define RK3528_PHYREG86 0x218
63 #define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14)
64
65 /* RK3568 COMBO PHY REG */
66 #define RK3568_PHYREG6 0x14
67 #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
68 #define RK3568_PHYREG6_PLL_DIV_SHIFT 6
69 #define RK3568_PHYREG6_PLL_DIV_2 1
70
71 #define RK3568_PHYREG7 0x18
72 #define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
73 #define RK3568_PHYREG7_TX_RTERM_SHIFT 4
74 #define RK3568_PHYREG7_TX_RTERM_50OHM 8
75 #define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
76 #define RK3568_PHYREG7_RX_RTERM_SHIFT 0
77 #define RK3568_PHYREG7_RX_RTERM_44OHM 15
78
79 #define RK3568_PHYREG8 0x1C
80 #define RK3568_PHYREG8_SSC_EN BIT(4)
81
82 #define RK3568_PHYREG11 0x28
83 #define RK3568_PHYREG11_SU_TRIM_0_7 0xF0
84
85 #define RK3568_PHYREG12 0x2C
86 #define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4
87
88 #define RK3568_PHYREG13 0x30
89 #define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4)
90 #define RK3568_PHYREG13_RESISTER_SHIFT 0x4
91 #define RK3568_PHYREG13_RESISTER_HIGH_Z 3
92 #define RK3568_PHYREG13_CKRCV_AMP0 BIT(7)
93
94 #define RK3568_PHYREG14 0x34
95 #define RK3568_PHYREG14_CKRCV_AMP1 BIT(0)
96
97 #define RK3568_PHYREG15 0x38
98 #define RK3568_PHYREG15_CTLE_EN BIT(0)
99 #define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
100 #define RK3568_PHYREG15_SSC_CNT_SHIFT 6
101 #define RK3568_PHYREG15_SSC_CNT_VALUE 1
102
103 #define RK3568_PHYREG16 0x3C
104 #define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f
105
106 #define RK3568_PHYREG18 0x44
107 #define RK3568_PHYREG18_PLL_LOOP 0x32
108
109 #define RK3568_PHYREG30 0x74
110 #define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
111 #define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
112
113 #define RK3568_PHYREG32 0x7C
114 #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
115 #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
116 #define RK3568_PHYREG32_SSC_DIR_SHIFT 4
117 #define RK3568_PHYREG32_SSC_UPWARD 0
118 #define RK3568_PHYREG32_SSC_DOWNWARD 1
119 #define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
120 #define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6
121 #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
122
123 #define RK3568_PHYREG33 0x80
124 #define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5)
125 #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
126 #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
127 #define RK3568_PHYREG33_PLL_KVCO_VALUE 2
128 #define RK3576_PHYREG33_PLL_KVCO_VALUE 4
129
130 /* RK3588 COMBO PHY registers */
131 #define RK3588_PHYREG27 0x6C
132 #define RK3588_PHYREG27_RX_TRIM 0x4C
133
134 /* RK3576 COMBO PHY registers */
135 #define RK3576_PHYREG10 0x24
136 #define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
137 #define RK3576_PHYREG10_SSC_PCM_3500PPM 7
138
139 #define RK3576_PHYREG17 0x40
140
141 #define RK3576_PHYREG21 0x50
142 #define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D
143
144 #define RK3576_PHYREG30 0x74
145
146 struct rockchip_combphy_priv;
147
148 struct combphy_reg {
149 u16 offset;
150 u16 bitend;
151 u16 bitstart;
152 u16 disable;
153 u16 enable;
154 };
155
156 struct rockchip_combphy_grfcfg {
157 struct combphy_reg pcie_mode_set;
158 struct combphy_reg usb_mode_set;
159 struct combphy_reg sgmii_mode_set;
160 struct combphy_reg qsgmii_mode_set;
161 struct combphy_reg pipe_rxterm_set;
162 struct combphy_reg pipe_txelec_set;
163 struct combphy_reg pipe_txcomp_set;
164 struct combphy_reg pipe_clk_24m;
165 struct combphy_reg pipe_clk_25m;
166 struct combphy_reg pipe_clk_100m;
167 struct combphy_reg pipe_phymode_sel;
168 struct combphy_reg pipe_rate_sel;
169 struct combphy_reg pipe_rxterm_sel;
170 struct combphy_reg pipe_txelec_sel;
171 struct combphy_reg pipe_txcomp_sel;
172 struct combphy_reg pipe_clk_ext;
173 struct combphy_reg pipe_sel_usb;
174 struct combphy_reg pipe_sel_qsgmii;
175 struct combphy_reg pipe_phy_status;
176 struct combphy_reg con0_for_pcie;
177 struct combphy_reg con1_for_pcie;
178 struct combphy_reg con2_for_pcie;
179 struct combphy_reg con3_for_pcie;
180 struct combphy_reg con0_for_sata;
181 struct combphy_reg con1_for_sata;
182 struct combphy_reg con2_for_sata;
183 struct combphy_reg con3_for_sata;
184 struct combphy_reg pipe_con0_for_sata;
185 struct combphy_reg pipe_con1_for_sata;
186 struct combphy_reg pipe_xpcs_phy_ready;
187 struct combphy_reg pipe_pcie1l0_sel;
188 struct combphy_reg pipe_pcie1l1_sel;
189 struct combphy_reg u3otg0_port_en;
190 struct combphy_reg u3otg1_port_en;
191 };
192
193 struct rockchip_combphy_cfg {
194 unsigned int num_phys;
195 unsigned int phy_ids[3];
196 const struct rockchip_combphy_grfcfg *grfcfg;
197 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
198 };
199
200 struct rockchip_combphy_priv {
201 u8 type;
202 int id;
203 void __iomem *mmio;
204 int num_clks;
205 struct clk_bulk_data *clks;
206 struct device *dev;
207 struct regmap *pipe_grf;
208 struct regmap *phy_grf;
209 struct phy *phy;
210 struct reset_control *phy_rst;
211 const struct rockchip_combphy_cfg *cfg;
212 bool enable_ssc;
213 bool ext_refclk;
214 struct clk *refclk;
215 };
216
rockchip_combphy_updatel(struct rockchip_combphy_priv * priv,int mask,int val,int reg)217 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
218 int mask, int val, int reg)
219 {
220 unsigned int temp;
221
222 temp = readl(priv->mmio + reg);
223 temp = (temp & ~(mask)) | val;
224 writel(temp, priv->mmio + reg);
225 }
226
rockchip_combphy_param_write(struct regmap * base,const struct combphy_reg * reg,bool en)227 static int rockchip_combphy_param_write(struct regmap *base,
228 const struct combphy_reg *reg, bool en)
229 {
230 u32 val, mask, tmp;
231
232 tmp = en ? reg->enable : reg->disable;
233 mask = GENMASK(reg->bitend, reg->bitstart);
234 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
235
236 return regmap_write(base, reg->offset, val);
237 }
238
rockchip_combphy_is_ready(struct rockchip_combphy_priv * priv)239 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
240 {
241 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
242 u32 mask, val;
243
244 mask = GENMASK(cfg->pipe_phy_status.bitend,
245 cfg->pipe_phy_status.bitstart);
246
247 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
248 val = (val & mask) >> cfg->pipe_phy_status.bitstart;
249
250 return val;
251 }
252
rockchip_combphy_init(struct phy * phy)253 static int rockchip_combphy_init(struct phy *phy)
254 {
255 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
256 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
257 u32 val;
258 int ret;
259
260 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
261 if (ret) {
262 dev_err(priv->dev, "failed to enable clks\n");
263 return ret;
264 }
265
266 switch (priv->type) {
267 case PHY_TYPE_PCIE:
268 case PHY_TYPE_USB3:
269 case PHY_TYPE_SATA:
270 case PHY_TYPE_SGMII:
271 case PHY_TYPE_QSGMII:
272 if (priv->cfg->combphy_cfg)
273 ret = priv->cfg->combphy_cfg(priv);
274 break;
275 default:
276 dev_err(priv->dev, "incompatible PHY type\n");
277 ret = -EINVAL;
278 break;
279 }
280
281 if (ret) {
282 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
283 goto err_clk;
284 }
285
286 ret = reset_control_deassert(priv->phy_rst);
287 if (ret)
288 goto err_clk;
289
290 if (priv->type == PHY_TYPE_USB3) {
291 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
292 priv, val,
293 val == cfg->pipe_phy_status.enable,
294 10, 1000);
295 if (ret)
296 dev_warn(priv->dev, "wait phy status ready timeout\n");
297 }
298
299 return 0;
300
301 err_clk:
302 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
303
304 return ret;
305 }
306
rockchip_combphy_exit(struct phy * phy)307 static int rockchip_combphy_exit(struct phy *phy)
308 {
309 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
310
311 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
312 reset_control_assert(priv->phy_rst);
313
314 return 0;
315 }
316
317 static const struct phy_ops rockchip_combphy_ops = {
318 .init = rockchip_combphy_init,
319 .exit = rockchip_combphy_exit,
320 .owner = THIS_MODULE,
321 };
322
rockchip_combphy_xlate(struct device * dev,const struct of_phandle_args * args)323 static struct phy *rockchip_combphy_xlate(struct device *dev, const struct of_phandle_args *args)
324 {
325 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
326
327 if (args->args_count != 1) {
328 dev_err(dev, "invalid number of arguments\n");
329 return ERR_PTR(-EINVAL);
330 }
331
332 if (priv->type != PHY_NONE && priv->type != args->args[0])
333 dev_warn(dev, "phy type select %d overwriting type %d\n",
334 args->args[0], priv->type);
335
336 priv->type = args->args[0];
337
338 return priv->phy;
339 }
340
rockchip_combphy_parse_dt(struct device * dev,struct rockchip_combphy_priv * priv)341 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
342 {
343 int i;
344
345 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
346 if (priv->num_clks < 1)
347 return -EINVAL;
348
349 priv->refclk = NULL;
350 for (i = 0; i < priv->num_clks; i++) {
351 if (!strncmp(priv->clks[i].id, "ref", 3)) {
352 priv->refclk = priv->clks[i].clk;
353 break;
354 }
355 }
356
357 if (!priv->refclk) {
358 dev_err(dev, "no refclk found\n");
359 return -EINVAL;
360 }
361
362 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
363 if (IS_ERR(priv->pipe_grf)) {
364 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
365 return PTR_ERR(priv->pipe_grf);
366 }
367
368 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
369 if (IS_ERR(priv->phy_grf)) {
370 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
371 return PTR_ERR(priv->phy_grf);
372 }
373
374 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
375
376 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
377
378 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy");
379 /* fallback to old behaviour */
380 if (PTR_ERR(priv->phy_rst) == -ENOENT)
381 priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
382 if (IS_ERR(priv->phy_rst))
383 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
384
385 return 0;
386 }
387
rockchip_combphy_probe(struct platform_device * pdev)388 static int rockchip_combphy_probe(struct platform_device *pdev)
389 {
390 struct phy_provider *phy_provider;
391 struct device *dev = &pdev->dev;
392 struct rockchip_combphy_priv *priv;
393 const struct rockchip_combphy_cfg *phy_cfg;
394 struct resource *res;
395 int ret, id;
396
397 phy_cfg = of_device_get_match_data(dev);
398 if (!phy_cfg) {
399 dev_err(dev, "no OF match data provided\n");
400 return -EINVAL;
401 }
402
403 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
404 if (!priv)
405 return -ENOMEM;
406
407 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
408 if (IS_ERR(priv->mmio)) {
409 ret = PTR_ERR(priv->mmio);
410 return ret;
411 }
412
413 /* find the phy-id from the io address */
414 priv->id = -ENODEV;
415 for (id = 0; id < phy_cfg->num_phys; id++) {
416 if (res->start == phy_cfg->phy_ids[id]) {
417 priv->id = id;
418 break;
419 }
420 }
421
422 priv->dev = dev;
423 priv->type = PHY_NONE;
424 priv->cfg = phy_cfg;
425
426 ret = rockchip_combphy_parse_dt(dev, priv);
427 if (ret)
428 return ret;
429
430 ret = reset_control_assert(priv->phy_rst);
431 if (ret) {
432 dev_err(dev, "failed to reset phy\n");
433 return ret;
434 }
435
436 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
437 if (IS_ERR(priv->phy)) {
438 dev_err(dev, "failed to create combphy\n");
439 return PTR_ERR(priv->phy);
440 }
441
442 dev_set_drvdata(dev, priv);
443 phy_set_drvdata(priv->phy, priv);
444
445 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
446
447 return PTR_ERR_OR_ZERO(phy_provider);
448 }
449
rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv * priv,unsigned long rate)450 static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsigned long rate)
451 {
452 struct device_node *np = priv->dev->of_node;
453 u32 val;
454
455 /* Set SSC downward spread spectrum for PCIe and USB3 */
456 if (priv->type == PHY_TYPE_PCIE || priv->type == PHY_TYPE_USB3) {
457 val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
458 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
459 }
460
461 /* Set SSC downward spread spectrum +500ppm for SATA in 100MHz */
462 if (priv->type == PHY_TYPE_SATA && rate == REF_CLOCK_100MHz) {
463 val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
464 RK3568_PHYREG32_SSC_DOWNWARD);
465 val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
466 RK3568_PHYREG32_SSC_OFFSET_500PPM);
467 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
468 RK3568_PHYREG32);
469 }
470
471 if (!priv->enable_ssc)
472 return;
473
474 /* Enable SSC */
475 val = readl(priv->mmio + RK3568_PHYREG8);
476 val |= RK3568_PHYREG8_SSC_EN;
477 writel(val, priv->mmio + RK3568_PHYREG8);
478
479 /* Some SoCs need tuning PCIe SSC instead of default configuration in 24MHz */
480 if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") &&
481 !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy"))
482 return;
483
484 /* PLL control SSC module period should be set if need tuning */
485 val = readl(priv->mmio + RK3568_PHYREG33);
486 val |= RK3568_PHYREG33_PLL_SSC_CTRL;
487 writel(val, priv->mmio + RK3568_PHYREG33);
488
489 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
490 /* Set PLL loop divider */
491 writel(0x00, priv->mmio + RK3576_PHYREG17);
492 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
493
494 /* Set up rx_pck invert and rx msb to disable */
495 writel(0x00, priv->mmio + RK3588_PHYREG27);
496
497 /*
498 * Set up SU adjust signal:
499 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
500 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
501 * su_trim[23:16], CKRCV adjust
502 * su_trim[31:24], CKDRV adjust
503 */
504 writel(0x90, priv->mmio + RK3568_PHYREG11);
505 writel(0x02, priv->mmio + RK3568_PHYREG12);
506 writel(0x08, priv->mmio + RK3568_PHYREG13);
507 writel(0x57, priv->mmio + RK3568_PHYREG14);
508 writel(0x40, priv->mmio + RK3568_PHYREG15);
509
510 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
511
512 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
513 RK3576_PHYREG33_PLL_KVCO_VALUE);
514 writel(val, priv->mmio + RK3568_PHYREG33);
515 }
516 }
517
rk3528_combphy_cfg(struct rockchip_combphy_priv * priv)518 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
519 {
520 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
521 unsigned long rate;
522 u32 val;
523
524 /* Set SSC downward spread spectrum */
525 val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD);
526 rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6);
527
528 switch (priv->type) {
529 case PHY_TYPE_PCIE:
530 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
531 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
532 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
533 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
534 break;
535 case PHY_TYPE_USB3:
536 /* Enable adaptive CTLE for USB3.0 Rx */
537 rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN,
538 RK3528_PHYREG80);
539
540 /* Set slow slew rate control for PI */
541 val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL,
542 RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW);
543 rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val,
544 RK3528_PHYREG81);
545
546 /* Set CDR phase path with 2x gain */
547 rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X,
548 RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81);
549
550 /* Set Rx squelch input filler bandwidth */
551 val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE);
552 rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83);
553
554 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
555 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
556 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
557 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
558 break;
559 default:
560 dev_err(priv->dev, "incompatible PHY type\n");
561 return -EINVAL;
562 }
563
564 rate = clk_get_rate(priv->refclk);
565
566 switch (rate) {
567 case REF_CLOCK_24MHz:
568 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
569 if (priv->type == PHY_TYPE_USB3) {
570 /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
571 val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE);
572 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val,
573 RK3528_PHYREG40);
574 } else if (priv->type == PHY_TYPE_PCIE) {
575 /* tx_trim[14]=1, Enable the counting clock of the rterm detect */
576 rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN,
577 RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86);
578 }
579 break;
580 case REF_CLOCK_100MHz:
581 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
582 if (priv->type == PHY_TYPE_PCIE) {
583 /* Gate_tx_pck_sel length select for L1ss support */
584 rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
585 RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
586
587 /* PLL KVCO tuning fine */
588 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
589 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
590 RK3528_PHYREG6);
591
592 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
593 writel(0x570804f0, priv->mmio + RK3528_PHYREG42);
594 }
595 break;
596 default:
597 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
598 return -EINVAL;
599 }
600
601 if (priv->ext_refclk) {
602 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
603
604 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
605 val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL,
606 RK3528_PHYREG42_CKDRV_CLK_CKRCV);
607 val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ,
608 RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE);
609 val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ,
610 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE);
611 val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ,
612 RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE);
613 rockchip_combphy_updatel(priv,
614 RK3528_PHYREG42_CKDRV_CLK_SEL |
615 RK3528_PHYREG42_PLL_LPF_R1_ADJ |
616 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ |
617 RK3528_PHYREG42_PLL_KVCO_ADJ,
618 val, RK3528_PHYREG42);
619
620 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
621 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
622 RK3528_PHYREG6);
623 }
624 }
625
626 if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
627 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
628 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
629
630 return 0;
631 }
632
633 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
634 /* pipe-phy-grf */
635 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
636 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
637 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
638 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
639 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
640 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
641 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
642 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
643 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
644 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
645 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
646 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
647 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
648 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
649 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
650 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
651 /* pipe-grf */
652 .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
653 };
654
655 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
656 .num_phys = 1,
657 .phy_ids = {
658 0xffdc0000,
659 },
660 .grfcfg = &rk3528_combphy_grfcfgs,
661 .combphy_cfg = rk3528_combphy_cfg,
662 };
663
rk3562_combphy_cfg(struct rockchip_combphy_priv * priv)664 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
665 {
666 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
667 unsigned long rate;
668 u32 val;
669
670 switch (priv->type) {
671 case PHY_TYPE_PCIE:
672 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
673 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
674 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
675 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
676 break;
677 case PHY_TYPE_USB3:
678 /* Enable adaptive CTLE for USB3.0 Rx */
679 rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
680 RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
681
682 /* Set PLL KVCO fine tuning signals */
683 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
684 BIT(3), RK3568_PHYREG33);
685
686 /* Set PLL LPF R1 to su_trim[10:7]=1001 */
687 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
688
689 /* Set PLL input clock divider 1/2 */
690 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
691 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
692
693 /* Set PLL loop divider */
694 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
695
696 /* Set PLL KVCO to min and set PLL charge pump current to max */
697 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
698
699 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
700 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
701 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
702 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
703 break;
704 default:
705 dev_err(priv->dev, "incompatible PHY type\n");
706 return -EINVAL;
707 }
708
709 rate = clk_get_rate(priv->refclk);
710
711 switch (rate) {
712 case REF_CLOCK_24MHz:
713 if (priv->type == PHY_TYPE_USB3) {
714 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
715 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
716 RK3568_PHYREG15_SSC_CNT_VALUE);
717 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
718 val, RK3568_PHYREG15);
719
720 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
721 }
722 break;
723 case REF_CLOCK_25MHz:
724 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
725 break;
726 case REF_CLOCK_100MHz:
727 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
728 if (priv->type == PHY_TYPE_PCIE) {
729 /* Gate_tx_pck_sel length select for L1ss support */
730 rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
731 RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
732 RK3568_PHYREG30);
733 /* PLL KVCO tuning fine */
734 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
735 RK3568_PHYREG33_PLL_KVCO_VALUE);
736 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
737 val, RK3568_PHYREG33);
738
739 /* Enable controlling random jitter, aka RMJ */
740 writel(0x4, priv->mmio + RK3568_PHYREG12);
741
742 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
743 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
744 val, RK3568_PHYREG6);
745
746 writel(0x32, priv->mmio + RK3568_PHYREG18);
747 writel(0xf0, priv->mmio + RK3568_PHYREG11);
748 }
749 break;
750 default:
751 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
752 return -EINVAL;
753 }
754
755 if (priv->ext_refclk) {
756 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
757 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
758 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
759 val |= RK3568_PHYREG13_CKRCV_AMP0;
760 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
761 RK3568_PHYREG13);
762
763 val = readl(priv->mmio + RK3568_PHYREG14);
764 val |= RK3568_PHYREG14_CKRCV_AMP1;
765 writel(val, priv->mmio + RK3568_PHYREG14);
766 }
767 }
768
769 rk_combphy_common_cfg_ssc(priv, rate);
770
771 return 0;
772 }
773
774 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
775 /* pipe-phy-grf */
776 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
777 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
778 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
779 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
780 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
781 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
782 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
783 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
784 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
785 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
786 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
787 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
788 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
789 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
790 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
791 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
792 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
793 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
794 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
795 };
796
797 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
798 .num_phys = 1,
799 .phy_ids = {
800 0xff750000
801 },
802 .grfcfg = &rk3562_combphy_grfcfgs,
803 .combphy_cfg = rk3562_combphy_cfg,
804 };
805
rk3568_combphy_cfg(struct rockchip_combphy_priv * priv)806 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
807 {
808 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
809 unsigned long rate;
810 u32 val;
811
812 switch (priv->type) {
813 case PHY_TYPE_PCIE:
814 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
815 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
816 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
817 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
818 break;
819
820 case PHY_TYPE_USB3:
821 /* Enable adaptive CTLE for USB3.0 Rx. */
822 val = readl(priv->mmio + RK3568_PHYREG15);
823 val |= RK3568_PHYREG15_CTLE_EN;
824 writel(val, priv->mmio + RK3568_PHYREG15);
825
826 /* Set PLL KVCO fine tuning signals. */
827 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
828 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
829
830 /* Enable controlling random jitter. */
831 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
832
833 /* Set PLL input clock divider 1/2. */
834 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
835 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
836 RK3568_PHYREG6);
837
838 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
839 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
840
841 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
842 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
843 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
844 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
845 switch (priv->id) {
846 case 0:
847 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
848 break;
849 case 1:
850 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
851 break;
852 }
853 break;
854
855 case PHY_TYPE_SATA:
856 /* Enable adaptive CTLE for SATA Rx. */
857 val = readl(priv->mmio + RK3568_PHYREG15);
858 val |= RK3568_PHYREG15_CTLE_EN;
859 writel(val, priv->mmio + RK3568_PHYREG15);
860 /*
861 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
862 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
863 */
864 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
865 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
866 writel(val, priv->mmio + RK3568_PHYREG7);
867
868 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
869 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
870 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
871 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
872 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
873 break;
874
875 case PHY_TYPE_SGMII:
876 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
877 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
878 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
879 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
880 break;
881
882 case PHY_TYPE_QSGMII:
883 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
884 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
885 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
886 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
887 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
888 break;
889
890 default:
891 dev_err(priv->dev, "incompatible PHY type\n");
892 return -EINVAL;
893 }
894
895 rate = clk_get_rate(priv->refclk);
896
897 switch (rate) {
898 case REF_CLOCK_24MHz:
899 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
900 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
901 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
902 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
903 val, RK3568_PHYREG15);
904
905 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
906 }
907 break;
908
909 case REF_CLOCK_25MHz:
910 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
911 break;
912
913 case REF_CLOCK_100MHz:
914 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
915 if (priv->type == PHY_TYPE_PCIE) {
916 /* PLL KVCO fine tuning. */
917 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
918 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
919 val, RK3568_PHYREG33);
920
921 /* Enable controlling random jitter. */
922 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
923
924 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
925 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
926 val, RK3568_PHYREG6);
927
928 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
929 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
930 }
931 break;
932
933 default:
934 dev_err(priv->dev, "unsupported rate: %lu\n", rate);
935 return -EINVAL;
936 }
937
938 if (priv->ext_refclk) {
939 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
940 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
941 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
942 val |= RK3568_PHYREG13_CKRCV_AMP0;
943 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
944 RK3568_PHYREG13);
945
946 val = readl(priv->mmio + RK3568_PHYREG14);
947 val |= RK3568_PHYREG14_CKRCV_AMP1;
948 writel(val, priv->mmio + RK3568_PHYREG14);
949 }
950 }
951
952 rk_combphy_common_cfg_ssc(priv, rate);
953
954 return 0;
955 }
956
957 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
958 /* pipe-phy-grf */
959 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
960 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
961 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
962 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
963 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
964 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
965 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
966 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
967 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
968 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
969 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
970 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
971 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
972 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
973 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
974 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
975 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
976 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
977 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
978 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
979 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
980 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
981 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
982 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
983 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
984 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
985 /* pipe-grf */
986 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
987 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
988 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
989 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
990 };
991
992 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
993 .num_phys = 3,
994 .phy_ids = {
995 0xfe820000,
996 0xfe830000,
997 0xfe840000,
998 },
999 .grfcfg = &rk3568_combphy_grfcfgs,
1000 .combphy_cfg = rk3568_combphy_cfg,
1001 };
1002
rk3576_combphy_cfg(struct rockchip_combphy_priv * priv)1003 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
1004 {
1005 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
1006 unsigned long rate;
1007 u32 val;
1008
1009 switch (priv->type) {
1010 case PHY_TYPE_PCIE:
1011 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
1012 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
1013 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
1014 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
1015 break;
1016
1017 case PHY_TYPE_USB3:
1018 /* Enable adaptive CTLE for USB3.0 Rx */
1019 val = readl(priv->mmio + RK3568_PHYREG15);
1020 val |= RK3568_PHYREG15_CTLE_EN;
1021 writel(val, priv->mmio + RK3568_PHYREG15);
1022
1023 /* Set PLL KVCO fine tuning signals */
1024 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),
1025 RK3568_PHYREG33);
1026
1027 /* Set PLL LPF R1 to su_trim[10:7]=1001 */
1028 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
1029
1030 /* Set PLL input clock divider 1/2 */
1031 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
1032 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
1033
1034 /* Set PLL loop divider */
1035 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
1036
1037 /* Set PLL KVCO to min and set PLL charge pump current to max */
1038 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
1039
1040 /* Set Rx squelch input filler bandwidth */
1041 writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
1042
1043 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
1044 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
1045 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
1046 break;
1047
1048 case PHY_TYPE_SATA:
1049 /* Enable adaptive CTLE for SATA Rx */
1050 val = readl(priv->mmio + RK3568_PHYREG15);
1051 val |= RK3568_PHYREG15_CTLE_EN;
1052 writel(val, priv->mmio + RK3568_PHYREG15);
1053
1054 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
1055 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
1056 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
1057 writel(val, priv->mmio + RK3568_PHYREG7);
1058
1059 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
1060 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
1061 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
1062 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
1063 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
1064 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
1065 break;
1066
1067 default:
1068 dev_err(priv->dev, "incompatible PHY type\n");
1069 return -EINVAL;
1070 }
1071
1072 rate = clk_get_rate(priv->refclk);
1073
1074 switch (rate) {
1075 case REF_CLOCK_24MHz:
1076 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
1077 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
1078 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
1079 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
1080 RK3568_PHYREG15_SSC_CNT_VALUE);
1081 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
1082 val, RK3568_PHYREG15);
1083
1084 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
1085 } else if (priv->type == PHY_TYPE_PCIE) {
1086 /* PLL KVCO tuning fine */
1087 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
1088 RK3576_PHYREG33_PLL_KVCO_VALUE);
1089 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
1090 val, RK3568_PHYREG33);
1091
1092 /* Set up rx_pck invert and rx msb to disable */
1093 writel(0x00, priv->mmio + RK3588_PHYREG27);
1094
1095 /*
1096 * Set up SU adjust signal:
1097 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
1098 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011
1099 * su_trim[31:24], CKDRV adjust
1100 */
1101 writel(0x90, priv->mmio + RK3568_PHYREG11);
1102 writel(0x02, priv->mmio + RK3568_PHYREG12);
1103 writel(0x57, priv->mmio + RK3568_PHYREG14);
1104
1105 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
1106 }
1107 break;
1108
1109 case REF_CLOCK_25MHz:
1110 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
1111 break;
1112
1113 case REF_CLOCK_100MHz:
1114 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
1115 if (priv->type == PHY_TYPE_PCIE) {
1116 /* gate_tx_pck_sel length select work for L1SS */
1117 writel(0xc0, priv->mmio + RK3576_PHYREG30);
1118
1119 /* PLL KVCO tuning fine */
1120 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
1121 RK3576_PHYREG33_PLL_KVCO_VALUE);
1122 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
1123 val, RK3568_PHYREG33);
1124
1125 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
1126 writel(0x4c, priv->mmio + RK3588_PHYREG27);
1127
1128 /*
1129 * Set up SU adjust signal:
1130 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
1131 * su_trim[15:8], bypass PLL loop divider code, and
1132 * PLL LPF R1 adujst bits[9:7]=3'b101
1133 * su_trim[23:16], CKRCV adjust
1134 * su_trim[31:24], CKDRV adjust
1135 */
1136 writel(0x90, priv->mmio + RK3568_PHYREG11);
1137 writel(0x43, priv->mmio + RK3568_PHYREG12);
1138 writel(0x88, priv->mmio + RK3568_PHYREG13);
1139 writel(0x56, priv->mmio + RK3568_PHYREG14);
1140 } else if (priv->type == PHY_TYPE_SATA) {
1141 /* ssc ppm adjust to 3500ppm */
1142 rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
1143 RK3576_PHYREG10_SSC_PCM_3500PPM,
1144 RK3576_PHYREG10);
1145 }
1146 break;
1147
1148 default:
1149 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
1150 return -EINVAL;
1151 }
1152
1153 if (priv->ext_refclk) {
1154 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
1155 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
1156 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
1157 RK3576_PHYREG33_PLL_KVCO_VALUE);
1158 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
1159 val, RK3568_PHYREG33);
1160
1161 /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
1162 writel(0x0c, priv->mmio + RK3588_PHYREG27);
1163
1164 /*
1165 * Set up SU adjust signal:
1166 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
1167 * su_trim[15:8], bypass PLL loop divider code, and
1168 * PLL LPF R1 adujst bits[9:7]=3'b101.
1169 * su_trim[23:16], CKRCV adjust
1170 * su_trim[31:24], CKDRV adjust
1171 */
1172 writel(0x90, priv->mmio + RK3568_PHYREG11);
1173 writel(0x43, priv->mmio + RK3568_PHYREG12);
1174 writel(0x88, priv->mmio + RK3568_PHYREG13);
1175 writel(0x56, priv->mmio + RK3568_PHYREG14);
1176 }
1177 }
1178
1179 rk_combphy_common_cfg_ssc(priv, rate);
1180
1181 return 0;
1182 }
1183
1184 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
1185 /* pipe-phy-grf */
1186 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1187 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1188 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1189 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1190 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1191 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
1192 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1193 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1194 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
1195 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
1196 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1197 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1198 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1199 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1200 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1201 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1202 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1203 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1204 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1205 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1206 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1207 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1208 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1209 /* php-grf */
1210 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
1211 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
1212 };
1213
1214 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
1215 .num_phys = 2,
1216 .phy_ids = {
1217 0x2b050000,
1218 0x2b060000
1219 },
1220 .grfcfg = &rk3576_combphy_grfcfgs,
1221 .combphy_cfg = rk3576_combphy_cfg,
1222 };
1223
rk3588_combphy_cfg(struct rockchip_combphy_priv * priv)1224 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
1225 {
1226 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
1227 unsigned long rate;
1228 u32 val;
1229
1230 switch (priv->type) {
1231 case PHY_TYPE_PCIE:
1232 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
1233 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
1234 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
1235 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
1236 switch (priv->id) {
1237 case 1:
1238 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
1239 break;
1240 case 2:
1241 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
1242 break;
1243 }
1244 break;
1245 case PHY_TYPE_USB3:
1246 /* Enable adaptive CTLE for USB3.0 Rx. */
1247 val = readl(priv->mmio + RK3568_PHYREG15);
1248 val |= RK3568_PHYREG15_CTLE_EN;
1249 writel(val, priv->mmio + RK3568_PHYREG15);
1250
1251 /* Set PLL KVCO fine tuning signals. */
1252 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
1253 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
1254
1255 /* Enable controlling random jitter. */
1256 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
1257
1258 /* Set PLL input clock divider 1/2. */
1259 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
1260 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
1261 RK3568_PHYREG6);
1262
1263 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
1264 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
1265
1266 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
1267 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
1268 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
1269 break;
1270 case PHY_TYPE_SATA:
1271 /* Enable adaptive CTLE for SATA Rx. */
1272 val = readl(priv->mmio + RK3568_PHYREG15);
1273 val |= RK3568_PHYREG15_CTLE_EN;
1274 writel(val, priv->mmio + RK3568_PHYREG15);
1275 /*
1276 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
1277 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
1278 */
1279 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
1280 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
1281 writel(val, priv->mmio + RK3568_PHYREG7);
1282
1283 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
1284 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
1285 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
1286 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
1287 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
1288 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
1289 break;
1290 case PHY_TYPE_SGMII:
1291 case PHY_TYPE_QSGMII:
1292 default:
1293 dev_err(priv->dev, "incompatible PHY type\n");
1294 return -EINVAL;
1295 }
1296
1297 rate = clk_get_rate(priv->refclk);
1298
1299 switch (rate) {
1300 case REF_CLOCK_24MHz:
1301 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
1302 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
1303 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
1304 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
1305 val, RK3568_PHYREG15);
1306
1307 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
1308 }
1309 break;
1310
1311 case REF_CLOCK_25MHz:
1312 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
1313 break;
1314 case REF_CLOCK_100MHz:
1315 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
1316 if (priv->type == PHY_TYPE_PCIE) {
1317 /* PLL KVCO fine tuning. */
1318 val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT;
1319 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
1320 val, RK3568_PHYREG33);
1321
1322 /* Enable controlling random jitter. */
1323 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
1324
1325 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
1326 writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
1327
1328 /* Set up su_trim: */
1329 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
1330 }
1331 break;
1332 default:
1333 dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
1334 return -EINVAL;
1335 }
1336
1337 if (priv->ext_refclk) {
1338 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
1339 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
1340 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
1341 val |= RK3568_PHYREG13_CKRCV_AMP0;
1342 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
1343 RK3568_PHYREG13);
1344
1345 val = readl(priv->mmio + RK3568_PHYREG14);
1346 val |= RK3568_PHYREG14_CKRCV_AMP1;
1347 writel(val, priv->mmio + RK3568_PHYREG14);
1348 }
1349 }
1350
1351 rk_combphy_common_cfg_ssc(priv, rate);
1352
1353 return 0;
1354 }
1355
1356 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
1357 /* pipe-phy-grf */
1358 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1359 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1360 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1361 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1362 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1363 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1364 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1365 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1366 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1367 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1368 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1369 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1370 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1371 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1372 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1373 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1374 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1375 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1376 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1377 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1378 /* pipe-grf */
1379 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
1380 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
1381 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
1382 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
1383 };
1384
1385 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
1386 .num_phys = 3,
1387 .phy_ids = {
1388 0xfee00000,
1389 0xfee10000,
1390 0xfee20000,
1391 },
1392 .grfcfg = &rk3588_combphy_grfcfgs,
1393 .combphy_cfg = rk3588_combphy_cfg,
1394 };
1395
1396 static const struct of_device_id rockchip_combphy_of_match[] = {
1397 {
1398 .compatible = "rockchip,rk3528-naneng-combphy",
1399 .data = &rk3528_combphy_cfgs,
1400 },
1401 {
1402 .compatible = "rockchip,rk3562-naneng-combphy",
1403 .data = &rk3562_combphy_cfgs,
1404 },
1405 {
1406 .compatible = "rockchip,rk3568-naneng-combphy",
1407 .data = &rk3568_combphy_cfgs,
1408 },
1409 {
1410 .compatible = "rockchip,rk3576-naneng-combphy",
1411 .data = &rk3576_combphy_cfgs,
1412 },
1413 {
1414 .compatible = "rockchip,rk3588-naneng-combphy",
1415 .data = &rk3588_combphy_cfgs,
1416 },
1417 { },
1418 };
1419 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
1420
1421 static struct platform_driver rockchip_combphy_driver = {
1422 .probe = rockchip_combphy_probe,
1423 .driver = {
1424 .name = "rockchip-naneng-combphy",
1425 .of_match_table = rockchip_combphy_of_match,
1426 },
1427 };
1428 module_platform_driver(rockchip_combphy_driver);
1429
1430 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
1431 MODULE_LICENSE("GPL v2");
1432