1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD9832 SPI DDS driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/dev_printk.h>
13 #include <linux/err.h>
14 #include <linux/kstrtox.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spi/spi.h>
19 #include <linux/sysfs.h>
20 #include <linux/types.h>
21 #include <linux/unaligned.h>
22
23 #include <asm/byteorder.h>
24 #include <asm/div64.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
28
29 #include "dds.h"
30
31 /* Registers */
32 #define AD9832_FREQ0LL 0x0
33 #define AD9832_FREQ0HL 0x1
34 #define AD9832_FREQ0LM 0x2
35 #define AD9832_FREQ0HM 0x3
36 #define AD9832_FREQ1LL 0x4
37 #define AD9832_FREQ1HL 0x5
38 #define AD9832_FREQ1LM 0x6
39 #define AD9832_FREQ1HM 0x7
40 #define AD9832_PHASE0L 0x8
41 #define AD9832_PHASE0H 0x9
42 #define AD9832_PHASE1L 0xA
43 #define AD9832_PHASE1H 0xB
44 #define AD9832_PHASE2L 0xC
45 #define AD9832_PHASE2H 0xD
46 #define AD9832_PHASE3L 0xE
47 #define AD9832_PHASE3H 0xF
48 #define AD9832_PHASE_SYM 0x10
49 #define AD9832_FREQ_SYM 0x11
50 #define AD9832_PINCTRL_EN 0x12
51 #define AD9832_OUTPUT_EN 0x13
52
53 /* Command Control Bits */
54 #define AD9832_CMD_PHA8BITSW 0x1
55 #define AD9832_CMD_PHA16BITSW 0x0
56 #define AD9832_CMD_FRE8BITSW 0x3
57 #define AD9832_CMD_FRE16BITSW 0x2
58 #define AD9832_CMD_FPSELECT 0x6
59 #define AD9832_CMD_SYNCSELSRC 0x8
60 #define AD9832_CMD_SLEEPRESCLR 0xC
61
62 #define AD9832_FREQ BIT(11)
63 #define AD9832_PHASE_MASK GENMASK(10, 9)
64 #define AD9832_SYNC BIT(13)
65 #define AD9832_SELSRC BIT(12)
66 #define AD9832_SLEEP BIT(13)
67 #define AD9832_RESET BIT(12)
68 #define AD9832_CLR BIT(11)
69 #define AD9832_FREQ_BITS 32
70 #define AD9832_PHASE_BITS 12
71 #define AD9832_CMD_MSK GENMASK(15, 12)
72 #define AD9832_ADD_MSK GENMASK(11, 8)
73 #define AD9832_DAT_MSK GENMASK(7, 0)
74
75 /**
76 * struct ad9832_state - driver instance specific data
77 * @spi: spi_device
78 * @mclk: external master clock
79 * @ctrl_fp: cached frequency/phase control word
80 * @ctrl_ss: cached sync/selsrc control word
81 * @ctrl_src: cached sleep/reset/clr word
82 * @xfer: default spi transfer
83 * @msg: default spi message
84 * @freq_xfer: tuning word spi transfer
85 * @freq_msg: tuning word spi message
86 * @phase_xfer: tuning word spi transfer
87 * @phase_msg: tuning word spi message
88 * @lock: protect sensor state
89 * @data: spi transmit buffer
90 * @phase_data: tuning word spi transmit buffer
91 * @freq_data: tuning word spi transmit buffer
92 */
93 struct ad9832_state {
94 struct spi_device *spi;
95 struct clk *mclk;
96 unsigned short ctrl_fp;
97 unsigned short ctrl_ss;
98 unsigned short ctrl_src;
99 struct spi_transfer xfer;
100 struct spi_message msg;
101 struct spi_transfer freq_xfer[4];
102 struct spi_message freq_msg;
103 struct spi_transfer phase_xfer[2];
104 struct spi_message phase_msg;
105 struct mutex lock; /* protect sensor state */
106 /*
107 * DMA (thus cache coherency maintenance) requires the
108 * transfer buffers to live in their own cache lines.
109 */
110 union {
111 __be16 freq_data[4];
112 __be16 phase_data[2];
113 __be16 data;
114 } __aligned(IIO_DMA_MINALIGN);
115 };
116
ad9832_calc_freqreg(unsigned long mclk,unsigned long fout)117 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
118 {
119 u64 freqreg = (u64)fout << AD9832_FREQ_BITS;
120
121 do_div(freqreg, mclk);
122 return freqreg;
123 }
124
ad9832_write_frequency(struct ad9832_state * st,unsigned int addr,unsigned long fout)125 static int ad9832_write_frequency(struct ad9832_state *st,
126 unsigned int addr, unsigned long fout)
127 {
128 unsigned long clk_freq;
129 unsigned long regval;
130 u8 regval_bytes[4];
131 u16 freq_cmd;
132
133 clk_freq = clk_get_rate(st->mclk);
134
135 if (!clk_freq || fout > (clk_freq / 2))
136 return -EINVAL;
137
138 regval = ad9832_calc_freqreg(clk_freq, fout);
139 put_unaligned_be32(regval, regval_bytes);
140
141 for (int i = 0; i < ARRAY_SIZE(regval_bytes); i++) {
142 freq_cmd = (i % 2 == 0) ? AD9832_CMD_FRE8BITSW : AD9832_CMD_FRE16BITSW;
143
144 st->freq_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, freq_cmd) |
145 FIELD_PREP(AD9832_ADD_MSK, addr - i) |
146 FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i]));
147 }
148
149 return spi_sync(st->spi, &st->freq_msg);
150 }
151
ad9832_write_phase(struct ad9832_state * st,unsigned long addr,unsigned long phase)152 static int ad9832_write_phase(struct ad9832_state *st,
153 unsigned long addr, unsigned long phase)
154 {
155 u8 phase_bytes[2];
156 u16 phase_cmd;
157
158 if (phase >= BIT(AD9832_PHASE_BITS))
159 return -EINVAL;
160
161 put_unaligned_be16(phase, phase_bytes);
162
163 for (int i = 0; i < ARRAY_SIZE(phase_bytes); i++) {
164 phase_cmd = (i % 2 == 0) ? AD9832_CMD_PHA8BITSW : AD9832_CMD_PHA16BITSW;
165
166 st->phase_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, phase_cmd) |
167 FIELD_PREP(AD9832_ADD_MSK, addr - i) |
168 FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i]));
169 }
170
171 return spi_sync(st->spi, &st->phase_msg);
172 }
173
ad9832_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)174 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
175 const char *buf, size_t len)
176 {
177 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
178 struct ad9832_state *st = iio_priv(indio_dev);
179 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
180 int ret;
181 unsigned long val;
182
183 ret = kstrtoul(buf, 10, &val);
184 if (ret)
185 goto error_ret;
186
187 mutex_lock(&st->lock);
188 switch ((u32)this_attr->address) {
189 case AD9832_FREQ0HM:
190 case AD9832_FREQ1HM:
191 ret = ad9832_write_frequency(st, this_attr->address, val);
192 break;
193 case AD9832_PHASE0H:
194 case AD9832_PHASE1H:
195 case AD9832_PHASE2H:
196 case AD9832_PHASE3H:
197 ret = ad9832_write_phase(st, this_attr->address, val);
198 break;
199 case AD9832_PINCTRL_EN:
200 st->ctrl_ss &= ~AD9832_SELSRC;
201 st->ctrl_ss |= FIELD_PREP(AD9832_SELSRC, val ? 0 : 1);
202
203 st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSRC) |
204 st->ctrl_ss);
205 ret = spi_sync(st->spi, &st->msg);
206 break;
207 case AD9832_FREQ_SYM:
208 if (val == 1 || val == 0) {
209 st->ctrl_fp &= ~AD9832_FREQ;
210 st->ctrl_fp |= FIELD_PREP(AD9832_FREQ, val ? 1 : 0);
211 } else {
212 ret = -EINVAL;
213 break;
214 }
215 st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
216 st->ctrl_fp);
217 ret = spi_sync(st->spi, &st->msg);
218 break;
219 case AD9832_PHASE_SYM:
220 if (val > 3) {
221 ret = -EINVAL;
222 break;
223 }
224
225 st->ctrl_fp &= ~AD9832_PHASE_MASK;
226 st->ctrl_fp |= FIELD_PREP(AD9832_PHASE_MASK, val);
227
228 st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
229 st->ctrl_fp);
230 ret = spi_sync(st->spi, &st->msg);
231 break;
232 case AD9832_OUTPUT_EN:
233 if (val)
234 st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR);
235 else
236 st->ctrl_src |= FIELD_PREP(AD9832_RESET, 1);
237
238 st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
239 st->ctrl_src);
240 ret = spi_sync(st->spi, &st->msg);
241 break;
242 default:
243 ret = -ENODEV;
244 }
245 mutex_unlock(&st->lock);
246
247 error_ret:
248 return ret ? ret : len;
249 }
250
251 /*
252 * see dds.h for further information
253 */
254
255 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
256 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
257 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
258 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
259
260 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
261 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
262 static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
263 static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
264 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
265 ad9832_write, AD9832_PHASE_SYM);
266 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
267
268 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
269 ad9832_write, AD9832_PINCTRL_EN);
270 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
271 ad9832_write, AD9832_OUTPUT_EN);
272
273 static struct attribute *ad9832_attributes[] = {
274 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
275 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
276 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
277 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
278 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
279 &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
280 &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
281 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
282 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
283 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
284 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
285 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
286 NULL,
287 };
288
289 static const struct attribute_group ad9832_attribute_group = {
290 .attrs = ad9832_attributes,
291 };
292
293 static const struct iio_info ad9832_info = {
294 .attrs = &ad9832_attribute_group,
295 };
296
ad9832_probe(struct spi_device * spi)297 static int ad9832_probe(struct spi_device *spi)
298 {
299 struct iio_dev *indio_dev;
300 struct ad9832_state *st;
301 int ret;
302
303 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
304 if (!indio_dev)
305 return -ENOMEM;
306
307 st = iio_priv(indio_dev);
308
309 ret = devm_regulator_get_enable(&spi->dev, "avdd");
310 if (ret)
311 return dev_err_probe(&spi->dev, ret, "failed to enable specified AVDD voltage\n");
312
313 ret = devm_regulator_get_enable(&spi->dev, "dvdd");
314 if (ret)
315 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVDD supply\n");
316
317 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
318 if (IS_ERR(st->mclk))
319 return PTR_ERR(st->mclk);
320
321 st->spi = spi;
322 mutex_init(&st->lock);
323
324 indio_dev->name = spi_get_device_id(spi)->name;
325 indio_dev->info = &ad9832_info;
326 indio_dev->modes = INDIO_DIRECT_MODE;
327
328 /* Setup default messages */
329 st->xfer.tx_buf = &st->data;
330 st->xfer.len = 2;
331
332 spi_message_init(&st->msg);
333 spi_message_add_tail(&st->xfer, &st->msg);
334
335 st->freq_xfer[0].tx_buf = &st->freq_data[0];
336 st->freq_xfer[0].len = 2;
337 st->freq_xfer[0].cs_change = 1;
338 st->freq_xfer[1].tx_buf = &st->freq_data[1];
339 st->freq_xfer[1].len = 2;
340 st->freq_xfer[1].cs_change = 1;
341 st->freq_xfer[2].tx_buf = &st->freq_data[2];
342 st->freq_xfer[2].len = 2;
343 st->freq_xfer[2].cs_change = 1;
344 st->freq_xfer[3].tx_buf = &st->freq_data[3];
345 st->freq_xfer[3].len = 2;
346
347 spi_message_init(&st->freq_msg);
348 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
349 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
350 spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
351 spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
352
353 st->phase_xfer[0].tx_buf = &st->phase_data[0];
354 st->phase_xfer[0].len = 2;
355 st->phase_xfer[0].cs_change = 1;
356 st->phase_xfer[1].tx_buf = &st->phase_data[1];
357 st->phase_xfer[1].len = 2;
358
359 spi_message_init(&st->phase_msg);
360 spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
361 spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
362
363 st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
364 st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
365 st->ctrl_src);
366 ret = spi_sync(st->spi, &st->msg);
367 if (ret) {
368 dev_err(&spi->dev, "device init failed\n");
369 return ret;
370 }
371
372 return devm_iio_device_register(&spi->dev, indio_dev);
373 }
374
375 static const struct of_device_id ad9832_of_match[] = {
376 { .compatible = "adi,ad9832" },
377 { .compatible = "adi,ad9835" },
378 { }
379 };
380 MODULE_DEVICE_TABLE(of, ad9832_of_match);
381
382 static const struct spi_device_id ad9832_id[] = {
383 {"ad9832", 0},
384 {"ad9835", 0},
385 { }
386 };
387 MODULE_DEVICE_TABLE(spi, ad9832_id);
388
389 static struct spi_driver ad9832_driver = {
390 .driver = {
391 .name = "ad9832",
392 .of_match_table = ad9832_of_match,
393 },
394 .probe = ad9832_probe,
395 .id_table = ad9832_id,
396 };
397 module_spi_driver(ad9832_driver);
398
399 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
400 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
401 MODULE_LICENSE("GPL v2");
402