1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7191 ADC driver
4 *
5 * Copyright 2025 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/mutex.h>
15 #include <linux/property.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/spi/spi.h>
18 #include <linux/types.h>
19 #include <linux/units.h>
20
21 #include <linux/iio/adc/ad_sigma_delta.h>
22 #include <linux/iio/iio.h>
23
24 #define ad_sigma_delta_to_ad7191(sigmad) \
25 container_of((sigmad), struct ad7191_state, sd)
26
27 #define AD7191_TEMP_CODES_PER_DEGREE 2815
28
29 #define AD7191_CHAN_MASK BIT(0)
30 #define AD7191_TEMP_MASK BIT(1)
31
32 enum ad7191_channel {
33 AD7191_CH_AIN1_AIN2,
34 AD7191_CH_AIN3_AIN4,
35 AD7191_CH_TEMP,
36 };
37
38 /*
39 * NOTE:
40 * The AD7191 features a dual-use data out ready DOUT/RDY output.
41 * In order to avoid contentions on the SPI bus, it's therefore necessary
42 * to use SPI bus locking.
43 *
44 * The DOUT/RDY output must also be wired to an interrupt-capable GPIO.
45 *
46 * The SPI controller's chip select must be connected to the PDOWN pin
47 * of the ADC. When CS (PDOWN) is high, it powers down the device and
48 * resets the internal circuitry.
49 */
50
51 struct ad7191_state {
52 struct ad_sigma_delta sd;
53 struct mutex lock; /* Protect device state */
54
55 struct gpio_descs *odr_gpios;
56 struct gpio_descs *pga_gpios;
57 struct gpio_desc *temp_gpio;
58 struct gpio_desc *chan_gpio;
59
60 u16 int_vref_mv;
61 const u32 (*scale_avail)[2];
62 size_t scale_avail_size;
63 u32 scale_index;
64 const u32 *samp_freq_avail;
65 size_t samp_freq_avail_size;
66 u32 samp_freq_index;
67
68 struct clk *mclk;
69 };
70
ad7191_set_channel(struct ad_sigma_delta * sd,unsigned int address)71 static int ad7191_set_channel(struct ad_sigma_delta *sd, unsigned int address)
72 {
73 struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd);
74 u8 temp_gpio_val, chan_gpio_val;
75
76 if (!FIELD_FIT(AD7191_CHAN_MASK | AD7191_TEMP_MASK, address))
77 return -EINVAL;
78
79 chan_gpio_val = FIELD_GET(AD7191_CHAN_MASK, address);
80 temp_gpio_val = FIELD_GET(AD7191_TEMP_MASK, address);
81
82 gpiod_set_value(st->chan_gpio, chan_gpio_val);
83 gpiod_set_value(st->temp_gpio, temp_gpio_val);
84
85 return 0;
86 }
87
ad7191_set_cs(struct ad_sigma_delta * sigma_delta,int assert)88 static int ad7191_set_cs(struct ad_sigma_delta *sigma_delta, int assert)
89 {
90 struct spi_transfer t = {
91 .len = 0,
92 .cs_change = assert,
93 };
94 struct spi_message m;
95
96 spi_message_init_with_transfers(&m, &t, 1);
97
98 return spi_sync_locked(sigma_delta->spi, &m);
99 }
100
ad7191_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)101 static int ad7191_set_mode(struct ad_sigma_delta *sd,
102 enum ad_sigma_delta_mode mode)
103 {
104 struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd);
105
106 switch (mode) {
107 case AD_SD_MODE_CONTINUOUS:
108 case AD_SD_MODE_SINGLE:
109 return ad7191_set_cs(&st->sd, 1);
110 case AD_SD_MODE_IDLE:
111 return ad7191_set_cs(&st->sd, 0);
112 default:
113 return -EINVAL;
114 }
115 }
116
117 static const struct ad_sigma_delta_info ad7191_sigma_delta_info = {
118 .set_channel = ad7191_set_channel,
119 .set_mode = ad7191_set_mode,
120 .has_registers = false,
121 };
122
ad7191_init_regulators(struct iio_dev * indio_dev)123 static int ad7191_init_regulators(struct iio_dev *indio_dev)
124 {
125 struct ad7191_state *st = iio_priv(indio_dev);
126 struct device *dev = &st->sd.spi->dev;
127 int ret;
128
129 ret = devm_regulator_get_enable(dev, "avdd");
130 if (ret)
131 return dev_err_probe(dev, ret, "Failed to enable specified AVdd supply\n");
132
133 ret = devm_regulator_get_enable(dev, "dvdd");
134 if (ret)
135 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
136
137 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
138 if (ret < 0)
139 return dev_err_probe(dev, ret, "Failed to get Vref voltage\n");
140
141 st->int_vref_mv = ret / 1000;
142
143 return 0;
144 }
145
ad7191_config_setup(struct iio_dev * indio_dev)146 static int ad7191_config_setup(struct iio_dev *indio_dev)
147 {
148 struct ad7191_state *st = iio_priv(indio_dev);
149 struct device *dev = &st->sd.spi->dev;
150 /* Sampling frequencies in Hz, see Table 5 */
151 static const u32 samp_freq[4] = { 120, 60, 50, 10 };
152 /* Gain options, see Table 7 */
153 const u32 gain[4] = { 1, 8, 64, 128 };
154 static u32 scale_buffer[4][2];
155 int odr_value, odr_index = 0, pga_value, pga_index = 0, i, ret;
156 const char *propname;
157 u64 scale_uv;
158
159 st->samp_freq_index = 0;
160 st->scale_index = 0;
161
162 propname = "adi,odr-value";
163 if (device_property_present(dev, propname)) {
164 ret = device_property_read_u32(dev, propname, &odr_value);
165 if (ret)
166 return dev_err_probe(dev, ret, "Failed to get %s.\n", propname);
167
168 for (i = 0; i < ARRAY_SIZE(samp_freq); i++) {
169 if (odr_value != samp_freq[i])
170 continue;
171 odr_index = i;
172 break;
173 }
174
175 st->samp_freq_avail = &samp_freq[odr_index];
176 st->samp_freq_avail_size = 1;
177
178 st->odr_gpios = NULL;
179 } else {
180 st->odr_gpios = devm_gpiod_get_array(dev, "odr", GPIOD_OUT_LOW);
181 if (IS_ERR(st->odr_gpios))
182 return dev_err_probe(dev, PTR_ERR(st->odr_gpios),
183 "Failed to get odr gpios.\n");
184
185 if (st->odr_gpios->ndescs != 2)
186 return dev_err_probe(dev, -EINVAL, "Expected 2 odr gpio pins.\n");
187
188 st->samp_freq_avail = samp_freq;
189 st->samp_freq_avail_size = ARRAY_SIZE(samp_freq);
190 }
191
192 mutex_lock(&st->lock);
193
194 for (i = 0; i < ARRAY_SIZE(scale_buffer); i++) {
195 scale_uv = ((u64)st->int_vref_mv * NANO) >>
196 (indio_dev->channels[0].scan_type.realbits - 1);
197 do_div(scale_uv, gain[i]);
198 scale_buffer[i][1] = do_div(scale_uv, NANO);
199 scale_buffer[i][0] = scale_uv;
200 }
201
202 mutex_unlock(&st->lock);
203
204 propname = "adi,pga-value";
205 if (device_property_present(dev, propname)) {
206 ret = device_property_read_u32(dev, propname, &pga_value);
207 if (ret)
208 return dev_err_probe(dev, ret, "Failed to get %s.\n", propname);
209
210 for (i = 0; i < ARRAY_SIZE(gain); i++) {
211 if (pga_value != gain[i])
212 continue;
213 pga_index = i;
214 break;
215 }
216
217 st->scale_avail = &scale_buffer[pga_index];
218 st->scale_avail_size = 1;
219
220 st->pga_gpios = NULL;
221 } else {
222 st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW);
223 if (IS_ERR(st->pga_gpios))
224 return dev_err_probe(dev, PTR_ERR(st->pga_gpios),
225 "Failed to get pga gpios.\n");
226
227 if (st->pga_gpios->ndescs != 2)
228 return dev_err_probe(dev, -EINVAL, "Expected 2 pga gpio pins.\n");
229
230 st->scale_avail = scale_buffer;
231 st->scale_avail_size = ARRAY_SIZE(scale_buffer);
232 }
233
234 st->temp_gpio = devm_gpiod_get(dev, "temp", GPIOD_OUT_LOW);
235 if (IS_ERR(st->temp_gpio))
236 return dev_err_probe(dev, PTR_ERR(st->temp_gpio),
237 "Failed to get temp gpio.\n");
238
239 st->chan_gpio = devm_gpiod_get(dev, "chan", GPIOD_OUT_LOW);
240 if (IS_ERR(st->chan_gpio))
241 return dev_err_probe(dev, PTR_ERR(st->chan_gpio),
242 "Failed to get chan gpio.\n");
243
244 return 0;
245 }
246
ad7191_clock_setup(struct ad7191_state * st)247 static int ad7191_clock_setup(struct ad7191_state *st)
248 {
249 struct device *dev = &st->sd.spi->dev;
250
251 st->mclk = devm_clk_get_optional_enabled(dev, "mclk");
252 if (IS_ERR(st->mclk))
253 return dev_err_probe(dev, PTR_ERR(st->mclk),
254 "Failed to get mclk.\n");
255
256 return 0;
257 }
258
ad7191_setup(struct iio_dev * indio_dev)259 static int ad7191_setup(struct iio_dev *indio_dev)
260 {
261 struct ad7191_state *st = iio_priv(indio_dev);
262 int ret;
263
264 ret = ad7191_init_regulators(indio_dev);
265 if (ret)
266 return ret;
267
268 ret = ad7191_config_setup(indio_dev);
269 if (ret)
270 return ret;
271
272 return ad7191_clock_setup(st);
273 }
274
ad7191_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)275 static int ad7191_read_raw(struct iio_dev *indio_dev,
276 struct iio_chan_spec const *chan, int *val,
277 int *val2, long m)
278 {
279 struct ad7191_state *st = iio_priv(indio_dev);
280
281 switch (m) {
282 case IIO_CHAN_INFO_RAW:
283 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
284 case IIO_CHAN_INFO_SCALE:
285 switch (chan->type) {
286 case IIO_VOLTAGE: {
287 guard(mutex)(&st->lock);
288 *val = st->scale_avail[st->scale_index][0];
289 *val2 = st->scale_avail[st->scale_index][1];
290 return IIO_VAL_INT_PLUS_NANO;
291 }
292 case IIO_TEMP:
293 *val = 0;
294 *val2 = NANO / AD7191_TEMP_CODES_PER_DEGREE;
295 return IIO_VAL_INT_PLUS_NANO;
296 default:
297 return -EINVAL;
298 }
299 case IIO_CHAN_INFO_OFFSET:
300 *val = -(1 << (chan->scan_type.realbits - 1));
301 switch (chan->type) {
302 case IIO_VOLTAGE:
303 return IIO_VAL_INT;
304 case IIO_TEMP:
305 *val -= 273 * AD7191_TEMP_CODES_PER_DEGREE;
306 return IIO_VAL_INT;
307 default:
308 return -EINVAL;
309 }
310 case IIO_CHAN_INFO_SAMP_FREQ:
311 *val = st->samp_freq_avail[st->samp_freq_index];
312 return IIO_VAL_INT;
313 default:
314 return -EINVAL;
315 }
316 }
317
ad7191_set_gain(struct ad7191_state * st,int gain_index)318 static int ad7191_set_gain(struct ad7191_state *st, int gain_index)
319 {
320 DECLARE_BITMAP(bitmap, 2) = { };
321
322 st->scale_index = gain_index;
323
324 bitmap_write(bitmap, gain_index, 0, 2);
325
326 return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap);
327 }
328
ad7191_set_samp_freq(struct ad7191_state * st,int samp_freq_index)329 static int ad7191_set_samp_freq(struct ad7191_state *st, int samp_freq_index)
330 {
331 DECLARE_BITMAP(bitmap, 2) = {};
332
333 st->samp_freq_index = samp_freq_index;
334
335 bitmap_write(bitmap, samp_freq_index, 0, 2);
336
337 return gpiod_multi_set_value_cansleep(st->odr_gpios, bitmap);
338 }
339
__ad7191_write_raw(struct ad7191_state * st,struct iio_chan_spec const * chan,int val,int val2,long mask)340 static int __ad7191_write_raw(struct ad7191_state *st,
341 struct iio_chan_spec const *chan,
342 int val, int val2, long mask)
343 {
344 int i;
345
346 switch (mask) {
347 case IIO_CHAN_INFO_SCALE: {
348 if (!st->pga_gpios)
349 return -EPERM;
350 guard(mutex)(&st->lock);
351 for (i = 0; i < st->scale_avail_size; i++) {
352 if (val2 == st->scale_avail[i][1])
353 return ad7191_set_gain(st, i);
354 }
355 return -EINVAL;
356 }
357 case IIO_CHAN_INFO_SAMP_FREQ: {
358 if (!st->odr_gpios)
359 return -EPERM;
360 guard(mutex)(&st->lock);
361 for (i = 0; i < st->samp_freq_avail_size; i++) {
362 if (val == st->samp_freq_avail[i])
363 return ad7191_set_samp_freq(st, i);
364 }
365 return -EINVAL;
366 }
367 default:
368 return -EINVAL;
369 }
370 }
371
ad7191_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)372 static int ad7191_write_raw(struct iio_dev *indio_dev,
373 struct iio_chan_spec const *chan, int val, int val2,
374 long mask)
375 {
376 struct ad7191_state *st = iio_priv(indio_dev);
377 int ret;
378
379 if (!iio_device_claim_direct(indio_dev))
380 return -EBUSY;
381
382 ret = __ad7191_write_raw(st, chan, val, val2, mask);
383
384 iio_device_release_direct(indio_dev);
385
386 return ret;
387 }
388
ad7191_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)389 static int ad7191_write_raw_get_fmt(struct iio_dev *indio_dev,
390 struct iio_chan_spec const *chan, long mask)
391 {
392 switch (mask) {
393 case IIO_CHAN_INFO_SCALE:
394 return IIO_VAL_INT_PLUS_NANO;
395 case IIO_CHAN_INFO_SAMP_FREQ:
396 return IIO_VAL_INT;
397 default:
398 return -EINVAL;
399 }
400 }
401
ad7191_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)402 static int ad7191_read_avail(struct iio_dev *indio_dev,
403 struct iio_chan_spec const *chan, const int **vals,
404 int *type, int *length, long mask)
405 {
406 struct ad7191_state *st = iio_priv(indio_dev);
407
408 switch (mask) {
409 case IIO_CHAN_INFO_SCALE:
410 *vals = (int *)st->scale_avail;
411 *type = IIO_VAL_INT_PLUS_NANO;
412 *length = st->scale_avail_size * 2;
413 return IIO_AVAIL_LIST;
414 case IIO_CHAN_INFO_SAMP_FREQ:
415 *vals = (int *)st->samp_freq_avail;
416 *type = IIO_VAL_INT;
417 *length = st->samp_freq_avail_size;
418 return IIO_AVAIL_LIST;
419 }
420
421 return -EINVAL;
422 }
423
424 static const struct iio_info ad7191_info = {
425 .read_raw = ad7191_read_raw,
426 .write_raw = ad7191_write_raw,
427 .write_raw_get_fmt = ad7191_write_raw_get_fmt,
428 .read_avail = ad7191_read_avail,
429 .validate_trigger = ad_sd_validate_trigger,
430 };
431
432 static const struct iio_chan_spec ad7191_channels[] = {
433 {
434 .type = IIO_TEMP,
435 .address = AD7191_CH_TEMP,
436 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
437 BIT(IIO_CHAN_INFO_OFFSET) |
438 BIT(IIO_CHAN_INFO_SAMP_FREQ),
439 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
440 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
441 .scan_type = {
442 .sign = 'u',
443 .realbits = 24,
444 .storagebits = 32,
445 .endianness = IIO_BE,
446 },
447 },
448 {
449 .type = IIO_VOLTAGE,
450 .differential = 1,
451 .indexed = 1,
452 .channel = 1,
453 .channel2 = 2,
454 .address = AD7191_CH_AIN1_AIN2,
455 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
456 BIT(IIO_CHAN_INFO_OFFSET) |
457 BIT(IIO_CHAN_INFO_SAMP_FREQ),
458 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
459 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
460 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
461 .scan_index = 1,
462 .scan_type = {
463 .sign = 'u',
464 .realbits = 24,
465 .storagebits = 32,
466 .endianness = IIO_BE,
467 },
468 },
469 {
470 .type = IIO_VOLTAGE,
471 .differential = 1,
472 .indexed = 1,
473 .channel = 3,
474 .channel2 = 4,
475 .address = AD7191_CH_AIN3_AIN4,
476 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
477 BIT(IIO_CHAN_INFO_OFFSET) |
478 BIT(IIO_CHAN_INFO_SAMP_FREQ),
479 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
480 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
481 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
482 .scan_index = 2,
483 .scan_type = {
484 .sign = 'u',
485 .realbits = 24,
486 .storagebits = 32,
487 .endianness = IIO_BE,
488 },
489 },
490 IIO_CHAN_SOFT_TIMESTAMP(3),
491 };
492
ad7191_probe(struct spi_device * spi)493 static int ad7191_probe(struct spi_device *spi)
494 {
495 struct device *dev = &spi->dev;
496 struct ad7191_state *st;
497 struct iio_dev *indio_dev;
498 int ret;
499
500 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
501 if (!indio_dev)
502 return -ENOMEM;
503
504 st = iio_priv(indio_dev);
505
506 ret = devm_mutex_init(dev, &st->lock);
507 if (ret)
508 return ret;
509
510 indio_dev->name = "ad7191";
511 indio_dev->modes = INDIO_DIRECT_MODE;
512 indio_dev->channels = ad7191_channels;
513 indio_dev->num_channels = ARRAY_SIZE(ad7191_channels);
514 indio_dev->info = &ad7191_info;
515
516 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7191_sigma_delta_info);
517 if (ret)
518 return ret;
519
520 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
521 if (ret)
522 return ret;
523
524 ret = ad7191_setup(indio_dev);
525 if (ret)
526 return ret;
527
528 return devm_iio_device_register(dev, indio_dev);
529 }
530
531 static const struct of_device_id ad7191_of_match[] = {
532 { .compatible = "adi,ad7191", },
533 { }
534 };
535 MODULE_DEVICE_TABLE(of, ad7191_of_match);
536
537 static const struct spi_device_id ad7191_id_table[] = {
538 { .name = "ad7191" },
539 { }
540 };
541 MODULE_DEVICE_TABLE(spi, ad7191_id_table);
542
543 static struct spi_driver ad7191_driver = {
544 .driver = {
545 .name = "ad7191",
546 .of_match_table = ad7191_of_match,
547 },
548 .probe = ad7191_probe,
549 .id_table = ad7191_id_table,
550 };
551 module_spi_driver(ad7191_driver);
552
553 MODULE_AUTHOR("Alisa-Dariana Roman <alisa.roman@analog.com>");
554 MODULE_DESCRIPTION("Analog Devices AD7191 ADC");
555 MODULE_LICENSE("GPL");
556 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
557