1 /*
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "lib/events.h"
34 #include "en.h"
35 #include "en_accel/ktls.h"
36 #include "en_accel/en_accel.h"
37 #include "en/ptp.h"
38 #include "en/port.h"
39
40 #include <net/page_pool/helpers.h>
41
mlx5e_ethtool_put_stat(u64 ** data,u64 val)42 void mlx5e_ethtool_put_stat(u64 **data, u64 val)
43 {
44 *(*data)++ = val;
45 }
46
stats_grps_num(struct mlx5e_priv * priv)47 static unsigned int stats_grps_num(struct mlx5e_priv *priv)
48 {
49 return !priv->profile->stats_grps_num ? 0 :
50 priv->profile->stats_grps_num(priv);
51 }
52
mlx5e_stats_total_num(struct mlx5e_priv * priv)53 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv)
54 {
55 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
56 const unsigned int num_stats_grps = stats_grps_num(priv);
57 unsigned int total = 0;
58 int i;
59
60 for (i = 0; i < num_stats_grps; i++)
61 total += stats_grps[i]->get_num_stats(priv);
62
63 return total;
64 }
65
mlx5e_stats_update_ndo_stats(struct mlx5e_priv * priv)66 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv)
67 {
68 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
69 const unsigned int num_stats_grps = stats_grps_num(priv);
70 int i;
71
72 for (i = num_stats_grps - 1; i >= 0; i--)
73 if (stats_grps[i]->update_stats &&
74 stats_grps[i]->update_stats_mask & MLX5E_NDO_UPDATE_STATS)
75 stats_grps[i]->update_stats(priv);
76 }
77
mlx5e_stats_update(struct mlx5e_priv * priv)78 void mlx5e_stats_update(struct mlx5e_priv *priv)
79 {
80 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
81 const unsigned int num_stats_grps = stats_grps_num(priv);
82 int i;
83
84 for (i = num_stats_grps - 1; i >= 0; i--)
85 if (stats_grps[i]->update_stats)
86 stats_grps[i]->update_stats(priv);
87 }
88
mlx5e_stats_fill(struct mlx5e_priv * priv,u64 * data,int idx)89 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx)
90 {
91 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
92 const unsigned int num_stats_grps = stats_grps_num(priv);
93 int i;
94
95 for (i = 0; i < num_stats_grps; i++)
96 stats_grps[i]->fill_stats(priv, &data);
97 }
98
mlx5e_stats_fill_strings(struct mlx5e_priv * priv,u8 * data)99 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data)
100 {
101 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
102 const unsigned int num_stats_grps = stats_grps_num(priv);
103 int i;
104
105 for (i = 0; i < num_stats_grps; i++)
106 stats_grps[i]->fill_strings(priv, &data);
107 }
108
109 /* Concrete NIC Stats */
110
111 static const struct counter_desc sw_stats_desc[] = {
112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
113 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
114 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
121 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
122 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_mpwqe_blks) },
123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_mpwqe_pkts) },
124
125 #ifdef CONFIG_MLX5_EN_TLS
126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_packets) },
127 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_bytes) },
128 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
129 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_packets) },
130 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_bytes) },
131 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
132 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_skip_no_sync_data) },
133 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_no_sync_data) },
134 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_bypass_req) },
135 #endif
136
137 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
138 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
139 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_packets) },
140 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_bytes) },
141 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_skbs) },
142 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_large_hds) },
143 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_hds_nodata_packets) },
144 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_hds_nodata_bytes) },
145 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_hds_nosplit_packets) },
146 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_hds_nosplit_bytes) },
147 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) },
148 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
149 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
150 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
151 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
152 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) },
153 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) },
154 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
155 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
156 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
157 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
158 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_mpwqe) },
159 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_inlnw) },
160 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_nops) },
161 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
162 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
163 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
164 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
165 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
166 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
167 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
168 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
169 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
170 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
171 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
172 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
173 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
174 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) },
175 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_mpwqe) },
176 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_inlnw) },
177 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_nops) },
178 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) },
179 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) },
180 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) },
181 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
182 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
183 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
184 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) },
185 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
186 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
187 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
188 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
189 #ifdef CONFIG_MLX5_EN_ARFS
190 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_add) },
191 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_in) },
192 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_out) },
193 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_expired) },
194 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) },
195 #endif
196 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) },
197 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_fast) },
198 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_slow) },
199 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_slow_high_order) },
200 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_empty) },
201 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_refill) },
202 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_waive) },
203 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_cached) },
204 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_cache_full) },
205 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring) },
206 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring_full) },
207 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_released_ref) },
208 #ifdef CONFIG_MLX5_EN_TLS
209 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_packets) },
210 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_bytes) },
211 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_pkt) },
212 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_start) },
213 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_end) },
214 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_skip) },
215 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_ok) },
216 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_retry) },
217 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_skip) },
218 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_err) },
219 #endif
220 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
221 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
222 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
223 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
224 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_force_irq) },
225 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
226 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_packets) },
227 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_bytes) },
228 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_complete) },
229 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary) },
230 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary_inner) },
231 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_none) },
232 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_ecn_mark) },
233 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_removed_vlan_packets) },
234 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_drop) },
235 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_redirect) },
236 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_wqe_err) },
237 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_cqes) },
238 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_strides) },
239 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_oversize_pkts_sw_drop) },
240 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_buff_alloc_err) },
241 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) },
242 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) },
243 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) },
244 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) },
245 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) },
246 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) },
247 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_full) },
248 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_err) },
249 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_cqes) },
250 };
251
252 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
253
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw)254 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw)
255 {
256 return NUM_SW_COUNTERS;
257 }
258
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(sw)259 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(sw)
260 {
261 int i;
262
263 for (i = 0; i < NUM_SW_COUNTERS; i++)
264 ethtool_puts(data, sw_stats_desc[i].format);
265 }
266
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw)267 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw)
268 {
269 int i;
270
271 for (i = 0; i < NUM_SW_COUNTERS; i++)
272 mlx5e_ethtool_put_stat(data,
273 MLX5E_READ_CTR64_CPU(&priv->stats.sw,
274 sw_stats_desc, i));
275 }
276
mlx5e_stats_grp_sw_update_stats_xdp_red(struct mlx5e_sw_stats * s,struct mlx5e_xdpsq_stats * xdpsq_red_stats)277 static void mlx5e_stats_grp_sw_update_stats_xdp_red(struct mlx5e_sw_stats *s,
278 struct mlx5e_xdpsq_stats *xdpsq_red_stats)
279 {
280 s->tx_xdp_xmit += xdpsq_red_stats->xmit;
281 s->tx_xdp_mpwqe += xdpsq_red_stats->mpwqe;
282 s->tx_xdp_inlnw += xdpsq_red_stats->inlnw;
283 s->tx_xdp_nops += xdpsq_red_stats->nops;
284 s->tx_xdp_full += xdpsq_red_stats->full;
285 s->tx_xdp_err += xdpsq_red_stats->err;
286 s->tx_xdp_cqes += xdpsq_red_stats->cqes;
287 }
288
mlx5e_stats_grp_sw_update_stats_xdpsq(struct mlx5e_sw_stats * s,struct mlx5e_xdpsq_stats * xdpsq_stats)289 static void mlx5e_stats_grp_sw_update_stats_xdpsq(struct mlx5e_sw_stats *s,
290 struct mlx5e_xdpsq_stats *xdpsq_stats)
291 {
292 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
293 s->rx_xdp_tx_mpwqe += xdpsq_stats->mpwqe;
294 s->rx_xdp_tx_inlnw += xdpsq_stats->inlnw;
295 s->rx_xdp_tx_nops += xdpsq_stats->nops;
296 s->rx_xdp_tx_full += xdpsq_stats->full;
297 s->rx_xdp_tx_err += xdpsq_stats->err;
298 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
299 }
300
mlx5e_stats_grp_sw_update_stats_xsksq(struct mlx5e_sw_stats * s,struct mlx5e_xdpsq_stats * xsksq_stats)301 static void mlx5e_stats_grp_sw_update_stats_xsksq(struct mlx5e_sw_stats *s,
302 struct mlx5e_xdpsq_stats *xsksq_stats)
303 {
304 s->tx_xsk_xmit += xsksq_stats->xmit;
305 s->tx_xsk_mpwqe += xsksq_stats->mpwqe;
306 s->tx_xsk_inlnw += xsksq_stats->inlnw;
307 s->tx_xsk_full += xsksq_stats->full;
308 s->tx_xsk_err += xsksq_stats->err;
309 s->tx_xsk_cqes += xsksq_stats->cqes;
310 }
311
mlx5e_stats_grp_sw_update_stats_xskrq(struct mlx5e_sw_stats * s,struct mlx5e_rq_stats * xskrq_stats)312 static void mlx5e_stats_grp_sw_update_stats_xskrq(struct mlx5e_sw_stats *s,
313 struct mlx5e_rq_stats *xskrq_stats)
314 {
315 s->rx_xsk_packets += xskrq_stats->packets;
316 s->rx_xsk_bytes += xskrq_stats->bytes;
317 s->rx_xsk_csum_complete += xskrq_stats->csum_complete;
318 s->rx_xsk_csum_unnecessary += xskrq_stats->csum_unnecessary;
319 s->rx_xsk_csum_unnecessary_inner += xskrq_stats->csum_unnecessary_inner;
320 s->rx_xsk_csum_none += xskrq_stats->csum_none;
321 s->rx_xsk_ecn_mark += xskrq_stats->ecn_mark;
322 s->rx_xsk_removed_vlan_packets += xskrq_stats->removed_vlan_packets;
323 s->rx_xsk_xdp_drop += xskrq_stats->xdp_drop;
324 s->rx_xsk_xdp_redirect += xskrq_stats->xdp_redirect;
325 s->rx_xsk_wqe_err += xskrq_stats->wqe_err;
326 s->rx_xsk_mpwqe_filler_cqes += xskrq_stats->mpwqe_filler_cqes;
327 s->rx_xsk_mpwqe_filler_strides += xskrq_stats->mpwqe_filler_strides;
328 s->rx_xsk_oversize_pkts_sw_drop += xskrq_stats->oversize_pkts_sw_drop;
329 s->rx_xsk_buff_alloc_err += xskrq_stats->buff_alloc_err;
330 s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks;
331 s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts;
332 s->rx_xsk_congst_umr += xskrq_stats->congst_umr;
333 }
334
mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats * s,struct mlx5e_rq_stats * rq_stats)335 static void mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats *s,
336 struct mlx5e_rq_stats *rq_stats)
337 {
338 s->rx_packets += rq_stats->packets;
339 s->rx_bytes += rq_stats->bytes;
340 s->rx_lro_packets += rq_stats->lro_packets;
341 s->rx_lro_bytes += rq_stats->lro_bytes;
342 s->rx_gro_packets += rq_stats->gro_packets;
343 s->rx_gro_bytes += rq_stats->gro_bytes;
344 s->rx_gro_skbs += rq_stats->gro_skbs;
345 s->rx_gro_large_hds += rq_stats->gro_large_hds;
346 s->rx_hds_nodata_packets += rq_stats->hds_nodata_packets;
347 s->rx_hds_nodata_bytes += rq_stats->hds_nodata_bytes;
348 s->rx_hds_nosplit_packets += rq_stats->hds_nosplit_packets;
349 s->rx_hds_nosplit_bytes += rq_stats->hds_nosplit_bytes;
350 s->rx_ecn_mark += rq_stats->ecn_mark;
351 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
352 s->rx_csum_none += rq_stats->csum_none;
353 s->rx_csum_complete += rq_stats->csum_complete;
354 s->rx_csum_complete_tail += rq_stats->csum_complete_tail;
355 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow;
356 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
357 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
358 s->rx_xdp_drop += rq_stats->xdp_drop;
359 s->rx_xdp_redirect += rq_stats->xdp_redirect;
360 s->rx_wqe_err += rq_stats->wqe_err;
361 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
362 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
363 s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop;
364 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
365 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
366 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
367 s->rx_congst_umr += rq_stats->congst_umr;
368 #ifdef CONFIG_MLX5_EN_ARFS
369 s->rx_arfs_add += rq_stats->arfs_add;
370 s->rx_arfs_request_in += rq_stats->arfs_request_in;
371 s->rx_arfs_request_out += rq_stats->arfs_request_out;
372 s->rx_arfs_expired += rq_stats->arfs_expired;
373 s->rx_arfs_err += rq_stats->arfs_err;
374 #endif
375 s->rx_recover += rq_stats->recover;
376 s->rx_pp_alloc_fast += rq_stats->pp_alloc_fast;
377 s->rx_pp_alloc_slow += rq_stats->pp_alloc_slow;
378 s->rx_pp_alloc_empty += rq_stats->pp_alloc_empty;
379 s->rx_pp_alloc_refill += rq_stats->pp_alloc_refill;
380 s->rx_pp_alloc_waive += rq_stats->pp_alloc_waive;
381 s->rx_pp_alloc_slow_high_order += rq_stats->pp_alloc_slow_high_order;
382 s->rx_pp_recycle_cached += rq_stats->pp_recycle_cached;
383 s->rx_pp_recycle_cache_full += rq_stats->pp_recycle_cache_full;
384 s->rx_pp_recycle_ring += rq_stats->pp_recycle_ring;
385 s->rx_pp_recycle_ring_full += rq_stats->pp_recycle_ring_full;
386 s->rx_pp_recycle_released_ref += rq_stats->pp_recycle_released_ref;
387 #ifdef CONFIG_MLX5_EN_TLS
388 s->rx_tls_decrypted_packets += rq_stats->tls_decrypted_packets;
389 s->rx_tls_decrypted_bytes += rq_stats->tls_decrypted_bytes;
390 s->rx_tls_resync_req_pkt += rq_stats->tls_resync_req_pkt;
391 s->rx_tls_resync_req_start += rq_stats->tls_resync_req_start;
392 s->rx_tls_resync_req_end += rq_stats->tls_resync_req_end;
393 s->rx_tls_resync_req_skip += rq_stats->tls_resync_req_skip;
394 s->rx_tls_resync_res_ok += rq_stats->tls_resync_res_ok;
395 s->rx_tls_resync_res_retry += rq_stats->tls_resync_res_retry;
396 s->rx_tls_resync_res_skip += rq_stats->tls_resync_res_skip;
397 s->rx_tls_err += rq_stats->tls_err;
398 #endif
399 }
400
mlx5e_stats_grp_sw_update_stats_ch_stats(struct mlx5e_sw_stats * s,struct mlx5e_ch_stats * ch_stats)401 static void mlx5e_stats_grp_sw_update_stats_ch_stats(struct mlx5e_sw_stats *s,
402 struct mlx5e_ch_stats *ch_stats)
403 {
404 s->ch_events += ch_stats->events;
405 s->ch_poll += ch_stats->poll;
406 s->ch_arm += ch_stats->arm;
407 s->ch_aff_change += ch_stats->aff_change;
408 s->ch_force_irq += ch_stats->force_irq;
409 s->ch_eq_rearm += ch_stats->eq_rearm;
410 }
411
mlx5e_stats_grp_sw_update_stats_sq(struct mlx5e_sw_stats * s,struct mlx5e_sq_stats * sq_stats)412 static void mlx5e_stats_grp_sw_update_stats_sq(struct mlx5e_sw_stats *s,
413 struct mlx5e_sq_stats *sq_stats)
414 {
415 s->tx_packets += sq_stats->packets;
416 s->tx_bytes += sq_stats->bytes;
417 s->tx_tso_packets += sq_stats->tso_packets;
418 s->tx_tso_bytes += sq_stats->tso_bytes;
419 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
420 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
421 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
422 s->tx_nop += sq_stats->nop;
423 s->tx_mpwqe_blks += sq_stats->mpwqe_blks;
424 s->tx_mpwqe_pkts += sq_stats->mpwqe_pkts;
425 s->tx_queue_stopped += sq_stats->stopped;
426 s->tx_queue_wake += sq_stats->wake;
427 s->tx_queue_dropped += sq_stats->dropped;
428 s->tx_cqe_err += sq_stats->cqe_err;
429 s->tx_recover += sq_stats->recover;
430 s->tx_xmit_more += sq_stats->xmit_more;
431 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
432 s->tx_csum_none += sq_stats->csum_none;
433 s->tx_csum_partial += sq_stats->csum_partial;
434 #ifdef CONFIG_MLX5_EN_TLS
435 s->tx_tls_encrypted_packets += sq_stats->tls_encrypted_packets;
436 s->tx_tls_encrypted_bytes += sq_stats->tls_encrypted_bytes;
437 s->tx_tls_ooo += sq_stats->tls_ooo;
438 s->tx_tls_dump_bytes += sq_stats->tls_dump_bytes;
439 s->tx_tls_dump_packets += sq_stats->tls_dump_packets;
440 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
441 s->tx_tls_skip_no_sync_data += sq_stats->tls_skip_no_sync_data;
442 s->tx_tls_drop_no_sync_data += sq_stats->tls_drop_no_sync_data;
443 s->tx_tls_drop_bypass_req += sq_stats->tls_drop_bypass_req;
444 #endif
445 s->tx_cqes += sq_stats->cqes;
446 }
447
mlx5e_stats_grp_sw_update_stats_ptp(struct mlx5e_priv * priv,struct mlx5e_sw_stats * s)448 static void mlx5e_stats_grp_sw_update_stats_ptp(struct mlx5e_priv *priv,
449 struct mlx5e_sw_stats *s)
450 {
451 int i;
452
453 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
454 return;
455
456 mlx5e_stats_grp_sw_update_stats_ch_stats(s, &priv->ptp_stats.ch);
457
458 if (priv->tx_ptp_opened) {
459 for (i = 0; i < priv->max_opened_tc; i++) {
460 mlx5e_stats_grp_sw_update_stats_sq(s, &priv->ptp_stats.sq[i]);
461
462 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
463 barrier();
464 }
465 }
466 if (priv->rx_ptp_opened) {
467 mlx5e_stats_grp_sw_update_stats_rq_stats(s, &priv->ptp_stats.rq);
468
469 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
470 barrier();
471 }
472 }
473
mlx5e_stats_grp_sw_update_stats_qos(struct mlx5e_priv * priv,struct mlx5e_sw_stats * s)474 static void mlx5e_stats_grp_sw_update_stats_qos(struct mlx5e_priv *priv,
475 struct mlx5e_sw_stats *s)
476 {
477 struct mlx5e_sq_stats **stats;
478 u16 max_qos_sqs;
479 int i;
480
481 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
482 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
483 stats = READ_ONCE(priv->htb_qos_sq_stats);
484
485 for (i = 0; i < max_qos_sqs; i++) {
486 mlx5e_stats_grp_sw_update_stats_sq(s, READ_ONCE(stats[i]));
487
488 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
489 barrier();
490 }
491 }
492
mlx5e_stats_update_stats_rq_page_pool(struct mlx5e_channel * c)493 static void mlx5e_stats_update_stats_rq_page_pool(struct mlx5e_channel *c)
494 {
495 struct mlx5e_rq_stats *rq_stats = c->rq.stats;
496 struct page_pool *pool = c->rq.page_pool;
497 struct page_pool_stats stats = { 0 };
498
499 page_pool_get_stats(pool, &stats);
500
501 rq_stats->pp_alloc_fast = stats.alloc_stats.fast;
502 rq_stats->pp_alloc_slow = stats.alloc_stats.slow;
503 rq_stats->pp_alloc_slow_high_order = stats.alloc_stats.slow_high_order;
504 rq_stats->pp_alloc_empty = stats.alloc_stats.empty;
505 rq_stats->pp_alloc_waive = stats.alloc_stats.waive;
506 rq_stats->pp_alloc_refill = stats.alloc_stats.refill;
507
508 rq_stats->pp_recycle_cached = stats.recycle_stats.cached;
509 rq_stats->pp_recycle_cache_full = stats.recycle_stats.cache_full;
510 rq_stats->pp_recycle_ring = stats.recycle_stats.ring;
511 rq_stats->pp_recycle_ring_full = stats.recycle_stats.ring_full;
512 rq_stats->pp_recycle_released_ref = stats.recycle_stats.released_refcnt;
513 }
514
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw)515 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw)
516 {
517 struct mlx5e_sw_stats *s = &priv->stats.sw;
518 u16 nch = mlx5e_stats_nch_read(priv);
519 int i;
520
521 memset(s, 0, sizeof(*s));
522
523 for (i = 0; i < priv->channels.num; i++) /* for active channels only */
524 mlx5e_stats_update_stats_rq_page_pool(priv->channels.c[i]);
525
526 for (i = 0; i < nch; i++) {
527 struct mlx5e_channel_stats *channel_stats =
528 priv->channel_stats[i];
529
530 int j;
531
532 mlx5e_stats_grp_sw_update_stats_rq_stats(s, &channel_stats->rq);
533 mlx5e_stats_grp_sw_update_stats_xdpsq(s, &channel_stats->rq_xdpsq);
534 mlx5e_stats_grp_sw_update_stats_ch_stats(s, &channel_stats->ch);
535 /* xdp redirect */
536 mlx5e_stats_grp_sw_update_stats_xdp_red(s, &channel_stats->xdpsq);
537 /* AF_XDP zero-copy */
538 mlx5e_stats_grp_sw_update_stats_xskrq(s, &channel_stats->xskrq);
539 mlx5e_stats_grp_sw_update_stats_xsksq(s, &channel_stats->xsksq);
540
541 for (j = 0; j < priv->max_opened_tc; j++) {
542 mlx5e_stats_grp_sw_update_stats_sq(s, &channel_stats->sq[j]);
543
544 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
545 barrier();
546 }
547 }
548 mlx5e_stats_grp_sw_update_stats_ptp(priv, s);
549 mlx5e_stats_grp_sw_update_stats_qos(priv, s);
550 }
551
552 static const struct counter_desc q_stats_desc[] = {
553 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
554 };
555
556 static const struct counter_desc drop_rq_stats_desc[] = {
557 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
558 };
559
560 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
561 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
562
q_counter_any(struct mlx5e_priv * priv)563 static bool q_counter_any(struct mlx5e_priv *priv)
564 {
565 struct mlx5_core_dev *pos;
566 int i;
567
568 mlx5_sd_for_each_dev(i, priv->mdev, pos)
569 if (priv->q_counter[i++])
570 return true;
571
572 return false;
573 }
574
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qcnt)575 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qcnt)
576 {
577 int num_stats = 0;
578
579 if (q_counter_any(priv))
580 num_stats += NUM_Q_COUNTERS;
581
582 if (priv->drop_rq_q_counter)
583 num_stats += NUM_DROP_RQ_COUNTERS;
584
585 return num_stats;
586 }
587
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qcnt)588 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qcnt)
589 {
590 int i;
591
592 for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
593 ethtool_puts(data, q_stats_desc[i].format);
594
595 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
596 ethtool_puts(data, drop_rq_stats_desc[i].format);
597 }
598
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt)599 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt)
600 {
601 int i;
602
603 for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
604 mlx5e_ethtool_put_stat(data,
605 MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
606 q_stats_desc, i));
607 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
608 mlx5e_ethtool_put_stat(
609 data, MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
610 drop_rq_stats_desc, i));
611 }
612
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt)613 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt)
614 {
615 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
616 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {};
617 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {};
618 struct mlx5_core_dev *pos;
619 u32 rx_out_of_buffer = 0;
620 int ret, i;
621
622 MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER);
623
624 mlx5_sd_for_each_dev(i, priv->mdev, pos) {
625 if (priv->q_counter[i]) {
626 MLX5_SET(query_q_counter_in, in, counter_set_id,
627 priv->q_counter[i]);
628 ret = mlx5_cmd_exec_inout(pos, query_q_counter, in, out);
629 if (!ret)
630 rx_out_of_buffer += MLX5_GET(query_q_counter_out,
631 out, out_of_buffer);
632 }
633 }
634 qcnt->rx_out_of_buffer = rx_out_of_buffer;
635
636 if (priv->drop_rq_q_counter) {
637 MLX5_SET(query_q_counter_in, in, counter_set_id,
638 priv->drop_rq_q_counter);
639 ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
640 if (!ret)
641 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out,
642 out, out_of_buffer);
643 }
644 }
645
646 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
647 static const struct counter_desc vnic_env_stats_steer_desc[] = {
648 { "rx_steer_missed_packets",
649 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
650 };
651
652 static const struct counter_desc vnic_env_stats_dev_oob_desc[] = {
653 { "dev_internal_queue_oob",
654 VNIC_ENV_OFF(vport_env.internal_rq_out_of_buffer) },
655 };
656
657 static const struct counter_desc vnic_env_stats_drop_desc[] = {
658 { "rx_oversize_pkts_buffer",
659 VNIC_ENV_OFF(vport_env.eth_wqe_too_small) },
660 };
661
662 #define NUM_VNIC_ENV_STEER_COUNTERS(dev) \
663 (MLX5_CAP_GEN(dev, nic_receive_steering_discard) ? \
664 ARRAY_SIZE(vnic_env_stats_steer_desc) : 0)
665 #define NUM_VNIC_ENV_DEV_OOB_COUNTERS(dev) \
666 (MLX5_CAP_GEN(dev, vnic_env_int_rq_oob) ? \
667 ARRAY_SIZE(vnic_env_stats_dev_oob_desc) : 0)
668 #define NUM_VNIC_ENV_DROP_COUNTERS(dev) \
669 (MLX5_CAP_GEN(dev, eth_wqe_too_small) ? \
670 ARRAY_SIZE(vnic_env_stats_drop_desc) : 0)
671
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vnic_env)672 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vnic_env)
673 {
674 return NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev) +
675 NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev) +
676 NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev);
677 }
678
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vnic_env)679 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vnic_env)
680 {
681 int i;
682
683 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
684 ethtool_puts(data, vnic_env_stats_steer_desc[i].format);
685
686 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
687 ethtool_puts(data, vnic_env_stats_dev_oob_desc[i].format);
688
689 for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
690 ethtool_puts(data, vnic_env_stats_drop_desc[i].format);
691 }
692
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env)693 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env)
694 {
695 int i;
696
697 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
698 mlx5e_ethtool_put_stat(
699 data,
700 MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
701 vnic_env_stats_steer_desc, i));
702
703 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
704 mlx5e_ethtool_put_stat(
705 data,
706 MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
707 vnic_env_stats_dev_oob_desc, i));
708
709 for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
710 mlx5e_ethtool_put_stat(
711 data,
712 MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
713 vnic_env_stats_drop_desc, i));
714 }
715
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env)716 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env)
717 {
718 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
719 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
720 struct mlx5_core_dev *mdev = priv->mdev;
721
722 if (!mlx5e_stats_grp_vnic_env_num_stats(priv))
723 return;
724
725 MLX5_SET(query_vnic_env_in, in, opcode, MLX5_CMD_OP_QUERY_VNIC_ENV);
726 mlx5_cmd_exec_inout(mdev, query_vnic_env, in, out);
727 }
728
729 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
730 static const struct counter_desc vport_stats_desc[] = {
731 { "rx_vport_unicast_packets",
732 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
733 { "rx_vport_unicast_bytes",
734 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
735 { "tx_vport_unicast_packets",
736 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
737 { "tx_vport_unicast_bytes",
738 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
739 { "rx_vport_multicast_packets",
740 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
741 { "rx_vport_multicast_bytes",
742 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
743 { "tx_vport_multicast_packets",
744 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
745 { "tx_vport_multicast_bytes",
746 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
747 { "rx_vport_broadcast_packets",
748 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
749 { "rx_vport_broadcast_bytes",
750 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
751 { "tx_vport_broadcast_packets",
752 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
753 { "tx_vport_broadcast_bytes",
754 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
755 { "rx_vport_rdma_unicast_packets",
756 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
757 { "rx_vport_rdma_unicast_bytes",
758 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
759 { "tx_vport_rdma_unicast_packets",
760 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
761 { "tx_vport_rdma_unicast_bytes",
762 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
763 { "rx_vport_rdma_multicast_packets",
764 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
765 { "rx_vport_rdma_multicast_bytes",
766 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
767 { "tx_vport_rdma_multicast_packets",
768 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
769 { "tx_vport_rdma_multicast_bytes",
770 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
771 };
772
773 static const struct counter_desc vport_loopback_stats_desc[] = {
774 { "vport_loopback_packets",
775 VPORT_COUNTER_OFF(local_loopback.packets) },
776 { "vport_loopback_bytes",
777 VPORT_COUNTER_OFF(local_loopback.octets) },
778 };
779
780 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
781 #define NUM_VPORT_LOOPBACK_COUNTERS(dev) \
782 (MLX5_CAP_GEN(dev, vport_counter_local_loopback) ? \
783 ARRAY_SIZE(vport_loopback_stats_desc) : 0)
784
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport)785 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport)
786 {
787 return NUM_VPORT_COUNTERS +
788 NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev);
789 }
790
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport)791 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport)
792 {
793 int i;
794
795 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
796 ethtool_puts(data, vport_stats_desc[i].format);
797
798 for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
799 ethtool_puts(data, vport_loopback_stats_desc[i].format);
800 }
801
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport)802 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport)
803 {
804 int i;
805
806 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
807 mlx5e_ethtool_put_stat(
808 data,
809 MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
810 vport_stats_desc, i));
811
812 for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
813 mlx5e_ethtool_put_stat(
814 data,
815 MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
816 vport_loopback_stats_desc, i));
817 }
818
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport)819 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport)
820 {
821 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
822 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {};
823 struct mlx5_core_dev *mdev = priv->mdev;
824
825 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
826 mlx5_cmd_exec_inout(mdev, query_vport_counter, in, out);
827 }
828
829 #define PPORT_802_3_OFF(c) \
830 MLX5_BYTE_OFF(ppcnt_reg, \
831 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
832 static const struct counter_desc pport_802_3_stats_desc[] = {
833 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
834 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
835 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
836 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
837 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
838 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
839 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
840 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
841 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
842 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
843 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
844 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
845 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
846 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
847 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
848 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
849 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
850 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
851 };
852
853 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
854
855 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(802_3)
856 {
857 return NUM_PPORT_802_3_COUNTERS;
858 }
859
860 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(802_3)
861 {
862 int i;
863
864 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
865 ethtool_puts(data, pport_802_3_stats_desc[i].format);
866 }
867
868 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3)
869 {
870 int i;
871
872 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
873 mlx5e_ethtool_put_stat(
874 data, MLX5E_READ_CTR64_BE(
875 &priv->stats.pport.IEEE_802_3_counters,
876 pport_802_3_stats_desc, i));
877 }
878
879 #define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \
880 (MLX5_CAP_GEN(mdev, pcam_reg) ? MLX5_CAP_PCAM_REG(mdev, ppcnt) : 1)
881
882 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3)
883 {
884 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
885 struct mlx5_core_dev *mdev = priv->mdev;
886 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
887 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
888 void *out;
889
890 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
891 return;
892
893 MLX5_SET(ppcnt_reg, in, local_port, 1);
894 out = pstats->IEEE_802_3_counters;
895 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
896 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
897 }
898
899 #define MLX5E_READ_CTR64_BE_F(ptr, set, c) \
900 be64_to_cpu(*(__be64 *)((char *)ptr + \
901 MLX5_BYTE_OFF(ppcnt_reg, \
902 counter_set.set.c##_high)))
903
mlx5e_stats_get_ieee(struct mlx5_core_dev * mdev,u32 * ppcnt_ieee_802_3)904 static int mlx5e_stats_get_ieee(struct mlx5_core_dev *mdev,
905 u32 *ppcnt_ieee_802_3)
906 {
907 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
908 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
909
910 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
911 return -EOPNOTSUPP;
912
913 MLX5_SET(ppcnt_reg, in, local_port, 1);
914 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
915 return mlx5_core_access_reg(mdev, in, sz, ppcnt_ieee_802_3,
916 sz, MLX5_REG_PPCNT, 0, 0);
917 }
918
mlx5e_stats_get_per_prio(struct mlx5_core_dev * mdev,u32 * ppcnt_per_prio,int prio)919 static int mlx5e_stats_get_per_prio(struct mlx5_core_dev *mdev,
920 u32 *ppcnt_per_prio, int prio)
921 {
922 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
923 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
924
925 if (!(MLX5_CAP_PCAM_FEATURE(mdev, pfcc_mask) &&
926 MLX5_CAP_DEBUG(mdev, stall_detect)))
927 return -EOPNOTSUPP;
928
929 MLX5_SET(ppcnt_reg, in, local_port, 1);
930 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
931 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
932 return mlx5_core_access_reg(mdev, in, sz, ppcnt_per_prio, sz,
933 MLX5_REG_PPCNT, 0, 0);
934 }
935
mlx5e_stats_pause_get(struct mlx5e_priv * priv,struct ethtool_pause_stats * pause_stats)936 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
937 struct ethtool_pause_stats *pause_stats)
938 {
939 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
940 struct mlx5_core_dev *mdev = priv->mdev;
941 u64 ps_stats = 0;
942 int prio;
943
944 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
945 return;
946
947 pause_stats->tx_pause_frames =
948 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
949 eth_802_3_cntrs_grp_data_layout,
950 a_pause_mac_ctrl_frames_transmitted);
951 pause_stats->rx_pause_frames =
952 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
953 eth_802_3_cntrs_grp_data_layout,
954 a_pause_mac_ctrl_frames_received);
955
956 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
957 if (mlx5e_stats_get_per_prio(mdev, ppcnt_ieee_802_3, prio))
958 return;
959
960 ps_stats += MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
961 eth_per_prio_grp_data_layout,
962 device_stall_critical_watermark_cnt);
963 }
964
965 pause_stats->tx_pause_storm_events = ps_stats;
966 }
967
mlx5e_stats_eth_phy_get(struct mlx5e_priv * priv,struct ethtool_eth_phy_stats * phy_stats)968 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
969 struct ethtool_eth_phy_stats *phy_stats)
970 {
971 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
972 struct mlx5_core_dev *mdev = priv->mdev;
973
974 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
975 return;
976
977 phy_stats->SymbolErrorDuringCarrier =
978 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
979 eth_802_3_cntrs_grp_data_layout,
980 a_symbol_error_during_carrier);
981 }
982
mlx5e_stats_eth_mac_get(struct mlx5e_priv * priv,struct ethtool_eth_mac_stats * mac_stats)983 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
984 struct ethtool_eth_mac_stats *mac_stats)
985 {
986 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
987 struct mlx5_core_dev *mdev = priv->mdev;
988
989 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
990 return;
991
992 #define RD(name) \
993 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3, \
994 eth_802_3_cntrs_grp_data_layout, \
995 name)
996
997 mac_stats->FramesTransmittedOK = RD(a_frames_transmitted_ok);
998 mac_stats->FramesReceivedOK = RD(a_frames_received_ok);
999 mac_stats->FrameCheckSequenceErrors = RD(a_frame_check_sequence_errors);
1000 mac_stats->OctetsTransmittedOK = RD(a_octets_transmitted_ok);
1001 mac_stats->OctetsReceivedOK = RD(a_octets_received_ok);
1002 mac_stats->MulticastFramesXmittedOK = RD(a_multicast_frames_xmitted_ok);
1003 mac_stats->BroadcastFramesXmittedOK = RD(a_broadcast_frames_xmitted_ok);
1004 mac_stats->MulticastFramesReceivedOK = RD(a_multicast_frames_received_ok);
1005 mac_stats->BroadcastFramesReceivedOK = RD(a_broadcast_frames_received_ok);
1006 mac_stats->InRangeLengthErrors = RD(a_in_range_length_errors);
1007 mac_stats->OutOfRangeLengthField = RD(a_out_of_range_length_field);
1008 mac_stats->FrameTooLongErrors = RD(a_frame_too_long_errors);
1009 #undef RD
1010 }
1011
mlx5e_stats_eth_ctrl_get(struct mlx5e_priv * priv,struct ethtool_eth_ctrl_stats * ctrl_stats)1012 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
1013 struct ethtool_eth_ctrl_stats *ctrl_stats)
1014 {
1015 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
1016 struct mlx5_core_dev *mdev = priv->mdev;
1017
1018 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
1019 return;
1020
1021 ctrl_stats->MACControlFramesTransmitted =
1022 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
1023 eth_802_3_cntrs_grp_data_layout,
1024 a_mac_control_frames_transmitted);
1025 ctrl_stats->MACControlFramesReceived =
1026 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
1027 eth_802_3_cntrs_grp_data_layout,
1028 a_mac_control_frames_received);
1029 ctrl_stats->UnsupportedOpcodesReceived =
1030 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
1031 eth_802_3_cntrs_grp_data_layout,
1032 a_unsupported_opcodes_received);
1033 }
1034
1035 #define PPORT_2863_OFF(c) \
1036 MLX5_BYTE_OFF(ppcnt_reg, \
1037 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
1038 static const struct counter_desc pport_2863_stats_desc[] = {
1039 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
1040 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
1041 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
1042 };
1043
1044 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
1045
1046 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2863)
1047 {
1048 return NUM_PPORT_2863_COUNTERS;
1049 }
1050
1051 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2863)
1052 {
1053 int i;
1054
1055 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1056 ethtool_puts(data, pport_2863_stats_desc[i].format);
1057 }
1058
1059 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2863)
1060 {
1061 int i;
1062
1063 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1064 mlx5e_ethtool_put_stat(
1065 data, MLX5E_READ_CTR64_BE(
1066 &priv->stats.pport.RFC_2863_counters,
1067 pport_2863_stats_desc, i));
1068 }
1069
1070 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2863)
1071 {
1072 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1073 struct mlx5_core_dev *mdev = priv->mdev;
1074 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1075 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1076 void *out;
1077
1078 MLX5_SET(ppcnt_reg, in, local_port, 1);
1079 out = pstats->RFC_2863_counters;
1080 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
1081 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1082 }
1083
1084 #define PPORT_2819_OFF(c) \
1085 MLX5_BYTE_OFF(ppcnt_reg, \
1086 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
1087 static const struct counter_desc pport_2819_stats_desc[] = {
1088 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
1089 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
1090 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
1091 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
1092 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
1093 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
1094 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
1095 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
1096 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
1097 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
1098 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
1099 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
1100 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
1101 };
1102
1103 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
1104
1105 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2819)
1106 {
1107 return NUM_PPORT_2819_COUNTERS;
1108 }
1109
1110 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2819)
1111 {
1112 int i;
1113
1114 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1115 ethtool_puts(data, pport_2819_stats_desc[i].format);
1116 }
1117
1118 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2819)
1119 {
1120 int i;
1121
1122 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1123 mlx5e_ethtool_put_stat(
1124 data, MLX5E_READ_CTR64_BE(
1125 &priv->stats.pport.RFC_2819_counters,
1126 pport_2819_stats_desc, i));
1127 }
1128
1129 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2819)
1130 {
1131 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1132 struct mlx5_core_dev *mdev = priv->mdev;
1133 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1134 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1135 void *out;
1136
1137 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
1138 return;
1139
1140 MLX5_SET(ppcnt_reg, in, local_port, 1);
1141 out = pstats->RFC_2819_counters;
1142 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1143 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1144 }
1145
1146 static const struct ethtool_rmon_hist_range mlx5e_rmon_ranges[] = {
1147 { 0, 64 },
1148 { 65, 127 },
1149 { 128, 255 },
1150 { 256, 511 },
1151 { 512, 1023 },
1152 { 1024, 1518 },
1153 { 1519, 2047 },
1154 { 2048, 4095 },
1155 { 4096, 8191 },
1156 { 8192, 10239 },
1157 {}
1158 };
1159
mlx5e_stats_rmon_get(struct mlx5e_priv * priv,struct ethtool_rmon_stats * rmon,const struct ethtool_rmon_hist_range ** ranges)1160 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
1161 struct ethtool_rmon_stats *rmon,
1162 const struct ethtool_rmon_hist_range **ranges)
1163 {
1164 u32 ppcnt_RFC_2819_counters[MLX5_ST_SZ_DW(ppcnt_reg)];
1165 struct mlx5_core_dev *mdev = priv->mdev;
1166 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1167 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1168
1169 MLX5_SET(ppcnt_reg, in, local_port, 1);
1170 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1171 if (mlx5_core_access_reg(mdev, in, sz, ppcnt_RFC_2819_counters,
1172 sz, MLX5_REG_PPCNT, 0, 0))
1173 return;
1174
1175 #define RD(name) \
1176 MLX5E_READ_CTR64_BE_F(ppcnt_RFC_2819_counters, \
1177 eth_2819_cntrs_grp_data_layout, \
1178 name)
1179
1180 rmon->undersize_pkts = RD(ether_stats_undersize_pkts);
1181 rmon->fragments = RD(ether_stats_fragments);
1182 rmon->jabbers = RD(ether_stats_jabbers);
1183
1184 rmon->hist[0] = RD(ether_stats_pkts64octets);
1185 rmon->hist[1] = RD(ether_stats_pkts65to127octets);
1186 rmon->hist[2] = RD(ether_stats_pkts128to255octets);
1187 rmon->hist[3] = RD(ether_stats_pkts256to511octets);
1188 rmon->hist[4] = RD(ether_stats_pkts512to1023octets);
1189 rmon->hist[5] = RD(ether_stats_pkts1024to1518octets);
1190 rmon->hist[6] = RD(ether_stats_pkts1519to2047octets);
1191 rmon->hist[7] = RD(ether_stats_pkts2048to4095octets);
1192 rmon->hist[8] = RD(ether_stats_pkts4096to8191octets);
1193 rmon->hist[9] = RD(ether_stats_pkts8192to10239octets);
1194 #undef RD
1195
1196 *ranges = mlx5e_rmon_ranges;
1197 }
1198
mlx5e_stats_ts_get(struct mlx5e_priv * priv,struct ethtool_ts_stats * ts_stats)1199 void mlx5e_stats_ts_get(struct mlx5e_priv *priv,
1200 struct ethtool_ts_stats *ts_stats)
1201 {
1202 int i, j;
1203
1204 mutex_lock(&priv->state_lock);
1205
1206 if (priv->tx_ptp_opened) {
1207 struct mlx5e_ptp *ptp = priv->channels.ptp;
1208
1209 ts_stats->pkts = 0;
1210 ts_stats->err = 0;
1211 ts_stats->lost = 0;
1212
1213 if (!ptp)
1214 goto out;
1215
1216 /* Aggregate stats across all TCs */
1217 for (i = 0; i < ptp->num_tc; i++) {
1218 struct mlx5e_ptp_cq_stats *stats =
1219 ptp->ptpsq[i].cq_stats;
1220
1221 ts_stats->pkts += stats->cqe;
1222 ts_stats->err += stats->abort + stats->err_cqe +
1223 stats->late_cqe;
1224 ts_stats->lost += stats->lost_cqe;
1225 }
1226 } else {
1227 /* DMA layer will always successfully timestamp packets. Other
1228 * counters do not make sense for this layer.
1229 */
1230 ts_stats->pkts = 0;
1231
1232 /* Aggregate stats across all SQs */
1233 for (j = 0; j < priv->channels.num; j++) {
1234 struct mlx5e_channel *c = priv->channels.c[j];
1235
1236 for (i = 0; i < c->num_tc; i++) {
1237 struct mlx5e_sq_stats *stats = c->sq[i].stats;
1238
1239 ts_stats->pkts += stats->timestamps;
1240 }
1241 }
1242 }
1243
1244 out:
1245 mutex_unlock(&priv->state_lock);
1246 }
1247
1248 #define PPORT_PHY_LAYER_OFF(c) \
1249 MLX5_BYTE_OFF(ppcnt_reg, \
1250 counter_set.phys_layer_cntrs.c)
1251 static const struct counter_desc pport_phy_layer_cntrs_stats_desc[] = {
1252 { "link_down_events_phy", PPORT_PHY_LAYER_OFF(link_down_events) }
1253 };
1254
1255 #define PPORT_PHY_STATISTICAL_OFF(c) \
1256 MLX5_BYTE_OFF(ppcnt_reg, \
1257 counter_set.phys_layer_statistical_cntrs.c##_high)
1258 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
1259 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
1260 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
1261 };
1262
1263 static const struct counter_desc
1264 pport_phy_statistical_err_lanes_stats_desc[] = {
1265 { "rx_err_lane_0_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane0) },
1266 { "rx_err_lane_1_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane1) },
1267 { "rx_err_lane_2_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane2) },
1268 { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) },
1269 };
1270
1271 #define PPORT_PHY_RECOVERY_OFF(c) \
1272 MLX5_BYTE_OFF(ppcnt_reg, counter_set.phys_layer_recovery_cntrs.c)
1273 static const struct counter_desc
1274 pport_phy_recovery_cntrs_stats_desc[] = {
1275 { "total_success_recovery_phy",
1276 PPORT_PHY_RECOVERY_OFF(total_successful_recovery_events) }
1277 };
1278
1279 #define NUM_PPORT_PHY_LAYER_COUNTERS \
1280 ARRAY_SIZE(pport_phy_layer_cntrs_stats_desc)
1281 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \
1282 ARRAY_SIZE(pport_phy_statistical_stats_desc)
1283 #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \
1284 ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc)
1285 #define NUM_PPORT_PHY_RECOVERY_COUNTERS \
1286 ARRAY_SIZE(pport_phy_recovery_cntrs_stats_desc)
1287
1288 #define NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(dev) \
1289 (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_statistical_group) ? \
1290 NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0)
1291 #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(dev) \
1292 (MLX5_CAP_PCAM_FEATURE(dev, per_lane_error_counters) ? \
1293 NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0)
1294 #define NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(dev) \
1295 (MLX5_CAP_PCAM_FEATURE(dev, ppcnt_recovery_counters) ? \
1296 NUM_PPORT_PHY_RECOVERY_COUNTERS : 0)
1297
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy)1298 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy)
1299 {
1300 struct mlx5_core_dev *mdev = priv->mdev;
1301 int num_stats;
1302
1303 num_stats = NUM_PPORT_PHY_LAYER_COUNTERS;
1304
1305 num_stats += NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev);
1306
1307 num_stats += NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev);
1308
1309 num_stats += NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev);
1310 return num_stats;
1311 }
1312
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy)1313 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy)
1314 {
1315 struct mlx5_core_dev *mdev = priv->mdev;
1316 int i;
1317
1318 for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++)
1319 ethtool_puts(data, pport_phy_layer_cntrs_stats_desc[i].format);
1320
1321 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++)
1322 ethtool_puts(data, pport_phy_statistical_stats_desc[i].format);
1323
1324 for (i = 0;
1325 i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev);
1326 i++)
1327 ethtool_puts(data,
1328 pport_phy_statistical_err_lanes_stats_desc[i]
1329 .format);
1330
1331 for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++)
1332 ethtool_puts(data,
1333 pport_phy_recovery_cntrs_stats_desc[i].format);
1334 }
1335
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy)1336 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy)
1337 {
1338 struct mlx5_core_dev *mdev = priv->mdev;
1339 int i;
1340
1341 for (i = 0; i < NUM_PPORT_PHY_LAYER_COUNTERS; i++)
1342 mlx5e_ethtool_put_stat(
1343 data,
1344 MLX5E_READ_CTR32_BE(&priv->stats.pport
1345 .phy_counters,
1346 pport_phy_layer_cntrs_stats_desc, i));
1347
1348 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_LOOPBACK_COUNTERS(mdev); i++)
1349 mlx5e_ethtool_put_stat(
1350 data,
1351 MLX5E_READ_CTR64_BE(
1352 &priv->stats.pport.phy_statistical_counters,
1353 pport_phy_statistical_stats_desc, i));
1354
1355 for (i = 0;
1356 i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_LOOPBACK_COUNTERS(mdev);
1357 i++)
1358 mlx5e_ethtool_put_stat(
1359 data,
1360 MLX5E_READ_CTR64_BE(
1361 &priv->stats.pport.phy_statistical_counters,
1362 pport_phy_statistical_err_lanes_stats_desc, i));
1363
1364 for (i = 0; i < NUM_PPORT_PHY_RECOVERY_LOOPBACK_COUNTERS(mdev); i++)
1365 mlx5e_ethtool_put_stat(
1366 data,
1367 MLX5E_READ_CTR32_BE(
1368 &priv->stats.pport.phy_recovery_counters,
1369 pport_phy_recovery_cntrs_stats_desc, i));
1370 }
1371
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)1372 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
1373 {
1374 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1375 struct mlx5_core_dev *mdev = priv->mdev;
1376 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1377 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1378 void *out;
1379
1380 MLX5_SET(ppcnt_reg, in, local_port, 1);
1381 out = pstats->phy_counters;
1382 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1383 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1384
1385 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
1386 out = pstats->phy_statistical_counters;
1387 MLX5_SET(ppcnt_reg, in, grp,
1388 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1389 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0,
1390 0);
1391 }
1392
1393 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_recovery_counters)) {
1394 out = pstats->phy_recovery_counters;
1395 MLX5_SET(ppcnt_reg, in, grp,
1396 MLX5_PHYSICAL_LAYER_RECOVERY_GROUP);
1397 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0,
1398 0);
1399 }
1400 }
1401
mlx5e_get_link_ext_stats(struct net_device * dev,struct ethtool_link_ext_stats * stats)1402 void mlx5e_get_link_ext_stats(struct net_device *dev,
1403 struct ethtool_link_ext_stats *stats)
1404 {
1405 struct mlx5e_priv *priv = netdev_priv(dev);
1406 u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1407 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1408 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1409
1410 MLX5_SET(ppcnt_reg, in, local_port, 1);
1411 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1412 mlx5_core_access_reg(priv->mdev, in, sz, out,
1413 MLX5_ST_SZ_BYTES(ppcnt_reg), MLX5_REG_PPCNT, 0, 0);
1414
1415 stats->link_down_events = MLX5_GET(ppcnt_reg, out,
1416 counter_set.phys_layer_cntrs.link_down_events);
1417 }
1418
fec_num_lanes(struct mlx5_core_dev * dev)1419 static int fec_num_lanes(struct mlx5_core_dev *dev)
1420 {
1421 u32 out[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1422 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1423 int err;
1424
1425 MLX5_SET(pmlp_reg, in, local_port, 1);
1426 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
1427 MLX5_REG_PMLP, 0, 0);
1428 if (err)
1429 return 0;
1430
1431 return MLX5_GET(pmlp_reg, out, width);
1432 }
1433
fec_active_mode(struct mlx5_core_dev * mdev)1434 static int fec_active_mode(struct mlx5_core_dev *mdev)
1435 {
1436 unsigned long fec_active_long;
1437 u32 fec_active;
1438
1439 if (mlx5e_get_fec_mode(mdev, &fec_active, NULL))
1440 return MLX5E_FEC_NOFEC;
1441
1442 fec_active_long = fec_active;
1443 return find_first_bit(&fec_active_long, sizeof(unsigned long) * BITS_PER_BYTE);
1444 }
1445
1446 #define MLX5E_STATS_SET_FEC_BLOCK(idx) ({ \
1447 fec_stats->corrected_blocks.lanes[(idx)] = \
1448 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
1449 fc_fec_corrected_blocks_lane##idx); \
1450 fec_stats->uncorrectable_blocks.lanes[(idx)] = \
1451 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
1452 fc_fec_uncorrectable_blocks_lane##idx); \
1453 })
1454
fec_set_fc_stats(struct ethtool_fec_stats * fec_stats,u32 * ppcnt,u8 lanes)1455 static void fec_set_fc_stats(struct ethtool_fec_stats *fec_stats,
1456 u32 *ppcnt, u8 lanes)
1457 {
1458 if (lanes > 3) { /* 4 lanes */
1459 MLX5E_STATS_SET_FEC_BLOCK(3);
1460 MLX5E_STATS_SET_FEC_BLOCK(2);
1461 }
1462 if (lanes > 1) /* 2 lanes */
1463 MLX5E_STATS_SET_FEC_BLOCK(1);
1464 if (lanes > 0) /* 1 lane */
1465 MLX5E_STATS_SET_FEC_BLOCK(0);
1466 }
1467
fec_set_rs_stats(struct ethtool_fec_stats * fec_stats,u32 * ppcnt)1468 static void fec_set_rs_stats(struct ethtool_fec_stats *fec_stats, u32 *ppcnt)
1469 {
1470 fec_stats->corrected_blocks.total =
1471 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
1472 rs_fec_corrected_blocks);
1473 fec_stats->uncorrectable_blocks.total =
1474 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
1475 rs_fec_uncorrectable_blocks);
1476 }
1477
fec_set_block_stats(struct mlx5e_priv * priv,int mode,struct ethtool_fec_stats * fec_stats)1478 static void fec_set_block_stats(struct mlx5e_priv *priv,
1479 int mode,
1480 struct ethtool_fec_stats *fec_stats)
1481 {
1482 struct mlx5_core_dev *mdev = priv->mdev;
1483 u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1484 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1485 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1486
1487 MLX5_SET(ppcnt_reg, in, local_port, 1);
1488 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1489 if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
1490 return;
1491
1492 switch (mode) {
1493 case MLX5E_FEC_RS_528_514:
1494 case MLX5E_FEC_RS_544_514:
1495 case MLX5E_FEC_LLRS_272_257_1:
1496 case MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD:
1497 fec_set_rs_stats(fec_stats, out);
1498 return;
1499 case MLX5E_FEC_FIRECODE:
1500 fec_set_fc_stats(fec_stats, out, fec_num_lanes(mdev));
1501 }
1502 }
1503
fec_set_corrected_bits_total(struct mlx5e_priv * priv,struct ethtool_fec_stats * fec_stats)1504 static void fec_set_corrected_bits_total(struct mlx5e_priv *priv,
1505 struct ethtool_fec_stats *fec_stats)
1506 {
1507 u32 ppcnt_phy_statistical[MLX5_ST_SZ_DW(ppcnt_reg)];
1508 struct mlx5_core_dev *mdev = priv->mdev;
1509 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1510 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1511
1512 MLX5_SET(ppcnt_reg, in, local_port, 1);
1513 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1514 if (mlx5_core_access_reg(mdev, in, sz, ppcnt_phy_statistical,
1515 sz, MLX5_REG_PPCNT, 0, 0))
1516 return;
1517
1518 fec_stats->corrected_bits.total =
1519 MLX5E_READ_CTR64_BE_F(ppcnt_phy_statistical,
1520 phys_layer_statistical_cntrs,
1521 phy_corrected_bits);
1522 }
1523
1524 #define MLX5_RS_HISTOGRAM_ENTRIES \
1525 (MLX5_FLD_SZ_BYTES(rs_histogram_cntrs, hist) / \
1526 MLX5_FLD_SZ_BYTES(rs_histogram_cntrs, hist[0]))
1527
1528 enum {
1529 MLX5E_HISTOGRAM_FEC_RS_544_514 = 1,
1530 MLX5E_HISTOGRAM_FEC_LLRS = 2,
1531 MLX5E_HISTOGRAM_FEC_RS_528_514 = 3,
1532 };
1533
fec_rs_validate_hist_type(int mode,int hist_type)1534 static bool fec_rs_validate_hist_type(int mode, int hist_type)
1535 {
1536 switch (mode) {
1537 case MLX5E_FEC_RS_528_514:
1538 return hist_type == MLX5E_HISTOGRAM_FEC_RS_528_514;
1539 case MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD:
1540 case MLX5E_FEC_RS_544_514:
1541 return hist_type == MLX5E_HISTOGRAM_FEC_RS_544_514;
1542 case MLX5E_FEC_LLRS_272_257_1:
1543 return hist_type == MLX5E_HISTOGRAM_FEC_LLRS;
1544 default:
1545 break;
1546 }
1547
1548 return false;
1549 }
1550
1551 static u8
fec_rs_histogram_fill_ranges(struct mlx5e_priv * priv,int mode,struct ethtool_fec_hist_range * ranges)1552 fec_rs_histogram_fill_ranges(struct mlx5e_priv *priv, int mode,
1553 struct ethtool_fec_hist_range *ranges)
1554 {
1555 struct mlx5_core_dev *mdev = priv->mdev;
1556 u32 out[MLX5_ST_SZ_DW(pphcr_reg)] = {0};
1557 u32 in[MLX5_ST_SZ_DW(pphcr_reg)] = {0};
1558 int sz = MLX5_ST_SZ_BYTES(pphcr_reg);
1559 u8 hist_type, num_of_bins;
1560
1561 MLX5_SET(pphcr_reg, in, local_port, 1);
1562 if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPHCR, 0, 0))
1563 return 0;
1564
1565 hist_type = MLX5_GET(pphcr_reg, out, active_hist_type);
1566 if (!fec_rs_validate_hist_type(mode, hist_type))
1567 return 0;
1568
1569 num_of_bins = MLX5_GET(pphcr_reg, out, num_of_bins);
1570 if (WARN_ON_ONCE(num_of_bins > MLX5_RS_HISTOGRAM_ENTRIES))
1571 return 0;
1572
1573 for (int i = 0; i < num_of_bins; i++) {
1574 void *bin_range = MLX5_ADDR_OF(pphcr_reg, out, bin_range[i]);
1575
1576 ranges[i].high = MLX5_GET(bin_range_layout, bin_range,
1577 high_val);
1578 ranges[i].low = MLX5_GET(bin_range_layout, bin_range,
1579 low_val);
1580 }
1581
1582 return num_of_bins;
1583 }
1584
fec_rs_histogram_fill_stats(struct mlx5e_priv * priv,u8 num_of_bins,struct ethtool_fec_hist * hist)1585 static void fec_rs_histogram_fill_stats(struct mlx5e_priv *priv,
1586 u8 num_of_bins,
1587 struct ethtool_fec_hist *hist)
1588 {
1589 struct mlx5_core_dev *mdev = priv->mdev;
1590 u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1591 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1592 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1593 void *rs_histogram_cntrs;
1594
1595 MLX5_SET(ppcnt_reg, in, local_port, 1);
1596 MLX5_SET(ppcnt_reg, in, grp, MLX5_RS_FEC_HISTOGRAM_GROUP);
1597 if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
1598 return;
1599
1600 rs_histogram_cntrs = MLX5_ADDR_OF(ppcnt_reg, out,
1601 counter_set.rs_histogram_cntrs);
1602 /* Guaranteed that num_of_bins is less than MLX5E_FEC_RS_HIST_MAX
1603 * by fec_rs_histogram_fill_ranges().
1604 */
1605 for (int i = 0; i < num_of_bins; i++)
1606 hist->values[i].sum = MLX5_GET64(rs_histogram_cntrs,
1607 rs_histogram_cntrs,
1608 hist[i]);
1609 }
1610
fec_set_histograms_stats(struct mlx5e_priv * priv,int mode,struct ethtool_fec_hist * hist)1611 static void fec_set_histograms_stats(struct mlx5e_priv *priv, int mode,
1612 struct ethtool_fec_hist *hist)
1613 {
1614 u8 num_of_bins;
1615
1616 switch (mode) {
1617 case MLX5E_FEC_RS_528_514:
1618 case MLX5E_FEC_RS_544_514:
1619 case MLX5E_FEC_LLRS_272_257_1:
1620 case MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD:
1621 num_of_bins =
1622 fec_rs_histogram_fill_ranges(priv, mode, hist->ranges_buf);
1623 if (num_of_bins) {
1624 hist->ranges = hist->ranges_buf;
1625 return fec_rs_histogram_fill_stats(priv, num_of_bins,
1626 hist);
1627 }
1628 break;
1629 default:
1630 return;
1631 }
1632 }
1633
mlx5e_stats_fec_get(struct mlx5e_priv * priv,struct ethtool_fec_stats * fec_stats,struct ethtool_fec_hist * hist)1634 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
1635 struct ethtool_fec_stats *fec_stats,
1636 struct ethtool_fec_hist *hist)
1637 {
1638 int mode = fec_active_mode(priv->mdev);
1639
1640 if (mode == MLX5E_FEC_NOFEC)
1641 return;
1642
1643 if (MLX5_CAP_PCAM_FEATURE(priv->mdev, ppcnt_statistical_group)) {
1644 fec_set_corrected_bits_total(priv, fec_stats);
1645 fec_set_block_stats(priv, mode, fec_stats);
1646 }
1647
1648 if (MLX5_CAP_PCAM_REG(priv->mdev, pphcr))
1649 fec_set_histograms_stats(priv, mode, hist);
1650 }
1651
1652 #define PPORT_ETH_EXT_OFF(c) \
1653 MLX5_BYTE_OFF(ppcnt_reg, \
1654 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
1655 static const struct counter_desc pport_eth_ext_stats_desc[] = {
1656 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
1657 };
1658
1659 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
1660
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(eth_ext)1661 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(eth_ext)
1662 {
1663 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1664 return NUM_PPORT_ETH_EXT_COUNTERS;
1665
1666 return 0;
1667 }
1668
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(eth_ext)1669 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(eth_ext)
1670 {
1671 int i;
1672
1673 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1674 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1675 ethtool_puts(data, pport_eth_ext_stats_desc[i].format);
1676 }
1677
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext)1678 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext)
1679 {
1680 int i;
1681
1682 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1683 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1684 mlx5e_ethtool_put_stat(
1685 data,
1686 MLX5E_READ_CTR64_BE(
1687 &priv->stats.pport.eth_ext_counters,
1688 pport_eth_ext_stats_desc, i));
1689 }
1690
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext)1691 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext)
1692 {
1693 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1694 struct mlx5_core_dev *mdev = priv->mdev;
1695 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1696 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1697 void *out;
1698
1699 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
1700 return;
1701
1702 MLX5_SET(ppcnt_reg, in, local_port, 1);
1703 out = pstats->eth_ext_counters;
1704 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
1705 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1706 }
1707
1708 #define PCIE_PERF_OFF(c) \
1709 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
1710 static const struct counter_desc pcie_perf_stats_desc[] = {
1711 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
1712 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
1713 };
1714
1715 #define PCIE_PERF_OFF64(c) \
1716 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
1717 static const struct counter_desc pcie_perf_stats_desc64[] = {
1718 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
1719 };
1720
1721 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
1722 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
1723 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
1724 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
1725 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
1726 };
1727
1728 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
1729 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
1730 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
1731
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie)1732 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie)
1733 {
1734 int num_stats = 0;
1735
1736 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1737 num_stats += NUM_PCIE_PERF_COUNTERS;
1738
1739 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1740 num_stats += NUM_PCIE_PERF_COUNTERS64;
1741
1742 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1743 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
1744
1745 return num_stats;
1746 }
1747
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie)1748 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie)
1749 {
1750 int i;
1751
1752 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1753 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1754 ethtool_puts(data, pcie_perf_stats_desc[i].format);
1755
1756 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1757 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1758 ethtool_puts(data, pcie_perf_stats_desc64[i].format);
1759
1760 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1761 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1762 ethtool_puts(data,
1763 pcie_perf_stall_stats_desc[i].format);
1764 }
1765
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie)1766 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie)
1767 {
1768 int i;
1769
1770 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1771 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1772 mlx5e_ethtool_put_stat(
1773 data,
1774 MLX5E_READ_CTR32_BE(
1775 &priv->stats.pcie.pcie_perf_counters,
1776 pcie_perf_stats_desc, i));
1777
1778 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1779 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1780 mlx5e_ethtool_put_stat(
1781 data,
1782 MLX5E_READ_CTR64_BE(
1783 &priv->stats.pcie.pcie_perf_counters,
1784 pcie_perf_stats_desc64, i));
1785
1786 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1787 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1788 mlx5e_ethtool_put_stat(
1789 data,
1790 MLX5E_READ_CTR32_BE(
1791 &priv->stats.pcie.pcie_perf_counters,
1792 pcie_perf_stall_stats_desc, i));
1793 }
1794
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie)1795 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie)
1796 {
1797 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
1798 struct mlx5_core_dev *mdev = priv->mdev;
1799 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
1800 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
1801 void *out;
1802
1803 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
1804 return;
1805
1806 out = pcie_stats->pcie_perf_counters;
1807 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
1808 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
1809 }
1810
1811 #define PPORT_PER_TC_PRIO_OFF(c) \
1812 MLX5_BYTE_OFF(ppcnt_reg, \
1813 counter_set.eth_per_tc_prio_grp_data_layout.c##_high)
1814
1815 static const struct counter_desc pport_per_tc_prio_stats_desc[] = {
1816 { "rx_prio%d_buf_discard", PPORT_PER_TC_PRIO_OFF(no_buffer_discard_uc) },
1817 };
1818
1819 #define NUM_PPORT_PER_TC_PRIO_COUNTERS ARRAY_SIZE(pport_per_tc_prio_stats_desc)
1820
1821 #define PPORT_PER_TC_CONGEST_PRIO_OFF(c) \
1822 MLX5_BYTE_OFF(ppcnt_reg, \
1823 counter_set.eth_per_tc_congest_prio_grp_data_layout.c##_high)
1824
1825 static const struct counter_desc pport_per_tc_congest_prio_stats_desc[] = {
1826 { "rx_prio%d_cong_discard", PPORT_PER_TC_CONGEST_PRIO_OFF(wred_discard) },
1827 { "rx_prio%d_marked", PPORT_PER_TC_CONGEST_PRIO_OFF(ecn_marked_tc) },
1828 };
1829
1830 #define NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS \
1831 ARRAY_SIZE(pport_per_tc_congest_prio_stats_desc)
1832
mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv * priv)1833 static int mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv *priv)
1834 {
1835 struct mlx5_core_dev *mdev = priv->mdev;
1836
1837 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1838 return 0;
1839
1840 return NUM_PPORT_PER_TC_PRIO_COUNTERS * NUM_PPORT_PRIO;
1841 }
1842
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_port_buff_congest)1843 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_port_buff_congest)
1844 {
1845 struct mlx5_core_dev *mdev = priv->mdev;
1846 int i, prio;
1847
1848 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1849 return;
1850
1851 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1852 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1853 ethtool_sprintf(data,
1854 pport_per_tc_prio_stats_desc[i].format,
1855 prio);
1856 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++)
1857 ethtool_sprintf(data,
1858 pport_per_tc_congest_prio_stats_desc[i].format,
1859 prio);
1860 }
1861 }
1862
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest)1863 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest)
1864 {
1865 struct mlx5e_pport_stats *pport = &priv->stats.pport;
1866 struct mlx5_core_dev *mdev = priv->mdev;
1867 int i, prio;
1868
1869 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1870 return;
1871
1872 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1873 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1874 mlx5e_ethtool_put_stat(
1875 data,
1876 MLX5E_READ_CTR64_BE(
1877 &pport->per_tc_prio_counters[prio],
1878 pport_per_tc_prio_stats_desc, i));
1879 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++)
1880 mlx5e_ethtool_put_stat(
1881 data,
1882 MLX5E_READ_CTR64_BE(
1883 &pport->per_tc_congest_prio_counters
1884 [prio],
1885 pport_per_tc_congest_prio_stats_desc,
1886 i));
1887 }
1888 }
1889
mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv * priv)1890 static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv)
1891 {
1892 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1893 struct mlx5_core_dev *mdev = priv->mdev;
1894 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1895 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1896 void *out;
1897 int prio;
1898
1899 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1900 return;
1901
1902 MLX5_SET(ppcnt_reg, in, pnat, 2);
1903 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP);
1904 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1905 out = pstats->per_tc_prio_counters[prio];
1906 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1907 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1908 }
1909 }
1910
mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv * priv)1911 static int mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv *priv)
1912 {
1913 struct mlx5_core_dev *mdev = priv->mdev;
1914
1915 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1916 return 0;
1917
1918 return NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS * NUM_PPORT_PRIO;
1919 }
1920
mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv * priv)1921 static void mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv *priv)
1922 {
1923 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1924 struct mlx5_core_dev *mdev = priv->mdev;
1925 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1926 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1927 void *out;
1928 int prio;
1929
1930 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1931 return;
1932
1933 MLX5_SET(ppcnt_reg, in, pnat, 2);
1934 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP);
1935 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1936 out = pstats->per_tc_congest_prio_counters[prio];
1937 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1938 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1939 }
1940 }
1941
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_port_buff_congest)1942 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_port_buff_congest)
1943 {
1944 return mlx5e_grp_per_tc_prio_get_num_stats(priv) +
1945 mlx5e_grp_per_tc_congest_prio_get_num_stats(priv);
1946 }
1947
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_port_buff_congest)1948 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_port_buff_congest)
1949 {
1950 mlx5e_grp_per_tc_prio_update_stats(priv);
1951 mlx5e_grp_per_tc_congest_prio_update_stats(priv);
1952 }
1953
1954 #define PPORT_PER_PRIO_OFF(c) \
1955 MLX5_BYTE_OFF(ppcnt_reg, \
1956 counter_set.eth_per_prio_grp_data_layout.c##_high)
1957 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
1958 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
1959 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
1960 { "rx_prio%d_discards", PPORT_PER_PRIO_OFF(rx_discards) },
1961 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
1962 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
1963 };
1964
1965 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
1966
mlx5e_grp_per_prio_traffic_get_num_stats(void)1967 static int mlx5e_grp_per_prio_traffic_get_num_stats(void)
1968 {
1969 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
1970 }
1971
mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv * priv,u8 ** data)1972 static void mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
1973 u8 **data)
1974 {
1975 int i, prio;
1976
1977 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1978 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1979 ethtool_sprintf(data,
1980 pport_per_prio_traffic_stats_desc[i].format,
1981 prio);
1982 }
1983 }
1984
mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv * priv,u64 ** data)1985 static void mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
1986 u64 **data)
1987 {
1988 int i, prio;
1989
1990 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1991 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1992 mlx5e_ethtool_put_stat(
1993 data,
1994 MLX5E_READ_CTR64_BE(
1995 &priv->stats.pport
1996 .per_prio_counters[prio],
1997 pport_per_prio_traffic_stats_desc, i));
1998 }
1999 }
2000
2001 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
2002 /* %s is "global" or "prio{i}" */
2003 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
2004 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
2005 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
2006 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
2007 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
2008 };
2009
2010 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
2011 { "tx_pause_storm_warning_events", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
2012 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
2013 };
2014
2015 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
2016 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
2017 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
2018 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
2019
mlx5e_query_pfc_combined(struct mlx5e_priv * priv)2020 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
2021 {
2022 struct mlx5_core_dev *mdev = priv->mdev;
2023 u8 pfc_en_tx;
2024 u8 pfc_en_rx;
2025 int err;
2026
2027 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2028 return 0;
2029
2030 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
2031
2032 return err ? 0 : pfc_en_tx | pfc_en_rx;
2033 }
2034
mlx5e_query_global_pause_combined(struct mlx5e_priv * priv)2035 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
2036 {
2037 struct mlx5_core_dev *mdev = priv->mdev;
2038 u32 rx_pause;
2039 u32 tx_pause;
2040 int err;
2041
2042 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2043 return false;
2044
2045 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
2046
2047 return err ? false : rx_pause | tx_pause;
2048 }
2049
mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv * priv)2050 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
2051 {
2052 return (mlx5e_query_global_pause_combined(priv) +
2053 hweight8(mlx5e_query_pfc_combined(priv))) *
2054 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
2055 NUM_PPORT_PFC_STALL_COUNTERS(priv);
2056 }
2057
mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv * priv,u8 ** data)2058 static void mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
2059 u8 **data)
2060 {
2061 unsigned long pfc_combined;
2062 int i, prio;
2063
2064 pfc_combined = mlx5e_query_pfc_combined(priv);
2065 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
2066 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
2067 char pfc_string[ETH_GSTRING_LEN];
2068
2069 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
2070 ethtool_sprintf(data,
2071 pport_per_prio_pfc_stats_desc[i].format,
2072 pfc_string);
2073 }
2074 }
2075
2076 if (mlx5e_query_global_pause_combined(priv)) {
2077 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
2078 ethtool_sprintf(data,
2079 pport_per_prio_pfc_stats_desc[i].format,
2080 "global");
2081 }
2082 }
2083
2084 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
2085 ethtool_puts(data, pport_pfc_stall_stats_desc[i].format);
2086 }
2087
mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv * priv,u64 ** data)2088 static void mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
2089 u64 **data)
2090 {
2091 unsigned long pfc_combined;
2092 int i, prio;
2093
2094 pfc_combined = mlx5e_query_pfc_combined(priv);
2095 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
2096 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
2097 mlx5e_ethtool_put_stat(
2098 data,
2099 MLX5E_READ_CTR64_BE(
2100 &priv->stats.pport
2101 .per_prio_counters[prio],
2102 pport_per_prio_pfc_stats_desc, i));
2103 }
2104 }
2105
2106 if (mlx5e_query_global_pause_combined(priv)) {
2107 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
2108 mlx5e_ethtool_put_stat(
2109 data,
2110 MLX5E_READ_CTR64_BE(
2111 &priv->stats.pport.per_prio_counters[0],
2112 pport_per_prio_pfc_stats_desc, i));
2113 }
2114 }
2115
2116 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
2117 mlx5e_ethtool_put_stat(
2118 data, MLX5E_READ_CTR64_BE(
2119 &priv->stats.pport.per_prio_counters[0],
2120 pport_pfc_stall_stats_desc, i));
2121 }
2122
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio)2123 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio)
2124 {
2125 return mlx5e_grp_per_prio_traffic_get_num_stats() +
2126 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
2127 }
2128
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio)2129 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio)
2130 {
2131 mlx5e_grp_per_prio_traffic_fill_strings(priv, data);
2132 mlx5e_grp_per_prio_pfc_fill_strings(priv, data);
2133 }
2134
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio)2135 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio)
2136 {
2137 mlx5e_grp_per_prio_traffic_fill_stats(priv, data);
2138 mlx5e_grp_per_prio_pfc_fill_stats(priv, data);
2139 }
2140
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio)2141 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio)
2142 {
2143 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2144 struct mlx5_core_dev *mdev = priv->mdev;
2145 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
2146 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
2147 int prio;
2148 void *out;
2149
2150 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
2151 return;
2152
2153 MLX5_SET(ppcnt_reg, in, local_port, 1);
2154 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
2155 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
2156 out = pstats->per_prio_counters[prio];
2157 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
2158 mlx5_core_access_reg(mdev, in, sz, out, sz,
2159 MLX5_REG_PPCNT, 0, 0);
2160 }
2161 }
2162
2163 static const struct counter_desc mlx5e_pme_status_desc[] = {
2164 { "module_unplug", sizeof(u64) * MLX5_MODULE_STATUS_UNPLUGGED },
2165 };
2166
2167 static const struct counter_desc mlx5e_pme_error_desc[] = {
2168 { "module_bus_stuck", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BUS_STUCK },
2169 { "module_high_temp", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE },
2170 { "module_bad_shorted", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BAD_CABLE },
2171 };
2172
2173 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
2174 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
2175
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pme)2176 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pme)
2177 {
2178 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
2179 }
2180
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pme)2181 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pme)
2182 {
2183 int i;
2184
2185 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
2186 ethtool_puts(data, mlx5e_pme_status_desc[i].format);
2187
2188 for (i = 0; i < NUM_PME_ERR_STATS; i++)
2189 ethtool_puts(data, mlx5e_pme_error_desc[i].format);
2190 }
2191
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme)2192 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme)
2193 {
2194 struct mlx5_pme_stats pme_stats;
2195 int i;
2196
2197 mlx5_get_pme_stats(priv->mdev, &pme_stats);
2198
2199 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
2200 mlx5e_ethtool_put_stat(
2201 data, MLX5E_READ_CTR64_CPU(pme_stats.status_counters,
2202 mlx5e_pme_status_desc, i));
2203
2204 for (i = 0; i < NUM_PME_ERR_STATS; i++)
2205 mlx5e_ethtool_put_stat(
2206 data, MLX5E_READ_CTR64_CPU(pme_stats.error_counters,
2207 mlx5e_pme_error_desc, i));
2208 }
2209
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme)2210 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme) { return; }
2211
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(tls)2212 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(tls)
2213 {
2214 return mlx5e_ktls_get_count(priv);
2215 }
2216
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls)2217 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls)
2218 {
2219 mlx5e_ktls_get_strings(priv, data);
2220 }
2221
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls)2222 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls)
2223 {
2224 mlx5e_ktls_get_stats(priv, data);
2225 }
2226
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls)2227 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls) { return; }
2228
2229 static const struct counter_desc rq_stats_desc[] = {
2230 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
2231 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
2232 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
2233 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
2234 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
2235 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
2236 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2237 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
2238 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
2239 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2240 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
2241 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
2242 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_packets) },
2243 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_bytes) },
2244 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_skbs) },
2245 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_large_hds) },
2246 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, hds_nodata_packets) },
2247 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, hds_nodata_bytes) },
2248 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, hds_nosplit_packets) },
2249 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, hds_nosplit_bytes) },
2250 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) },
2251 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2252 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
2253 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2254 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2255 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2256 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2257 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2258 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2259 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
2260 #ifdef CONFIG_MLX5_EN_ARFS
2261 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_add) },
2262 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_in) },
2263 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_out) },
2264 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_expired) },
2265 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) },
2266 #endif
2267 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) },
2268 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_fast) },
2269 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_slow) },
2270 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_slow_high_order) },
2271 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_empty) },
2272 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_refill) },
2273 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_waive) },
2274 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_cached) },
2275 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_cache_full) },
2276 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring) },
2277 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring_full) },
2278 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_released_ref) },
2279 #ifdef CONFIG_MLX5_EN_TLS
2280 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_packets) },
2281 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_bytes) },
2282 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_pkt) },
2283 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_start) },
2284 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_end) },
2285 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_skip) },
2286 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_ok) },
2287 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_retry) },
2288 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_skip) },
2289 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_err) },
2290 #endif
2291 };
2292
2293 static const struct counter_desc sq_stats_desc[] = {
2294 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
2295 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
2296 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
2297 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
2298 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
2299 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
2300 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2301 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2302 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2303 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
2304 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, timestamps) },
2305 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, mpwqe_blks) },
2306 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, mpwqe_pkts) },
2307 #ifdef CONFIG_MLX5_EN_TLS
2308 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) },
2309 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) },
2310 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ooo) },
2311 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) },
2312 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) },
2313 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) },
2314 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) },
2315 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) },
2316 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) },
2317 #endif
2318 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2319 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
2320 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
2321 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2322 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
2323 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
2324 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
2325 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2326 };
2327
2328 static const struct counter_desc rq_xdpsq_stats_desc[] = {
2329 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2330 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2331 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2332 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
2333 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2334 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2335 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2336 };
2337
2338 static const struct counter_desc xdpsq_stats_desc[] = {
2339 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2340 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2341 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2342 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
2343 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2344 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2345 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2346 };
2347
2348 static const struct counter_desc xskrq_stats_desc[] = {
2349 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, packets) },
2350 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, bytes) },
2351 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_complete) },
2352 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
2353 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2354 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_none) },
2355 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, ecn_mark) },
2356 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2357 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_drop) },
2358 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2359 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, wqe_err) },
2360 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2361 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2362 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2363 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2364 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2365 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2366 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) },
2367 };
2368
2369 static const struct counter_desc xsksq_stats_desc[] = {
2370 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2371 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2372 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2373 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2374 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2375 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2376 };
2377
2378 static const struct counter_desc ch_stats_desc[] = {
2379 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
2380 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
2381 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
2382 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
2383 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, force_irq) },
2384 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
2385 };
2386
2387 static const struct counter_desc ptp_sq_stats_desc[] = {
2388 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, packets) },
2389 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, bytes) },
2390 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2391 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2392 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2393 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, nop) },
2394 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2395 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, stopped) },
2396 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, dropped) },
2397 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2398 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, recover) },
2399 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, cqes) },
2400 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, wake) },
2401 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2402 };
2403
2404 static const struct counter_desc ptp_ch_stats_desc[] = {
2405 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, events) },
2406 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, poll) },
2407 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, arm) },
2408 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
2409 };
2410
2411 static const struct counter_desc ptp_cq_stats_desc[] = {
2412 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, cqe) },
2413 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, err_cqe) },
2414 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, abort) },
2415 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, abort_abs_diff_ns) },
2416 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, late_cqe) },
2417 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, lost_cqe) },
2418 };
2419
2420 static const struct counter_desc ptp_rq_stats_desc[] = {
2421 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, packets) },
2422 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, bytes) },
2423 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete) },
2424 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
2425 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
2426 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
2427 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2428 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_none) },
2429 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, xdp_drop) },
2430 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2431 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, lro_packets) },
2432 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, lro_bytes) },
2433 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, ecn_mark) },
2434 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2435 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, wqe_err) },
2436 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2437 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2438 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2439 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2440 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2441 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2442 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, congst_umr) },
2443 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, recover) },
2444 };
2445
2446 static const struct counter_desc qos_sq_stats_desc[] = {
2447 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, packets) },
2448 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, bytes) },
2449 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
2450 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
2451 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
2452 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
2453 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2454 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2455 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2456 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, nop) },
2457 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, timestamps) },
2458 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, mpwqe_blks) },
2459 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, mpwqe_pkts) },
2460 #ifdef CONFIG_MLX5_EN_TLS
2461 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) },
2462 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) },
2463 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_ooo) },
2464 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) },
2465 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) },
2466 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) },
2467 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) },
2468 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) },
2469 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) },
2470 #endif
2471 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2472 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, stopped) },
2473 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, dropped) },
2474 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2475 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, recover) },
2476 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, cqes) },
2477 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, wake) },
2478 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2479 };
2480
2481 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
2482 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
2483 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc)
2484 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
2485 #define NUM_XSKRQ_STATS ARRAY_SIZE(xskrq_stats_desc)
2486 #define NUM_XSKSQ_STATS ARRAY_SIZE(xsksq_stats_desc)
2487 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
2488 #define NUM_PTP_SQ_STATS ARRAY_SIZE(ptp_sq_stats_desc)
2489 #define NUM_PTP_CH_STATS ARRAY_SIZE(ptp_ch_stats_desc)
2490 #define NUM_PTP_CQ_STATS ARRAY_SIZE(ptp_cq_stats_desc)
2491 #define NUM_PTP_RQ_STATS ARRAY_SIZE(ptp_rq_stats_desc)
2492 #define NUM_QOS_SQ_STATS ARRAY_SIZE(qos_sq_stats_desc)
2493
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qos)2494 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qos)
2495 {
2496 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2497 return NUM_QOS_SQ_STATS * smp_load_acquire(&priv->htb_max_qos_sqs);
2498 }
2499
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qos)2500 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qos)
2501 {
2502 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2503 u16 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
2504 int i, qid;
2505
2506 for (qid = 0; qid < max_qos_sqs; qid++)
2507 for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2508 ethtool_sprintf(data, qos_sq_stats_desc[i].format, qid);
2509 }
2510
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qos)2511 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qos)
2512 {
2513 struct mlx5e_sq_stats **stats;
2514 u16 max_qos_sqs;
2515 int i, qid;
2516
2517 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2518 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
2519 stats = READ_ONCE(priv->htb_qos_sq_stats);
2520
2521 for (qid = 0; qid < max_qos_sqs; qid++) {
2522 struct mlx5e_sq_stats *s = READ_ONCE(stats[qid]);
2523
2524 for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2525 mlx5e_ethtool_put_stat(
2526 data,
2527 MLX5E_READ_CTR64_CPU(s, qos_sq_stats_desc, i));
2528 }
2529 }
2530
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qos)2531 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qos) { return; }
2532
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ptp)2533 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ptp)
2534 {
2535 int num = NUM_PTP_CH_STATS;
2536
2537 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2538 return 0;
2539
2540 if (priv->tx_ptp_opened)
2541 num += (NUM_PTP_SQ_STATS + NUM_PTP_CQ_STATS) * priv->max_opened_tc;
2542 if (priv->rx_ptp_opened)
2543 num += NUM_PTP_RQ_STATS;
2544
2545 return num;
2546 }
2547
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(ptp)2548 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(ptp)
2549 {
2550 int i, tc;
2551
2552 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2553 return;
2554
2555 for (i = 0; i < NUM_PTP_CH_STATS; i++)
2556 ethtool_puts(data, ptp_ch_stats_desc[i].format);
2557
2558 if (priv->tx_ptp_opened) {
2559 for (tc = 0; tc < priv->max_opened_tc; tc++)
2560 for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2561 ethtool_sprintf(data,
2562 ptp_sq_stats_desc[i].format,
2563 tc);
2564
2565 for (tc = 0; tc < priv->max_opened_tc; tc++)
2566 for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2567 ethtool_sprintf(data,
2568 ptp_cq_stats_desc[i].format,
2569 tc);
2570 }
2571 if (priv->rx_ptp_opened) {
2572 for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2573 ethtool_puts(data, ptp_rq_stats_desc[i].format);
2574 }
2575 }
2576
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ptp)2577 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ptp)
2578 {
2579 int i, tc;
2580
2581 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2582 return;
2583
2584 for (i = 0; i < NUM_PTP_CH_STATS; i++)
2585 mlx5e_ethtool_put_stat(
2586 data, MLX5E_READ_CTR64_CPU(&priv->ptp_stats.ch,
2587 ptp_ch_stats_desc, i));
2588
2589 if (priv->tx_ptp_opened) {
2590 for (tc = 0; tc < priv->max_opened_tc; tc++)
2591 for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2592 mlx5e_ethtool_put_stat(
2593 data, MLX5E_READ_CTR64_CPU(
2594 &priv->ptp_stats.sq[tc],
2595 ptp_sq_stats_desc, i));
2596
2597 for (tc = 0; tc < priv->max_opened_tc; tc++)
2598 for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2599 mlx5e_ethtool_put_stat(
2600 data, MLX5E_READ_CTR64_CPU(
2601 &priv->ptp_stats.cq[tc],
2602 ptp_cq_stats_desc, i));
2603 }
2604 if (priv->rx_ptp_opened) {
2605 for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2606 mlx5e_ethtool_put_stat(
2607 data,
2608 MLX5E_READ_CTR64_CPU(&priv->ptp_stats.rq,
2609 ptp_rq_stats_desc, i));
2610 }
2611 }
2612
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ptp)2613 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ptp) { return; }
2614
MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(channels)2615 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(channels)
2616 {
2617 int max_nch = mlx5e_stats_nch_read(priv);
2618
2619 return (NUM_RQ_STATS * max_nch) +
2620 (NUM_CH_STATS * max_nch) +
2621 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
2622 (NUM_RQ_XDPSQ_STATS * max_nch) +
2623 (NUM_XDPSQ_STATS * max_nch) +
2624 (NUM_XSKRQ_STATS * max_nch * priv->xsk.ever_used) +
2625 (NUM_XSKSQ_STATS * max_nch * priv->xsk.ever_used);
2626 }
2627
MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(channels)2628 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(channels)
2629 {
2630 int max_nch = mlx5e_stats_nch_read(priv);
2631 bool is_xsk = priv->xsk.ever_used;
2632 int i, j, tc;
2633
2634 for (i = 0; i < max_nch; i++)
2635 for (j = 0; j < NUM_CH_STATS; j++)
2636 ethtool_sprintf(data, ch_stats_desc[j].format, i);
2637
2638 for (i = 0; i < max_nch; i++) {
2639 for (j = 0; j < NUM_RQ_STATS; j++)
2640 ethtool_sprintf(data, rq_stats_desc[j].format, i);
2641 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2642 ethtool_sprintf(data, xskrq_stats_desc[j].format, i);
2643 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2644 ethtool_sprintf(data, rq_xdpsq_stats_desc[j].format, i);
2645 }
2646
2647 for (tc = 0; tc < priv->max_opened_tc; tc++)
2648 for (i = 0; i < max_nch; i++)
2649 for (j = 0; j < NUM_SQ_STATS; j++)
2650 ethtool_sprintf(data, sq_stats_desc[j].format,
2651 i + tc * max_nch);
2652
2653 for (i = 0; i < max_nch; i++) {
2654 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2655 ethtool_sprintf(data, xsksq_stats_desc[j].format, i);
2656 for (j = 0; j < NUM_XDPSQ_STATS; j++)
2657 ethtool_sprintf(data, xdpsq_stats_desc[j].format, i);
2658 }
2659 }
2660
MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels)2661 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels)
2662 {
2663 int max_nch = mlx5e_stats_nch_read(priv);
2664 bool is_xsk = priv->xsk.ever_used;
2665 int i, j, tc;
2666
2667 for (i = 0; i < max_nch; i++)
2668 for (j = 0; j < NUM_CH_STATS; j++)
2669 mlx5e_ethtool_put_stat(
2670 data, MLX5E_READ_CTR64_CPU(
2671 &priv->channel_stats[i]->ch,
2672 ch_stats_desc, j));
2673
2674 for (i = 0; i < max_nch; i++) {
2675 for (j = 0; j < NUM_RQ_STATS; j++)
2676 mlx5e_ethtool_put_stat(
2677 data, MLX5E_READ_CTR64_CPU(
2678 &priv->channel_stats[i]->rq,
2679 rq_stats_desc, j));
2680 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2681 mlx5e_ethtool_put_stat(
2682 data, MLX5E_READ_CTR64_CPU(
2683 &priv->channel_stats[i]->xskrq,
2684 xskrq_stats_desc, j));
2685 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2686 mlx5e_ethtool_put_stat(
2687 data, MLX5E_READ_CTR64_CPU(
2688 &priv->channel_stats[i]->rq_xdpsq,
2689 rq_xdpsq_stats_desc, j));
2690 }
2691
2692 for (tc = 0; tc < priv->max_opened_tc; tc++)
2693 for (i = 0; i < max_nch; i++)
2694 for (j = 0; j < NUM_SQ_STATS; j++)
2695 mlx5e_ethtool_put_stat(
2696 data,
2697 MLX5E_READ_CTR64_CPU(
2698 &priv->channel_stats[i]->sq[tc],
2699 sq_stats_desc, j));
2700
2701 for (i = 0; i < max_nch; i++) {
2702 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2703 mlx5e_ethtool_put_stat(
2704 data, MLX5E_READ_CTR64_CPU(
2705 &priv->channel_stats[i]->xsksq,
2706 xsksq_stats_desc, j));
2707 for (j = 0; j < NUM_XDPSQ_STATS; j++)
2708 mlx5e_ethtool_put_stat(
2709 data, MLX5E_READ_CTR64_CPU(
2710 &priv->channel_stats[i]->xdpsq,
2711 xdpsq_stats_desc, j));
2712 }
2713 }
2714
MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels)2715 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels) { return; }
2716
2717 MLX5E_DEFINE_STATS_GRP(sw, 0);
2718 MLX5E_DEFINE_STATS_GRP(qcnt, MLX5E_NDO_UPDATE_STATS);
2719 MLX5E_DEFINE_STATS_GRP(vnic_env, 0);
2720 MLX5E_DEFINE_STATS_GRP(vport, MLX5E_NDO_UPDATE_STATS);
2721 MLX5E_DEFINE_STATS_GRP(802_3, MLX5E_NDO_UPDATE_STATS);
2722 MLX5E_DEFINE_STATS_GRP(2863, 0);
2723 MLX5E_DEFINE_STATS_GRP(2819, 0);
2724 MLX5E_DEFINE_STATS_GRP(phy, 0);
2725 MLX5E_DEFINE_STATS_GRP(pcie, 0);
2726 MLX5E_DEFINE_STATS_GRP(per_prio, 0);
2727 MLX5E_DEFINE_STATS_GRP(pme, 0);
2728 MLX5E_DEFINE_STATS_GRP(channels, 0);
2729 MLX5E_DEFINE_STATS_GRP(per_port_buff_congest, 0);
2730 MLX5E_DEFINE_STATS_GRP(eth_ext, 0);
2731 static MLX5E_DEFINE_STATS_GRP(tls, 0);
2732 MLX5E_DEFINE_STATS_GRP(ptp, 0);
2733 static MLX5E_DEFINE_STATS_GRP(qos, 0);
2734
2735 /* The stats groups order is opposite to the update_stats() order calls */
2736 mlx5e_stats_grp_t mlx5e_nic_stats_grps[] = {
2737 &MLX5E_STATS_GRP(sw),
2738 &MLX5E_STATS_GRP(qcnt),
2739 &MLX5E_STATS_GRP(vnic_env),
2740 &MLX5E_STATS_GRP(vport),
2741 &MLX5E_STATS_GRP(802_3),
2742 &MLX5E_STATS_GRP(2863),
2743 &MLX5E_STATS_GRP(2819),
2744 &MLX5E_STATS_GRP(phy),
2745 &MLX5E_STATS_GRP(eth_ext),
2746 &MLX5E_STATS_GRP(pcie),
2747 &MLX5E_STATS_GRP(per_prio),
2748 &MLX5E_STATS_GRP(pme),
2749 #ifdef CONFIG_MLX5_EN_IPSEC
2750 &MLX5E_STATS_GRP(ipsec_hw),
2751 &MLX5E_STATS_GRP(ipsec_sw),
2752 #endif
2753 &MLX5E_STATS_GRP(tls),
2754 &MLX5E_STATS_GRP(channels),
2755 &MLX5E_STATS_GRP(per_port_buff_congest),
2756 &MLX5E_STATS_GRP(ptp),
2757 &MLX5E_STATS_GRP(qos),
2758 #ifdef CONFIG_MLX5_MACSEC
2759 &MLX5E_STATS_GRP(macsec_hw),
2760 #endif
2761 &MLX5E_STATS_GRP(pcie_cong),
2762 };
2763
mlx5e_nic_stats_grps_num(struct mlx5e_priv * priv)2764 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv)
2765 {
2766 return ARRAY_SIZE(mlx5e_nic_stats_grps);
2767 }
2768