xref: /linux/crypto/aegis128-neon-inner.c (revision cbe44c389ae80362e72696ac08f7c55a83f2a050) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
4  */
5 
6 #include <asm/neon-intrinsics.h>
7 
8 #ifdef CONFIG_ARM64
9 #define AES_ROUND	"aese %0.16b, %1.16b \n\t aesmc %0.16b, %0.16b"
10 #else
11 #define AES_ROUND	"aese.8 %q0, %q1 \n\t aesmc.8 %q0, %q0"
12 #endif
13 
14 #define AEGIS_BLOCK_SIZE	16
15 
16 #include <stddef.h>
17 #include "aegis-neon.h"
18 
19 extern int aegis128_have_aes_insn;
20 
21 void *memcpy(void *dest, const void *src, size_t n);
22 
23 struct aegis128_state {
24 	uint8x16_t v[5];
25 };
26 
27 extern const uint8_t crypto_aes_sbox[];
28 
29 static struct aegis128_state aegis128_load_state_neon(const void *state)
30 {
31 	return (struct aegis128_state){ {
32 		vld1q_u8(state),
33 		vld1q_u8(state + 16),
34 		vld1q_u8(state + 32),
35 		vld1q_u8(state + 48),
36 		vld1q_u8(state + 64)
37 	} };
38 }
39 
40 static void aegis128_save_state_neon(struct aegis128_state st, void *state)
41 {
42 	vst1q_u8(state, st.v[0]);
43 	vst1q_u8(state + 16, st.v[1]);
44 	vst1q_u8(state + 32, st.v[2]);
45 	vst1q_u8(state + 48, st.v[3]);
46 	vst1q_u8(state + 64, st.v[4]);
47 }
48 
49 static inline __attribute__((always_inline))
50 uint8x16_t aegis_aes_round(uint8x16_t w)
51 {
52 	uint8x16_t z = {};
53 
54 #ifdef CONFIG_ARM64
55 	if (!__builtin_expect(aegis128_have_aes_insn, 1)) {
56 		static const uint8_t shift_rows[] = {
57 			0x0, 0x5, 0xa, 0xf, 0x4, 0x9, 0xe, 0x3,
58 			0x8, 0xd, 0x2, 0x7, 0xc, 0x1, 0x6, 0xb,
59 		};
60 		static const uint8_t ror32by8[] = {
61 			0x1, 0x2, 0x3, 0x0, 0x5, 0x6, 0x7, 0x4,
62 			0x9, 0xa, 0xb, 0x8, 0xd, 0xe, 0xf, 0xc,
63 		};
64 		uint8x16_t v;
65 
66 		// shift rows
67 		w = vqtbl1q_u8(w, vld1q_u8(shift_rows));
68 
69 		// sub bytes
70 #ifndef CONFIG_CC_IS_GCC
71 		v = vqtbl4q_u8(vld1q_u8_x4(crypto_aes_sbox), w);
72 		v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x40), w - 0x40);
73 		v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x80), w - 0x80);
74 		v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0xc0), w - 0xc0);
75 #else
76 		asm("tbl %0.16b, {v16.16b-v19.16b}, %1.16b" : "=w"(v) : "w"(w));
77 		w -= 0x40;
78 		asm("tbx %0.16b, {v20.16b-v23.16b}, %1.16b" : "+w"(v) : "w"(w));
79 		w -= 0x40;
80 		asm("tbx %0.16b, {v24.16b-v27.16b}, %1.16b" : "+w"(v) : "w"(w));
81 		w -= 0x40;
82 		asm("tbx %0.16b, {v28.16b-v31.16b}, %1.16b" : "+w"(v) : "w"(w));
83 #endif
84 
85 		// mix columns
86 		w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b);
87 		w ^= (uint8x16_t)vrev32q_u16((uint16x8_t)v);
88 		w ^= vqtbl1q_u8(v ^ w, vld1q_u8(ror32by8));
89 
90 		return w;
91 	}
92 #endif
93 
94 	/*
95 	 * We use inline asm here instead of the vaeseq_u8/vaesmcq_u8 intrinsics
96 	 * to force the compiler to issue the aese/aesmc instructions in pairs.
97 	 * This is much faster on many cores, where the instruction pair can
98 	 * execute in a single cycle.
99 	 */
100 	asm(AES_ROUND : "+w"(w) : "w"(z));
101 	return w;
102 }
103 
104 static inline __attribute__((always_inline))
105 struct aegis128_state aegis128_update_neon(struct aegis128_state st,
106 					   uint8x16_t m)
107 {
108 	m       ^= aegis_aes_round(st.v[4]);
109 	st.v[4] ^= aegis_aes_round(st.v[3]);
110 	st.v[3] ^= aegis_aes_round(st.v[2]);
111 	st.v[2] ^= aegis_aes_round(st.v[1]);
112 	st.v[1] ^= aegis_aes_round(st.v[0]);
113 	st.v[0] ^= m;
114 
115 	return st;
116 }
117 
118 static inline __attribute__((always_inline))
119 void preload_sbox(void)
120 {
121 	if (!IS_ENABLED(CONFIG_ARM64) ||
122 	    !IS_ENABLED(CONFIG_CC_IS_GCC) ||
123 	    __builtin_expect(aegis128_have_aes_insn, 1))
124 		return;
125 
126 	asm("ld1	{v16.16b-v19.16b}, [%0], #64	\n\t"
127 	    "ld1	{v20.16b-v23.16b}, [%0], #64	\n\t"
128 	    "ld1	{v24.16b-v27.16b}, [%0], #64	\n\t"
129 	    "ld1	{v28.16b-v31.16b}, [%0]		\n\t"
130 	    :: "r"(crypto_aes_sbox));
131 }
132 
133 void crypto_aegis128_init_neon(void *state, const void *key, const void *iv)
134 {
135 	static const uint8_t const0[] = {
136 		0x00, 0x01, 0x01, 0x02, 0x03, 0x05, 0x08, 0x0d,
137 		0x15, 0x22, 0x37, 0x59, 0x90, 0xe9, 0x79, 0x62,
138 	};
139 	static const uint8_t const1[] = {
140 		0xdb, 0x3d, 0x18, 0x55, 0x6d, 0xc2, 0x2f, 0xf1,
141 		0x20, 0x11, 0x31, 0x42, 0x73, 0xb5, 0x28, 0xdd,
142 	};
143 	uint8x16_t k = vld1q_u8(key);
144 	uint8x16_t kiv = k ^ vld1q_u8(iv);
145 	struct aegis128_state st = {{
146 		kiv,
147 		vld1q_u8(const1),
148 		vld1q_u8(const0),
149 		k ^ vld1q_u8(const0),
150 		k ^ vld1q_u8(const1),
151 	}};
152 	int i;
153 
154 	preload_sbox();
155 
156 	for (i = 0; i < 5; i++) {
157 		st = aegis128_update_neon(st, k);
158 		st = aegis128_update_neon(st, kiv);
159 	}
160 	aegis128_save_state_neon(st, state);
161 }
162 
163 void crypto_aegis128_update_neon(void *state, const void *msg)
164 {
165 	struct aegis128_state st = aegis128_load_state_neon(state);
166 
167 	preload_sbox();
168 
169 	st = aegis128_update_neon(st, vld1q_u8(msg));
170 
171 	aegis128_save_state_neon(st, state);
172 }
173 
174 #ifdef CONFIG_ARM
175 /*
176  * AArch32 does not provide these intrinsics natively because it does not
177  * implement the underlying instructions. AArch32 only provides 64-bit
178  * wide vtbl.8/vtbx.8 instruction, so use those instead.
179  */
180 static uint8x16_t vqtbl1q_u8(uint8x16_t a, uint8x16_t b)
181 {
182 	union {
183 		uint8x16_t	val;
184 		uint8x8x2_t	pair;
185 	} __a = { a };
186 
187 	return vcombine_u8(vtbl2_u8(__a.pair, vget_low_u8(b)),
188 			   vtbl2_u8(__a.pair, vget_high_u8(b)));
189 }
190 
191 static uint8x16_t vqtbx1q_u8(uint8x16_t v, uint8x16_t a, uint8x16_t b)
192 {
193 	union {
194 		uint8x16_t	val;
195 		uint8x8x2_t	pair;
196 	} __a = { a };
197 
198 	return vcombine_u8(vtbx2_u8(vget_low_u8(v), __a.pair, vget_low_u8(b)),
199 			   vtbx2_u8(vget_high_u8(v), __a.pair, vget_high_u8(b)));
200 }
201 
202 static int8_t vminvq_s8(int8x16_t v)
203 {
204 	int8x8_t s = vpmin_s8(vget_low_s8(v), vget_high_s8(v));
205 
206 	s = vpmin_s8(s, s);
207 	s = vpmin_s8(s, s);
208 	s = vpmin_s8(s, s);
209 
210 	return vget_lane_s8(s, 0);
211 }
212 #endif
213 
214 static const uint8_t permute[] __aligned(64) = {
215 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
216 	 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
217 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
218 };
219 
220 void crypto_aegis128_encrypt_chunk_neon(void *state, void *dst, const void *src,
221 					unsigned int size)
222 {
223 	struct aegis128_state st = aegis128_load_state_neon(state);
224 	const int short_input = size < AEGIS_BLOCK_SIZE;
225 	uint8x16_t msg;
226 
227 	preload_sbox();
228 
229 	while (size >= AEGIS_BLOCK_SIZE) {
230 		uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
231 
232 		msg = vld1q_u8(src);
233 		st = aegis128_update_neon(st, msg);
234 		msg ^= s;
235 		vst1q_u8(dst, msg);
236 
237 		size -= AEGIS_BLOCK_SIZE;
238 		src += AEGIS_BLOCK_SIZE;
239 		dst += AEGIS_BLOCK_SIZE;
240 	}
241 
242 	if (size > 0) {
243 		uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
244 		uint8_t buf[AEGIS_BLOCK_SIZE];
245 		const void *in = src;
246 		void *out = dst;
247 		uint8x16_t m;
248 
249 		if (__builtin_expect(short_input, 0))
250 			in = out = memcpy(buf + AEGIS_BLOCK_SIZE - size, src, size);
251 
252 		m = vqtbl1q_u8(vld1q_u8(in + size - AEGIS_BLOCK_SIZE),
253 			       vld1q_u8(permute + 32 - size));
254 
255 		st = aegis128_update_neon(st, m);
256 
257 		vst1q_u8(out + size - AEGIS_BLOCK_SIZE,
258 			 vqtbl1q_u8(m ^ s, vld1q_u8(permute + size)));
259 
260 		if (__builtin_expect(short_input, 0))
261 			memcpy(dst, out, size);
262 		else
263 			vst1q_u8(out - AEGIS_BLOCK_SIZE, msg);
264 	}
265 
266 	aegis128_save_state_neon(st, state);
267 }
268 
269 void crypto_aegis128_decrypt_chunk_neon(void *state, void *dst, const void *src,
270 					unsigned int size)
271 {
272 	struct aegis128_state st = aegis128_load_state_neon(state);
273 	const int short_input = size < AEGIS_BLOCK_SIZE;
274 	uint8x16_t msg;
275 
276 	preload_sbox();
277 
278 	while (size >= AEGIS_BLOCK_SIZE) {
279 		msg = vld1q_u8(src) ^ st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
280 		st = aegis128_update_neon(st, msg);
281 		vst1q_u8(dst, msg);
282 
283 		size -= AEGIS_BLOCK_SIZE;
284 		src += AEGIS_BLOCK_SIZE;
285 		dst += AEGIS_BLOCK_SIZE;
286 	}
287 
288 	if (size > 0) {
289 		uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
290 		uint8_t buf[AEGIS_BLOCK_SIZE];
291 		const void *in = src;
292 		void *out = dst;
293 		uint8x16_t m;
294 
295 		if (__builtin_expect(short_input, 0))
296 			in = out = memcpy(buf + AEGIS_BLOCK_SIZE - size, src, size);
297 
298 		m = s ^ vqtbx1q_u8(s, vld1q_u8(in + size - AEGIS_BLOCK_SIZE),
299 				   vld1q_u8(permute + 32 - size));
300 
301 		st = aegis128_update_neon(st, m);
302 
303 		vst1q_u8(out + size - AEGIS_BLOCK_SIZE,
304 			 vqtbl1q_u8(m, vld1q_u8(permute + size)));
305 
306 		if (__builtin_expect(short_input, 0))
307 			memcpy(dst, out, size);
308 		else
309 			vst1q_u8(out - AEGIS_BLOCK_SIZE, msg);
310 	}
311 
312 	aegis128_save_state_neon(st, state);
313 }
314 
315 int crypto_aegis128_final_neon(void *state, void *tag_xor,
316 			       unsigned int assoclen,
317 			       unsigned int cryptlen,
318 			       unsigned int authsize)
319 {
320 	struct aegis128_state st = aegis128_load_state_neon(state);
321 	uint8x16_t v;
322 	int i;
323 
324 	preload_sbox();
325 
326 	v = st.v[3] ^ (uint8x16_t)vcombine_u64(vmov_n_u64(8ULL * assoclen),
327 					       vmov_n_u64(8ULL * cryptlen));
328 
329 	for (i = 0; i < 7; i++)
330 		st = aegis128_update_neon(st, v);
331 
332 	v = st.v[0] ^ st.v[1] ^ st.v[2] ^ st.v[3] ^ st.v[4];
333 
334 	if (authsize > 0) {
335 		v = vqtbl1q_u8(~vceqq_u8(v, vld1q_u8(tag_xor)),
336 			       vld1q_u8(permute + authsize));
337 
338 		return vminvq_s8((int8x16_t)v);
339 	}
340 
341 	vst1q_u8(tag_xor, v);
342 	return 0;
343 }
344