1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Endpoint Function Driver to implement Non-Transparent Bridge functionality
4 *
5 * Copyright (C) 2020 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 /*
10 * The PCI NTB function driver configures the SoC with multiple PCIe Endpoint
11 * (EP) controller instances (see diagram below) in such a way that
12 * transactions from one EP controller are routed to the other EP controller.
13 * Once PCI NTB function driver configures the SoC with multiple EP instances,
14 * HOST1 and HOST2 can communicate with each other using SoC as a bridge.
15 *
16 * +-------------+ +-------------+
17 * | | | |
18 * | HOST1 | | HOST2 |
19 * | | | |
20 * +------^------+ +------^------+
21 * | |
22 * | |
23 * +---------|-------------------------------------------------|---------+
24 * | +------v------+ +------v------+ |
25 * | | | | | |
26 * | | EP | | EP | |
27 * | | CONTROLLER1 | | CONTROLLER2 | |
28 * | | <-----------------------------------> | |
29 * | | | | | |
30 * | | | | | |
31 * | | | SoC With Multiple EP Instances | | |
32 * | | | (Configured using NTB Function) | | |
33 * | +-------------+ +-------------+ |
34 * +---------------------------------------------------------------------+
35 */
36
37 #include <linux/delay.h>
38 #include <linux/io.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include <linux/pci-epc.h>
43 #include <linux/pci-epf.h>
44
45 static struct workqueue_struct *kpcintb_workqueue;
46
47 #define COMMAND_CONFIGURE_DOORBELL 1
48 #define COMMAND_TEARDOWN_DOORBELL 2
49 #define COMMAND_CONFIGURE_MW 3
50 #define COMMAND_TEARDOWN_MW 4
51 #define COMMAND_LINK_UP 5
52 #define COMMAND_LINK_DOWN 6
53
54 #define COMMAND_STATUS_OK 1
55 #define COMMAND_STATUS_ERROR 2
56
57 #define LINK_STATUS_UP BIT(0)
58
59 #define SPAD_COUNT 64
60 #define DB_COUNT 4
61 #define NTB_MW_OFFSET 2
62 #define DB_COUNT_MASK GENMASK(15, 0)
63 #define MSIX_ENABLE BIT(16)
64 #define MAX_DB_COUNT 32
65 #define MAX_MW 4
66
67 enum epf_ntb_bar {
68 BAR_CONFIG,
69 BAR_PEER_SPAD,
70 BAR_DB_MW1,
71 BAR_MW2,
72 BAR_MW3,
73 BAR_MW4,
74 };
75
76 struct epf_ntb {
77 u32 num_mws;
78 u32 db_count;
79 u32 spad_count;
80 struct pci_epf *epf;
81 u64 mws_size[MAX_MW];
82 struct config_group group;
83 struct epf_ntb_epc *epc[2];
84 };
85
86 #define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group)
87
88 struct epf_ntb_epc {
89 u8 func_no;
90 u8 vfunc_no;
91 bool linkup;
92 bool is_msix;
93 int msix_bar;
94 u32 spad_size;
95 struct pci_epc *epc;
96 struct epf_ntb *epf_ntb;
97 void __iomem *mw_addr[6];
98 size_t msix_table_offset;
99 struct epf_ntb_ctrl *reg;
100 struct pci_epf_bar *epf_bar;
101 enum pci_barno epf_ntb_bar[6];
102 struct delayed_work cmd_handler;
103 enum pci_epc_interface_type type;
104 const struct pci_epc_features *epc_features;
105 };
106
107 struct epf_ntb_ctrl {
108 u32 command;
109 u32 argument;
110 u16 command_status;
111 u16 link_status;
112 u32 topology;
113 u64 addr;
114 u64 size;
115 u32 num_mws;
116 u32 mw1_offset;
117 u32 spad_offset;
118 u32 spad_count;
119 u32 db_entry_size;
120 u32 db_data[MAX_DB_COUNT];
121 u32 db_offset[MAX_DB_COUNT];
122 } __packed;
123
124 static struct pci_epf_header epf_ntb_header = {
125 .vendorid = PCI_ANY_ID,
126 .deviceid = PCI_ANY_ID,
127 .baseclass_code = PCI_BASE_CLASS_MEMORY,
128 .interrupt_pin = PCI_INTERRUPT_INTA,
129 };
130
131 /**
132 * epf_ntb_link_up() - Raise link_up interrupt to both the hosts
133 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
134 * @link_up: true or false indicating Link is UP or Down
135 *
136 * Once NTB function in HOST1 and the NTB function in HOST2 invoke
137 * ntb_link_enable(), this NTB function driver will trigger a link event to
138 * the NTB client in both the hosts.
139 */
epf_ntb_link_up(struct epf_ntb * ntb,bool link_up)140 static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
141 {
142 enum pci_epc_interface_type type;
143 struct epf_ntb_epc *ntb_epc;
144 struct epf_ntb_ctrl *ctrl;
145 unsigned int irq_type;
146 struct pci_epc *epc;
147 u8 func_no, vfunc_no;
148 bool is_msix;
149 int ret;
150
151 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) {
152 ntb_epc = ntb->epc[type];
153 epc = ntb_epc->epc;
154 func_no = ntb_epc->func_no;
155 vfunc_no = ntb_epc->vfunc_no;
156 is_msix = ntb_epc->is_msix;
157 ctrl = ntb_epc->reg;
158 if (link_up)
159 ctrl->link_status |= LINK_STATUS_UP;
160 else
161 ctrl->link_status &= ~LINK_STATUS_UP;
162 irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
163 ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
164 if (ret) {
165 dev_err(&epc->dev,
166 "%s intf: Failed to raise Link Up IRQ\n",
167 pci_epc_interface_string(type));
168 return ret;
169 }
170 }
171
172 return 0;
173 }
174
175 /**
176 * epf_ntb_configure_mw() - Configure the Outbound Address Space for one host
177 * to access the memory window of other host
178 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
179 * @type: PRIMARY interface or SECONDARY interface
180 * @mw: Index of the memory window (either 0, 1, 2 or 3)
181 *
182 * +-----------------+ +---->+----------------+-----------+-----------------+
183 * | BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 |
184 * +-----------------+ | +----------------+ +-----------------+
185 * | BAR1 | | | Doorbell 2 +---------+ | |
186 * +-----------------+----+ +----------------+ | | |
187 * | BAR2 | | Doorbell 3 +-------+ | +-----------------+
188 * +-----------------+----+ +----------------+ | +-> MSI|X ADDRESS 2 |
189 * | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
190 * +-----------------+ | |----------------+ | | | |
191 * | BAR4 | | | | | | +-----------------+
192 * +-----------------+ | | MW1 +---+ | +-->+ MSI|X ADDRESS 3||
193 * | BAR5 | | | | | | +-----------------+
194 * +-----------------+ +---->-----------------+ | | | |
195 * EP CONTROLLER 1 | | | | +-----------------+
196 * | | | +---->+ MSI|X ADDRESS 4 |
197 * +----------------+ | +-----------------+
198 * (A) EP CONTROLLER 2 | | |
199 * (OB SPACE) | | |
200 * +-------> MW1 |
201 * | |
202 * | |
203 * (B) +-----------------+
204 * | |
205 * | |
206 * | |
207 * | |
208 * | |
209 * +-----------------+
210 * PCI Address Space
211 * (Managed by HOST2)
212 *
213 * This function performs stage (B) in the above diagram (see MW1) i.e., map OB
214 * address space of memory window to PCI address space.
215 *
216 * This operation requires 3 parameters
217 * 1) Address in the outbound address space
218 * 2) Address in the PCI Address space
219 * 3) Size of the address region to be mapped
220 *
221 * The address in the outbound address space (for MW1, MW2, MW3 and MW4) is
222 * stored in epf_bar corresponding to BAR_DB_MW1 for MW1 and BAR_MW2, BAR_MW3
223 * BAR_MW4 for rest of the BARs of epf_ntb_epc that is connected to HOST1. This
224 * is populated in epf_ntb_alloc_peer_mem() in this driver.
225 *
226 * The address and size of the PCI address region that has to be mapped would
227 * be provided by HOST2 in ctrl->addr and ctrl->size of epf_ntb_epc that is
228 * connected to HOST2.
229 *
230 * Please note Memory window1 (MW1) and Doorbell registers together will be
231 * mapped to a single BAR (BAR2) above for 32-bit BARs. The exact BAR that's
232 * used for Memory window (MW) can be obtained from epf_ntb_bar[BAR_DB_MW1],
233 * epf_ntb_bar[BAR_MW2], epf_ntb_bar[BAR_MW2], epf_ntb_bar[BAR_MW2].
234 */
epf_ntb_configure_mw(struct epf_ntb * ntb,enum pci_epc_interface_type type,u32 mw)235 static int epf_ntb_configure_mw(struct epf_ntb *ntb,
236 enum pci_epc_interface_type type, u32 mw)
237 {
238 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
239 struct pci_epf_bar *peer_epf_bar;
240 enum pci_barno peer_barno;
241 struct epf_ntb_ctrl *ctrl;
242 phys_addr_t phys_addr;
243 u8 func_no, vfunc_no;
244 struct pci_epc *epc;
245 u64 addr, size;
246 int ret = 0;
247
248 ntb_epc = ntb->epc[type];
249 epc = ntb_epc->epc;
250
251 peer_ntb_epc = ntb->epc[!type];
252 peer_barno = peer_ntb_epc->epf_ntb_bar[mw + NTB_MW_OFFSET];
253 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
254
255 phys_addr = peer_epf_bar->phys_addr;
256 ctrl = ntb_epc->reg;
257 addr = ctrl->addr;
258 size = ctrl->size;
259 if (mw + NTB_MW_OFFSET == BAR_DB_MW1)
260 phys_addr += ctrl->mw1_offset;
261
262 if (size > ntb->mws_size[mw]) {
263 dev_err(&epc->dev,
264 "%s intf: MW: %d Req Sz:%llxx > Supported Sz:%llx\n",
265 pci_epc_interface_string(type), mw, size,
266 ntb->mws_size[mw]);
267 ret = -EINVAL;
268 goto err_invalid_size;
269 }
270
271 func_no = ntb_epc->func_no;
272 vfunc_no = ntb_epc->vfunc_no;
273
274 ret = pci_epc_map_addr(epc, func_no, vfunc_no, phys_addr, addr, size);
275 if (ret)
276 dev_err(&epc->dev,
277 "%s intf: Failed to map memory window %d address\n",
278 pci_epc_interface_string(type), mw);
279
280 err_invalid_size:
281
282 return ret;
283 }
284
285 /**
286 * epf_ntb_teardown_mw() - Teardown the configured OB ATU
287 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
288 * @type: PRIMARY interface or SECONDARY interface
289 * @mw: Index of the memory window (either 0, 1, 2 or 3)
290 *
291 * Teardown the configured OB ATU configured in epf_ntb_configure_mw() using
292 * pci_epc_unmap_addr()
293 */
epf_ntb_teardown_mw(struct epf_ntb * ntb,enum pci_epc_interface_type type,u32 mw)294 static void epf_ntb_teardown_mw(struct epf_ntb *ntb,
295 enum pci_epc_interface_type type, u32 mw)
296 {
297 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
298 struct pci_epf_bar *peer_epf_bar;
299 enum pci_barno peer_barno;
300 struct epf_ntb_ctrl *ctrl;
301 phys_addr_t phys_addr;
302 u8 func_no, vfunc_no;
303 struct pci_epc *epc;
304
305 ntb_epc = ntb->epc[type];
306 epc = ntb_epc->epc;
307
308 peer_ntb_epc = ntb->epc[!type];
309 peer_barno = peer_ntb_epc->epf_ntb_bar[mw + NTB_MW_OFFSET];
310 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
311
312 phys_addr = peer_epf_bar->phys_addr;
313 ctrl = ntb_epc->reg;
314 if (mw + NTB_MW_OFFSET == BAR_DB_MW1)
315 phys_addr += ctrl->mw1_offset;
316 func_no = ntb_epc->func_no;
317 vfunc_no = ntb_epc->vfunc_no;
318
319 pci_epc_unmap_addr(epc, func_no, vfunc_no, phys_addr);
320 }
321
322 /**
323 * epf_ntb_configure_msi() - Map OB address space to MSI address
324 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
325 * @type: PRIMARY interface or SECONDARY interface
326 * @db_count: Number of doorbell interrupts to map
327 *
328 *+-----------------+ +----->+----------------+-----------+-----------------+
329 *| BAR0 | | | Doorbell 1 +---+-------> MSI ADDRESS |
330 *+-----------------+ | +----------------+ | +-----------------+
331 *| BAR1 | | | Doorbell 2 +---+ | |
332 *+-----------------+----+ +----------------+ | | |
333 *| BAR2 | | Doorbell 3 +---+ | |
334 *+-----------------+----+ +----------------+ | | |
335 *| BAR3 | | | Doorbell 4 +---+ | |
336 *+-----------------+ | |----------------+ | |
337 *| BAR4 | | | | | |
338 *+-----------------+ | | MW1 | | |
339 *| BAR5 | | | | | |
340 *+-----------------+ +----->-----------------+ | |
341 * EP CONTROLLER 1 | | | |
342 * | | | |
343 * +----------------+ +-----------------+
344 * (A) EP CONTROLLER 2 | |
345 * (OB SPACE) | |
346 * | MW1 |
347 * | |
348 * | |
349 * (B) +-----------------+
350 * | |
351 * | |
352 * | |
353 * | |
354 * | |
355 * +-----------------+
356 * PCI Address Space
357 * (Managed by HOST2)
358 *
359 *
360 * This function performs stage (B) in the above diagram (see Doorbell 1,
361 * Doorbell 2, Doorbell 3, Doorbell 4) i.e map OB address space corresponding to
362 * doorbell to MSI address in PCI address space.
363 *
364 * This operation requires 3 parameters
365 * 1) Address reserved for doorbell in the outbound address space
366 * 2) MSI-X address in the PCIe Address space
367 * 3) Number of MSI-X interrupts that has to be configured
368 *
369 * The address in the outbound address space (for the Doorbell) is stored in
370 * epf_bar corresponding to BAR_DB_MW1 of epf_ntb_epc that is connected to
371 * HOST1. This is populated in epf_ntb_alloc_peer_mem() in this driver along
372 * with address for MW1.
373 *
374 * pci_epc_map_msi_irq() takes the MSI address from MSI capability register
375 * and maps the OB address (obtained in epf_ntb_alloc_peer_mem()) to the MSI
376 * address.
377 *
378 * epf_ntb_configure_msi() also stores the MSI data to raise each interrupt
379 * in db_data of the peer's control region. This helps the peer to raise
380 * doorbell of the other host by writing db_data to the BAR corresponding to
381 * BAR_DB_MW1.
382 */
epf_ntb_configure_msi(struct epf_ntb * ntb,enum pci_epc_interface_type type,u16 db_count)383 static int epf_ntb_configure_msi(struct epf_ntb *ntb,
384 enum pci_epc_interface_type type, u16 db_count)
385 {
386 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
387 u32 db_entry_size, db_data, db_offset;
388 struct pci_epf_bar *peer_epf_bar;
389 struct epf_ntb_ctrl *peer_ctrl;
390 enum pci_barno peer_barno;
391 phys_addr_t phys_addr;
392 u8 func_no, vfunc_no;
393 struct pci_epc *epc;
394 int ret, i;
395
396 ntb_epc = ntb->epc[type];
397 epc = ntb_epc->epc;
398
399 peer_ntb_epc = ntb->epc[!type];
400 peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_DB_MW1];
401 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
402 peer_ctrl = peer_ntb_epc->reg;
403 db_entry_size = peer_ctrl->db_entry_size;
404
405 phys_addr = peer_epf_bar->phys_addr;
406 func_no = ntb_epc->func_no;
407 vfunc_no = ntb_epc->vfunc_no;
408
409 ret = pci_epc_map_msi_irq(epc, func_no, vfunc_no, phys_addr, db_count,
410 db_entry_size, &db_data, &db_offset);
411 if (ret) {
412 dev_err(&epc->dev, "%s intf: Failed to map MSI IRQ\n",
413 pci_epc_interface_string(type));
414 return ret;
415 }
416
417 for (i = 0; i < db_count; i++) {
418 peer_ctrl->db_data[i] = db_data | i;
419 peer_ctrl->db_offset[i] = db_offset;
420 }
421
422 return 0;
423 }
424
425 /**
426 * epf_ntb_configure_msix() - Map OB address space to MSI-X address
427 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
428 * @type: PRIMARY interface or SECONDARY interface
429 * @db_count: Number of doorbell interrupts to map
430 *
431 *+-----------------+ +----->+----------------+-----------+-----------------+
432 *| BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
433 *+-----------------+ | +----------------+ +-----------------+
434 *| BAR1 | | | Doorbell 2 +---------+ | |
435 *+-----------------+----+ +----------------+ | | |
436 *| BAR2 | | Doorbell 3 +-------+ | +-----------------+
437 *+-----------------+----+ +----------------+ | +-> MSI-X ADDRESS 2 |
438 *| BAR3 | | | Doorbell 4 +-----+ | +-----------------+
439 *+-----------------+ | |----------------+ | | | |
440 *| BAR4 | | | | | | +-----------------+
441 *+-----------------+ | | MW1 + | +-->+ MSI-X ADDRESS 3||
442 *| BAR5 | | | | | +-----------------+
443 *+-----------------+ +----->-----------------+ | | |
444 * EP CONTROLLER 1 | | | +-----------------+
445 * | | +---->+ MSI-X ADDRESS 4 |
446 * +----------------+ +-----------------+
447 * (A) EP CONTROLLER 2 | |
448 * (OB SPACE) | |
449 * | MW1 |
450 * | |
451 * | |
452 * (B) +-----------------+
453 * | |
454 * | |
455 * | |
456 * | |
457 * | |
458 * +-----------------+
459 * PCI Address Space
460 * (Managed by HOST2)
461 *
462 * This function performs stage (B) in the above diagram (see Doorbell 1,
463 * Doorbell 2, Doorbell 3, Doorbell 4) i.e map OB address space corresponding to
464 * doorbell to MSI-X address in PCI address space.
465 *
466 * This operation requires 3 parameters
467 * 1) Address reserved for doorbell in the outbound address space
468 * 2) MSI-X address in the PCIe Address space
469 * 3) Number of MSI-X interrupts that has to be configured
470 *
471 * The address in the outbound address space (for the Doorbell) is stored in
472 * epf_bar corresponding to BAR_DB_MW1 of epf_ntb_epc that is connected to
473 * HOST1. This is populated in epf_ntb_alloc_peer_mem() in this driver along
474 * with address for MW1.
475 *
476 * The MSI-X address is in the MSI-X table of EP CONTROLLER 2 and
477 * the count of doorbell is in ctrl->argument of epf_ntb_epc that is connected
478 * to HOST2. MSI-X table is stored memory mapped to ntb_epc->msix_bar and the
479 * offset is in ntb_epc->msix_table_offset. From this epf_ntb_configure_msix()
480 * gets the MSI-X address and data.
481 *
482 * epf_ntb_configure_msix() also stores the MSI-X data to raise each interrupt
483 * in db_data of the peer's control region. This helps the peer to raise
484 * doorbell of the other host by writing db_data to the BAR corresponding to
485 * BAR_DB_MW1.
486 */
epf_ntb_configure_msix(struct epf_ntb * ntb,enum pci_epc_interface_type type,u16 db_count)487 static int epf_ntb_configure_msix(struct epf_ntb *ntb,
488 enum pci_epc_interface_type type,
489 u16 db_count)
490 {
491 const struct pci_epc_features *epc_features;
492 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
493 struct pci_epf_bar *peer_epf_bar, *epf_bar;
494 struct pci_epf_msix_tbl *msix_tbl;
495 struct epf_ntb_ctrl *peer_ctrl;
496 u32 db_entry_size, msg_data;
497 enum pci_barno peer_barno;
498 phys_addr_t phys_addr;
499 u8 func_no, vfunc_no;
500 struct pci_epc *epc;
501 size_t align;
502 u64 msg_addr;
503 int ret, i;
504
505 ntb_epc = ntb->epc[type];
506 epc = ntb_epc->epc;
507
508 epf_bar = &ntb_epc->epf_bar[ntb_epc->msix_bar];
509 msix_tbl = epf_bar->addr + ntb_epc->msix_table_offset;
510
511 peer_ntb_epc = ntb->epc[!type];
512 peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_DB_MW1];
513 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
514 phys_addr = peer_epf_bar->phys_addr;
515 peer_ctrl = peer_ntb_epc->reg;
516 epc_features = ntb_epc->epc_features;
517 align = epc_features->align;
518
519 func_no = ntb_epc->func_no;
520 vfunc_no = ntb_epc->vfunc_no;
521 db_entry_size = peer_ctrl->db_entry_size;
522
523 for (i = 0; i < db_count; i++) {
524 msg_addr = ALIGN_DOWN(msix_tbl[i].msg_addr, align);
525 msg_data = msix_tbl[i].msg_data;
526 ret = pci_epc_map_addr(epc, func_no, vfunc_no, phys_addr, msg_addr,
527 db_entry_size);
528 if (ret) {
529 dev_err(&epc->dev,
530 "%s intf: Failed to configure MSI-X IRQ\n",
531 pci_epc_interface_string(type));
532 return ret;
533 }
534 phys_addr = phys_addr + db_entry_size;
535 peer_ctrl->db_data[i] = msg_data;
536 peer_ctrl->db_offset[i] = msix_tbl[i].msg_addr & (align - 1);
537 }
538 ntb_epc->is_msix = true;
539
540 return 0;
541 }
542
543 /**
544 * epf_ntb_configure_db() - Configure the Outbound Address Space for one host
545 * to ring the doorbell of other host
546 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
547 * @type: PRIMARY interface or SECONDARY interface
548 * @db_count: Count of the number of doorbells that has to be configured
549 * @msix: Indicates whether MSI-X or MSI should be used
550 *
551 * Invokes epf_ntb_configure_msix() or epf_ntb_configure_msi() required for
552 * one HOST to ring the doorbell of other HOST.
553 */
epf_ntb_configure_db(struct epf_ntb * ntb,enum pci_epc_interface_type type,u16 db_count,bool msix)554 static int epf_ntb_configure_db(struct epf_ntb *ntb,
555 enum pci_epc_interface_type type,
556 u16 db_count, bool msix)
557 {
558 struct epf_ntb_epc *ntb_epc;
559 struct pci_epc *epc;
560 int ret;
561
562 ntb_epc = ntb->epc[type];
563 epc = ntb_epc->epc;
564
565 if (!db_count || db_count > MAX_DB_COUNT) {
566 dev_err(&epc->dev, "DB count %d out of range (1 - %d)\n",
567 db_count, MAX_DB_COUNT);
568 return -EINVAL;
569 }
570
571 if (msix)
572 ret = epf_ntb_configure_msix(ntb, type, db_count);
573 else
574 ret = epf_ntb_configure_msi(ntb, type, db_count);
575
576 if (ret)
577 dev_err(&epc->dev, "%s intf: Failed to configure DB\n",
578 pci_epc_interface_string(type));
579
580 return ret;
581 }
582
583 /**
584 * epf_ntb_teardown_db() - Unmap address in OB address space to MSI/MSI-X
585 * address
586 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
587 * @type: PRIMARY interface or SECONDARY interface
588 *
589 * Invoke pci_epc_unmap_addr() to unmap OB address to MSI/MSI-X address.
590 */
591 static void
epf_ntb_teardown_db(struct epf_ntb * ntb,enum pci_epc_interface_type type)592 epf_ntb_teardown_db(struct epf_ntb *ntb, enum pci_epc_interface_type type)
593 {
594 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
595 struct pci_epf_bar *peer_epf_bar;
596 enum pci_barno peer_barno;
597 phys_addr_t phys_addr;
598 u8 func_no, vfunc_no;
599 struct pci_epc *epc;
600
601 ntb_epc = ntb->epc[type];
602 epc = ntb_epc->epc;
603
604 peer_ntb_epc = ntb->epc[!type];
605 peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_DB_MW1];
606 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
607 phys_addr = peer_epf_bar->phys_addr;
608 func_no = ntb_epc->func_no;
609 vfunc_no = ntb_epc->vfunc_no;
610
611 pci_epc_unmap_addr(epc, func_no, vfunc_no, phys_addr);
612 }
613
614 /**
615 * epf_ntb_cmd_handler() - Handle commands provided by the NTB Host
616 * @work: work_struct for the two epf_ntb_epc (PRIMARY and SECONDARY)
617 *
618 * Workqueue function that gets invoked for the two epf_ntb_epc
619 * periodically (once every 5ms) to see if it has received any commands
620 * from NTB host. The host can send commands to configure doorbell or
621 * configure memory window or to update link status.
622 */
epf_ntb_cmd_handler(struct work_struct * work)623 static void epf_ntb_cmd_handler(struct work_struct *work)
624 {
625 enum pci_epc_interface_type type;
626 struct epf_ntb_epc *ntb_epc;
627 struct epf_ntb_ctrl *ctrl;
628 u32 command, argument;
629 struct epf_ntb *ntb;
630 struct device *dev;
631 u16 db_count;
632 bool is_msix;
633 int ret;
634
635 ntb_epc = container_of(work, struct epf_ntb_epc, cmd_handler.work);
636 ctrl = ntb_epc->reg;
637 command = ctrl->command;
638 if (!command)
639 goto reset_handler;
640 argument = ctrl->argument;
641
642 ctrl->command = 0;
643 ctrl->argument = 0;
644
645 ctrl = ntb_epc->reg;
646 type = ntb_epc->type;
647 ntb = ntb_epc->epf_ntb;
648 dev = &ntb->epf->dev;
649
650 switch (command) {
651 case COMMAND_CONFIGURE_DOORBELL:
652 db_count = argument & DB_COUNT_MASK;
653 is_msix = argument & MSIX_ENABLE;
654 ret = epf_ntb_configure_db(ntb, type, db_count, is_msix);
655 if (ret < 0)
656 ctrl->command_status = COMMAND_STATUS_ERROR;
657 else
658 ctrl->command_status = COMMAND_STATUS_OK;
659 break;
660 case COMMAND_TEARDOWN_DOORBELL:
661 epf_ntb_teardown_db(ntb, type);
662 ctrl->command_status = COMMAND_STATUS_OK;
663 break;
664 case COMMAND_CONFIGURE_MW:
665 ret = epf_ntb_configure_mw(ntb, type, argument);
666 if (ret < 0)
667 ctrl->command_status = COMMAND_STATUS_ERROR;
668 else
669 ctrl->command_status = COMMAND_STATUS_OK;
670 break;
671 case COMMAND_TEARDOWN_MW:
672 epf_ntb_teardown_mw(ntb, type, argument);
673 ctrl->command_status = COMMAND_STATUS_OK;
674 break;
675 case COMMAND_LINK_UP:
676 ntb_epc->linkup = true;
677 if (ntb->epc[PRIMARY_INTERFACE]->linkup &&
678 ntb->epc[SECONDARY_INTERFACE]->linkup) {
679 ret = epf_ntb_link_up(ntb, true);
680 if (ret < 0)
681 ctrl->command_status = COMMAND_STATUS_ERROR;
682 else
683 ctrl->command_status = COMMAND_STATUS_OK;
684 goto reset_handler;
685 }
686 ctrl->command_status = COMMAND_STATUS_OK;
687 break;
688 case COMMAND_LINK_DOWN:
689 ntb_epc->linkup = false;
690 ret = epf_ntb_link_up(ntb, false);
691 if (ret < 0)
692 ctrl->command_status = COMMAND_STATUS_ERROR;
693 else
694 ctrl->command_status = COMMAND_STATUS_OK;
695 break;
696 default:
697 dev_err(dev, "%s intf UNKNOWN command: %d\n",
698 pci_epc_interface_string(type), command);
699 break;
700 }
701
702 reset_handler:
703 queue_delayed_work(kpcintb_workqueue, &ntb_epc->cmd_handler,
704 msecs_to_jiffies(5));
705 }
706
707 /**
708 * epf_ntb_peer_spad_bar_clear() - Clear Peer Scratchpad BAR
709 * @ntb_epc: EPC associated with one of the HOST which holds peer's outbound
710 * address.
711 *
712 *+-----------------+------->+------------------+ +-----------------+
713 *| BAR0 | | CONFIG REGION | | BAR0 |
714 *+-----------------+----+ +------------------+<-------+-----------------+
715 *| BAR1 | | |SCRATCHPAD REGION | | BAR1 |
716 *+-----------------+ +-->+------------------+<-------+-----------------+
717 *| BAR2 | Local Memory | BAR2 |
718 *+-----------------+ +-----------------+
719 *| BAR3 | | BAR3 |
720 *+-----------------+ +-----------------+
721 *| BAR4 | | BAR4 |
722 *+-----------------+ +-----------------+
723 *| BAR5 | | BAR5 |
724 *+-----------------+ +-----------------+
725 * EP CONTROLLER 1 EP CONTROLLER 2
726 *
727 * Clear BAR1 of EP CONTROLLER 2 which contains the HOST2's peer scratchpad
728 * region. While BAR1 is the default peer scratchpad BAR, an NTB could have
729 * other BARs for peer scratchpad (because of 64-bit BARs or reserved BARs).
730 * This function can get the exact BAR used for peer scratchpad from
731 * epf_ntb_bar[BAR_PEER_SPAD].
732 *
733 * Since HOST2's peer scratchpad is also HOST1's self scratchpad, this function
734 * gets the address of peer scratchpad from
735 * peer_ntb_epc->epf_ntb_bar[BAR_CONFIG].
736 */
epf_ntb_peer_spad_bar_clear(struct epf_ntb_epc * ntb_epc)737 static void epf_ntb_peer_spad_bar_clear(struct epf_ntb_epc *ntb_epc)
738 {
739 struct pci_epf_bar *epf_bar;
740 enum pci_barno barno;
741 u8 func_no, vfunc_no;
742 struct pci_epc *epc;
743
744 epc = ntb_epc->epc;
745 func_no = ntb_epc->func_no;
746 vfunc_no = ntb_epc->vfunc_no;
747 barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD];
748 epf_bar = &ntb_epc->epf_bar[barno];
749 pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar);
750 }
751
752 /**
753 * epf_ntb_peer_spad_bar_set() - Set peer scratchpad BAR
754 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
755 * @type: PRIMARY interface or SECONDARY interface
756 *
757 *+-----------------+------->+------------------+ +-----------------+
758 *| BAR0 | | CONFIG REGION | | BAR0 |
759 *+-----------------+----+ +------------------+<-------+-----------------+
760 *| BAR1 | | |SCRATCHPAD REGION | | BAR1 |
761 *+-----------------+ +-->+------------------+<-------+-----------------+
762 *| BAR2 | Local Memory | BAR2 |
763 *+-----------------+ +-----------------+
764 *| BAR3 | | BAR3 |
765 *+-----------------+ +-----------------+
766 *| BAR4 | | BAR4 |
767 *+-----------------+ +-----------------+
768 *| BAR5 | | BAR5 |
769 *+-----------------+ +-----------------+
770 * EP CONTROLLER 1 EP CONTROLLER 2
771 *
772 * Set BAR1 of EP CONTROLLER 2 which contains the HOST2's peer scratchpad
773 * region. While BAR1 is the default peer scratchpad BAR, an NTB could have
774 * other BARs for peer scratchpad (because of 64-bit BARs or reserved BARs).
775 * This function can get the exact BAR used for peer scratchpad from
776 * epf_ntb_bar[BAR_PEER_SPAD].
777 *
778 * Since HOST2's peer scratchpad is also HOST1's self scratchpad, this function
779 * gets the address of peer scratchpad from
780 * peer_ntb_epc->epf_ntb_bar[BAR_CONFIG].
781 */
epf_ntb_peer_spad_bar_set(struct epf_ntb * ntb,enum pci_epc_interface_type type)782 static int epf_ntb_peer_spad_bar_set(struct epf_ntb *ntb,
783 enum pci_epc_interface_type type)
784 {
785 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
786 struct pci_epf_bar *peer_epf_bar, *epf_bar;
787 enum pci_barno peer_barno, barno;
788 u32 peer_spad_offset;
789 u8 func_no, vfunc_no;
790 struct pci_epc *epc;
791 struct device *dev;
792 int ret;
793
794 dev = &ntb->epf->dev;
795
796 peer_ntb_epc = ntb->epc[!type];
797 peer_barno = peer_ntb_epc->epf_ntb_bar[BAR_CONFIG];
798 peer_epf_bar = &peer_ntb_epc->epf_bar[peer_barno];
799
800 ntb_epc = ntb->epc[type];
801 barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD];
802 epf_bar = &ntb_epc->epf_bar[barno];
803 func_no = ntb_epc->func_no;
804 vfunc_no = ntb_epc->vfunc_no;
805 epc = ntb_epc->epc;
806
807 peer_spad_offset = peer_ntb_epc->reg->spad_offset;
808 epf_bar->phys_addr = peer_epf_bar->phys_addr + peer_spad_offset;
809 epf_bar->size = peer_ntb_epc->spad_size;
810 epf_bar->barno = barno;
811 epf_bar->flags = PCI_BASE_ADDRESS_MEM_TYPE_32;
812
813 ret = pci_epc_set_bar(epc, func_no, vfunc_no, epf_bar);
814 if (ret) {
815 dev_err(dev, "%s intf: peer SPAD BAR set failed\n",
816 pci_epc_interface_string(type));
817 return ret;
818 }
819
820 return 0;
821 }
822
823 /**
824 * epf_ntb_config_sspad_bar_clear() - Clear Config + Self scratchpad BAR
825 * @ntb_epc: EPC associated with one of the HOST which holds peer's outbound
826 * address.
827 *
828 * +-----------------+------->+------------------+ +-----------------+
829 * | BAR0 | | CONFIG REGION | | BAR0 |
830 * +-----------------+----+ +------------------+<-------+-----------------+
831 * | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
832 * +-----------------+ +-->+------------------+<-------+-----------------+
833 * | BAR2 | Local Memory | BAR2 |
834 * +-----------------+ +-----------------+
835 * | BAR3 | | BAR3 |
836 * +-----------------+ +-----------------+
837 * | BAR4 | | BAR4 |
838 * +-----------------+ +-----------------+
839 * | BAR5 | | BAR5 |
840 * +-----------------+ +-----------------+
841 * EP CONTROLLER 1 EP CONTROLLER 2
842 *
843 * Clear BAR0 of EP CONTROLLER 1 which contains the HOST1's config and
844 * self scratchpad region (removes inbound ATU configuration). While BAR0 is
845 * the default self scratchpad BAR, an NTB could have other BARs for self
846 * scratchpad (because of reserved BARs). This function can get the exact BAR
847 * used for self scratchpad from epf_ntb_bar[BAR_CONFIG].
848 *
849 * Please note the self scratchpad region and config region is combined to
850 * a single region and mapped using the same BAR. Also note HOST2's peer
851 * scratchpad is HOST1's self scratchpad.
852 */
epf_ntb_config_sspad_bar_clear(struct epf_ntb_epc * ntb_epc)853 static void epf_ntb_config_sspad_bar_clear(struct epf_ntb_epc *ntb_epc)
854 {
855 struct pci_epf_bar *epf_bar;
856 enum pci_barno barno;
857 u8 func_no, vfunc_no;
858 struct pci_epc *epc;
859
860 epc = ntb_epc->epc;
861 func_no = ntb_epc->func_no;
862 vfunc_no = ntb_epc->vfunc_no;
863 barno = ntb_epc->epf_ntb_bar[BAR_CONFIG];
864 epf_bar = &ntb_epc->epf_bar[barno];
865 pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar);
866 }
867
868 /**
869 * epf_ntb_config_sspad_bar_set() - Set Config + Self scratchpad BAR
870 * @ntb_epc: EPC associated with one of the HOST which holds peer's outbound
871 * address.
872 *
873 * +-----------------+------->+------------------+ +-----------------+
874 * | BAR0 | | CONFIG REGION | | BAR0 |
875 * +-----------------+----+ +------------------+<-------+-----------------+
876 * | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
877 * +-----------------+ +-->+------------------+<-------+-----------------+
878 * | BAR2 | Local Memory | BAR2 |
879 * +-----------------+ +-----------------+
880 * | BAR3 | | BAR3 |
881 * +-----------------+ +-----------------+
882 * | BAR4 | | BAR4 |
883 * +-----------------+ +-----------------+
884 * | BAR5 | | BAR5 |
885 * +-----------------+ +-----------------+
886 * EP CONTROLLER 1 EP CONTROLLER 2
887 *
888 * Map BAR0 of EP CONTROLLER 1 which contains the HOST1's config and
889 * self scratchpad region. While BAR0 is the default self scratchpad BAR, an
890 * NTB could have other BARs for self scratchpad (because of reserved BARs).
891 * This function can get the exact BAR used for self scratchpad from
892 * epf_ntb_bar[BAR_CONFIG].
893 *
894 * Please note the self scratchpad region and config region is combined to
895 * a single region and mapped using the same BAR. Also note HOST2's peer
896 * scratchpad is HOST1's self scratchpad.
897 */
epf_ntb_config_sspad_bar_set(struct epf_ntb_epc * ntb_epc)898 static int epf_ntb_config_sspad_bar_set(struct epf_ntb_epc *ntb_epc)
899 {
900 struct pci_epf_bar *epf_bar;
901 enum pci_barno barno;
902 u8 func_no, vfunc_no;
903 struct epf_ntb *ntb;
904 struct pci_epc *epc;
905 struct device *dev;
906 int ret;
907
908 ntb = ntb_epc->epf_ntb;
909 dev = &ntb->epf->dev;
910
911 epc = ntb_epc->epc;
912 func_no = ntb_epc->func_no;
913 vfunc_no = ntb_epc->vfunc_no;
914 barno = ntb_epc->epf_ntb_bar[BAR_CONFIG];
915 epf_bar = &ntb_epc->epf_bar[barno];
916
917 ret = pci_epc_set_bar(epc, func_no, vfunc_no, epf_bar);
918 if (ret) {
919 dev_err(dev, "%s inft: Config/Status/SPAD BAR set failed\n",
920 pci_epc_interface_string(ntb_epc->type));
921 return ret;
922 }
923
924 return 0;
925 }
926
927 /**
928 * epf_ntb_config_spad_bar_free() - Free the physical memory associated with
929 * config + scratchpad region
930 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
931 *
932 * +-----------------+------->+------------------+ +-----------------+
933 * | BAR0 | | CONFIG REGION | | BAR0 |
934 * +-----------------+----+ +------------------+<-------+-----------------+
935 * | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
936 * +-----------------+ +-->+------------------+<-------+-----------------+
937 * | BAR2 | Local Memory | BAR2 |
938 * +-----------------+ +-----------------+
939 * | BAR3 | | BAR3 |
940 * +-----------------+ +-----------------+
941 * | BAR4 | | BAR4 |
942 * +-----------------+ +-----------------+
943 * | BAR5 | | BAR5 |
944 * +-----------------+ +-----------------+
945 * EP CONTROLLER 1 EP CONTROLLER 2
946 *
947 * Free the Local Memory mentioned in the above diagram. After invoking this
948 * function, any of config + self scratchpad region of HOST1 or peer scratchpad
949 * region of HOST2 should not be accessed.
950 */
epf_ntb_config_spad_bar_free(struct epf_ntb * ntb)951 static void epf_ntb_config_spad_bar_free(struct epf_ntb *ntb)
952 {
953 enum pci_epc_interface_type type;
954 struct epf_ntb_epc *ntb_epc;
955 enum pci_barno barno;
956 struct pci_epf *epf;
957
958 epf = ntb->epf;
959 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) {
960 ntb_epc = ntb->epc[type];
961 barno = ntb_epc->epf_ntb_bar[BAR_CONFIG];
962 if (ntb_epc->reg)
963 pci_epf_free_space(epf, ntb_epc->reg, barno, type);
964 }
965 }
966
967 /**
968 * epf_ntb_config_spad_bar_alloc() - Allocate memory for config + scratchpad
969 * region
970 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
971 * @type: PRIMARY interface or SECONDARY interface
972 *
973 * +-----------------+------->+------------------+ +-----------------+
974 * | BAR0 | | CONFIG REGION | | BAR0 |
975 * +-----------------+----+ +------------------+<-------+-----------------+
976 * | BAR1 | | |SCRATCHPAD REGION | | BAR1 |
977 * +-----------------+ +-->+------------------+<-------+-----------------+
978 * | BAR2 | Local Memory | BAR2 |
979 * +-----------------+ +-----------------+
980 * | BAR3 | | BAR3 |
981 * +-----------------+ +-----------------+
982 * | BAR4 | | BAR4 |
983 * +-----------------+ +-----------------+
984 * | BAR5 | | BAR5 |
985 * +-----------------+ +-----------------+
986 * EP CONTROLLER 1 EP CONTROLLER 2
987 *
988 * Allocate the Local Memory mentioned in the above diagram. The size of
989 * CONFIG REGION is sizeof(struct epf_ntb_ctrl) and size of SCRATCHPAD REGION
990 * is obtained from "spad-count" configfs entry.
991 *
992 * The size of both config region and scratchpad region has to be aligned,
993 * since the scratchpad region will also be mapped as PEER SCRATCHPAD of
994 * other host using a separate BAR.
995 */
epf_ntb_config_spad_bar_alloc(struct epf_ntb * ntb,enum pci_epc_interface_type type)996 static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb,
997 enum pci_epc_interface_type type)
998 {
999 const struct pci_epc_features *peer_epc_features, *epc_features;
1000 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
1001 size_t msix_table_size, pba_size, align;
1002 enum pci_barno peer_barno, barno;
1003 struct epf_ntb_ctrl *ctrl;
1004 u32 spad_size, ctrl_size;
1005 u64 size, peer_size;
1006 struct pci_epf *epf;
1007 struct device *dev;
1008 bool msix_capable;
1009 u32 spad_count;
1010 void *base;
1011
1012 epf = ntb->epf;
1013 dev = &epf->dev;
1014 ntb_epc = ntb->epc[type];
1015
1016 epc_features = ntb_epc->epc_features;
1017 barno = ntb_epc->epf_ntb_bar[BAR_CONFIG];
1018 size = epc_features->bar[barno].fixed_size;
1019 align = epc_features->align;
1020
1021 peer_ntb_epc = ntb->epc[!type];
1022 peer_epc_features = peer_ntb_epc->epc_features;
1023 peer_barno = ntb_epc->epf_ntb_bar[BAR_PEER_SPAD];
1024 peer_size = peer_epc_features->bar[peer_barno].fixed_size;
1025
1026 /* Check if epc_features is populated incorrectly */
1027 if ((!IS_ALIGNED(size, align)))
1028 return -EINVAL;
1029
1030 spad_count = ntb->spad_count;
1031
1032 ctrl_size = sizeof(struct epf_ntb_ctrl);
1033 spad_size = spad_count * 4;
1034
1035 msix_capable = epc_features->msix_capable;
1036 if (msix_capable) {
1037 msix_table_size = PCI_MSIX_ENTRY_SIZE * ntb->db_count;
1038 ctrl_size = ALIGN(ctrl_size, 8);
1039 ntb_epc->msix_table_offset = ctrl_size;
1040 ntb_epc->msix_bar = barno;
1041 /* Align to QWORD or 8 Bytes */
1042 pba_size = ALIGN(DIV_ROUND_UP(ntb->db_count, 8), 8);
1043 ctrl_size = ctrl_size + msix_table_size + pba_size;
1044 }
1045
1046 if (!align) {
1047 ctrl_size = roundup_pow_of_two(ctrl_size);
1048 spad_size = roundup_pow_of_two(spad_size);
1049 } else {
1050 ctrl_size = ALIGN(ctrl_size, align);
1051 spad_size = ALIGN(spad_size, align);
1052 }
1053
1054 if (peer_size) {
1055 if (peer_size < spad_size)
1056 spad_count = peer_size / 4;
1057 spad_size = peer_size;
1058 }
1059
1060 /*
1061 * In order to make sure SPAD offset is aligned to its size,
1062 * expand control region size to the size of SPAD if SPAD size
1063 * is greater than control region size.
1064 */
1065 if (spad_size > ctrl_size)
1066 ctrl_size = spad_size;
1067
1068 if (!size)
1069 size = ctrl_size + spad_size;
1070 else if (size < ctrl_size + spad_size)
1071 return -EINVAL;
1072
1073 base = pci_epf_alloc_space(epf, size, barno, epc_features, type);
1074 if (!base) {
1075 dev_err(dev, "%s intf: Config/Status/SPAD alloc region fail\n",
1076 pci_epc_interface_string(type));
1077 return -ENOMEM;
1078 }
1079
1080 ntb_epc->reg = base;
1081
1082 ctrl = ntb_epc->reg;
1083 ctrl->spad_offset = ctrl_size;
1084 ctrl->spad_count = spad_count;
1085 ctrl->num_mws = ntb->num_mws;
1086 ctrl->db_entry_size = align ? align : 4;
1087 ntb_epc->spad_size = spad_size;
1088
1089 return 0;
1090 }
1091
1092 /**
1093 * epf_ntb_config_spad_bar_alloc_interface() - Allocate memory for config +
1094 * scratchpad region for each of PRIMARY and SECONDARY interface
1095 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1096 *
1097 * Wrapper for epf_ntb_config_spad_bar_alloc() which allocates memory for
1098 * config + scratchpad region for a specific interface
1099 */
epf_ntb_config_spad_bar_alloc_interface(struct epf_ntb * ntb)1100 static int epf_ntb_config_spad_bar_alloc_interface(struct epf_ntb *ntb)
1101 {
1102 enum pci_epc_interface_type type;
1103 struct device *dev;
1104 int ret;
1105
1106 dev = &ntb->epf->dev;
1107
1108 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) {
1109 ret = epf_ntb_config_spad_bar_alloc(ntb, type);
1110 if (ret) {
1111 dev_err(dev, "%s intf: Config/SPAD BAR alloc failed\n",
1112 pci_epc_interface_string(type));
1113 return ret;
1114 }
1115 }
1116
1117 return 0;
1118 }
1119
1120 /**
1121 * epf_ntb_free_peer_mem() - Free memory allocated in peers outbound address
1122 * space
1123 * @ntb_epc: EPC associated with one of the HOST which holds peers outbound
1124 * address regions
1125 *
1126 * +-----------------+ +---->+----------------+-----------+-----------------+
1127 * | BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 |
1128 * +-----------------+ | +----------------+ +-----------------+
1129 * | BAR1 | | | Doorbell 2 +---------+ | |
1130 * +-----------------+----+ +----------------+ | | |
1131 * | BAR2 | | Doorbell 3 +-------+ | +-----------------+
1132 * +-----------------+----+ +----------------+ | +-> MSI|X ADDRESS 2 |
1133 * | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
1134 * +-----------------+ | |----------------+ | | | |
1135 * | BAR4 | | | | | | +-----------------+
1136 * +-----------------+ | | MW1 +---+ | +-->+ MSI|X ADDRESS 3||
1137 * | BAR5 | | | | | | +-----------------+
1138 * +-----------------+ +---->-----------------+ | | | |
1139 * EP CONTROLLER 1 | | | | +-----------------+
1140 * | | | +---->+ MSI|X ADDRESS 4 |
1141 * +----------------+ | +-----------------+
1142 * (A) EP CONTROLLER 2 | | |
1143 * (OB SPACE) | | |
1144 * +-------> MW1 |
1145 * | |
1146 * | |
1147 * (B) +-----------------+
1148 * | |
1149 * | |
1150 * | |
1151 * | |
1152 * | |
1153 * +-----------------+
1154 * PCI Address Space
1155 * (Managed by HOST2)
1156 *
1157 * Free memory allocated in EP CONTROLLER 2 (OB SPACE) in the above diagram.
1158 * It'll free Doorbell 1, Doorbell 2, Doorbell 3, Doorbell 4, MW1 (and MW2, MW3,
1159 * MW4).
1160 */
epf_ntb_free_peer_mem(struct epf_ntb_epc * ntb_epc)1161 static void epf_ntb_free_peer_mem(struct epf_ntb_epc *ntb_epc)
1162 {
1163 struct pci_epf_bar *epf_bar;
1164 void __iomem *mw_addr;
1165 phys_addr_t phys_addr;
1166 enum epf_ntb_bar bar;
1167 enum pci_barno barno;
1168 struct pci_epc *epc;
1169 size_t size;
1170
1171 epc = ntb_epc->epc;
1172
1173 for (bar = BAR_DB_MW1; bar < BAR_MW4; bar++) {
1174 barno = ntb_epc->epf_ntb_bar[bar];
1175 mw_addr = ntb_epc->mw_addr[barno];
1176 epf_bar = &ntb_epc->epf_bar[barno];
1177 phys_addr = epf_bar->phys_addr;
1178 size = epf_bar->size;
1179 if (mw_addr) {
1180 pci_epc_mem_free_addr(epc, phys_addr, mw_addr, size);
1181 ntb_epc->mw_addr[barno] = NULL;
1182 }
1183 }
1184 }
1185
1186 /**
1187 * epf_ntb_db_mw_bar_clear() - Clear doorbell and memory BAR
1188 * @ntb_epc: EPC associated with one of the HOST which holds peer's outbound
1189 * address
1190 *
1191 * +-----------------+ +---->+----------------+-----------+-----------------+
1192 * | BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 |
1193 * +-----------------+ | +----------------+ +-----------------+
1194 * | BAR1 | | | Doorbell 2 +---------+ | |
1195 * +-----------------+----+ +----------------+ | | |
1196 * | BAR2 | | Doorbell 3 +-------+ | +-----------------+
1197 * +-----------------+----+ +----------------+ | +-> MSI|X ADDRESS 2 |
1198 * | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
1199 * +-----------------+ | |----------------+ | | | |
1200 * | BAR4 | | | | | | +-----------------+
1201 * +-----------------+ | | MW1 +---+ | +-->+ MSI|X ADDRESS 3||
1202 * | BAR5 | | | | | | +-----------------+
1203 * +-----------------+ +---->-----------------+ | | | |
1204 * EP CONTROLLER 1 | | | | +-----------------+
1205 * | | | +---->+ MSI|X ADDRESS 4 |
1206 * +----------------+ | +-----------------+
1207 * (A) EP CONTROLLER 2 | | |
1208 * (OB SPACE) | | |
1209 * +-------> MW1 |
1210 * | |
1211 * | |
1212 * (B) +-----------------+
1213 * | |
1214 * | |
1215 * | |
1216 * | |
1217 * | |
1218 * +-----------------+
1219 * PCI Address Space
1220 * (Managed by HOST2)
1221 *
1222 * Clear doorbell and memory BARs (remove inbound ATU configuration). In the above
1223 * diagram it clears BAR2 TO BAR5 of EP CONTROLLER 1 (Doorbell BAR, MW1 BAR, MW2
1224 * BAR, MW3 BAR and MW4 BAR).
1225 */
epf_ntb_db_mw_bar_clear(struct epf_ntb_epc * ntb_epc)1226 static void epf_ntb_db_mw_bar_clear(struct epf_ntb_epc *ntb_epc)
1227 {
1228 struct pci_epf_bar *epf_bar;
1229 enum epf_ntb_bar bar;
1230 enum pci_barno barno;
1231 u8 func_no, vfunc_no;
1232 struct pci_epc *epc;
1233
1234 epc = ntb_epc->epc;
1235
1236 func_no = ntb_epc->func_no;
1237 vfunc_no = ntb_epc->vfunc_no;
1238
1239 for (bar = BAR_DB_MW1; bar < BAR_MW4; bar++) {
1240 barno = ntb_epc->epf_ntb_bar[bar];
1241 epf_bar = &ntb_epc->epf_bar[barno];
1242 pci_epc_clear_bar(epc, func_no, vfunc_no, epf_bar);
1243 }
1244 }
1245
1246 /**
1247 * epf_ntb_db_mw_bar_cleanup() - Clear doorbell/memory BAR and free memory
1248 * allocated in peers outbound address space
1249 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1250 * @type: PRIMARY interface or SECONDARY interface
1251 *
1252 * Wrapper for epf_ntb_db_mw_bar_clear() to clear HOST1's BAR and
1253 * epf_ntb_free_peer_mem() which frees up HOST2 outbound memory.
1254 */
epf_ntb_db_mw_bar_cleanup(struct epf_ntb * ntb,enum pci_epc_interface_type type)1255 static void epf_ntb_db_mw_bar_cleanup(struct epf_ntb *ntb,
1256 enum pci_epc_interface_type type)
1257 {
1258 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
1259
1260 ntb_epc = ntb->epc[type];
1261 peer_ntb_epc = ntb->epc[!type];
1262
1263 epf_ntb_db_mw_bar_clear(ntb_epc);
1264 epf_ntb_free_peer_mem(peer_ntb_epc);
1265 }
1266
1267 /**
1268 * epf_ntb_configure_interrupt() - Configure MSI/MSI-X capability
1269 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1270 * @type: PRIMARY interface or SECONDARY interface
1271 *
1272 * Configure MSI/MSI-X capability for each interface with number of
1273 * interrupts equal to "db_count" configfs entry.
1274 */
epf_ntb_configure_interrupt(struct epf_ntb * ntb,enum pci_epc_interface_type type)1275 static int epf_ntb_configure_interrupt(struct epf_ntb *ntb,
1276 enum pci_epc_interface_type type)
1277 {
1278 const struct pci_epc_features *epc_features;
1279 bool msix_capable, msi_capable;
1280 struct epf_ntb_epc *ntb_epc;
1281 u8 func_no, vfunc_no;
1282 struct pci_epc *epc;
1283 struct device *dev;
1284 int ret;
1285
1286 ntb_epc = ntb->epc[type];
1287 dev = &ntb->epf->dev;
1288
1289 epc_features = ntb_epc->epc_features;
1290 msix_capable = epc_features->msix_capable;
1291 msi_capable = epc_features->msi_capable;
1292
1293 if (!(msix_capable || msi_capable)) {
1294 dev_err(dev, "MSI or MSI-X is required for doorbell\n");
1295 return -EINVAL;
1296 }
1297
1298 func_no = ntb_epc->func_no;
1299 vfunc_no = ntb_epc->vfunc_no;
1300
1301 if (!ntb->db_count || ntb->db_count > MAX_DB_COUNT) {
1302 dev_err(dev, "DB count %d out of range (1 - %d)\n",
1303 ntb->db_count, MAX_DB_COUNT);
1304 return -EINVAL;
1305 }
1306
1307 epc = ntb_epc->epc;
1308
1309 if (msi_capable) {
1310 ret = pci_epc_set_msi(epc, func_no, vfunc_no, ntb->db_count);
1311 if (ret) {
1312 dev_err(dev, "%s intf: MSI configuration failed\n",
1313 pci_epc_interface_string(type));
1314 return ret;
1315 }
1316 }
1317
1318 if (msix_capable) {
1319 ret = pci_epc_set_msix(epc, func_no, vfunc_no, ntb->db_count,
1320 ntb_epc->msix_bar,
1321 ntb_epc->msix_table_offset);
1322 if (ret) {
1323 dev_err(dev, "MSI configuration failed\n");
1324 return ret;
1325 }
1326 }
1327
1328 return 0;
1329 }
1330
1331 /**
1332 * epf_ntb_alloc_peer_mem() - Allocate memory in peer's outbound address space
1333 * @dev: The PCI device.
1334 * @ntb_epc: EPC associated with one of the HOST whose BAR holds peer's outbound
1335 * address
1336 * @bar: BAR of @ntb_epc in for which memory has to be allocated (could be
1337 * BAR_DB_MW1, BAR_MW2, BAR_MW3, BAR_MW4)
1338 * @peer_ntb_epc: EPC associated with HOST whose outbound address space is
1339 * used by @ntb_epc
1340 * @size: Size of the address region that has to be allocated in peers OB SPACE
1341 *
1342 *
1343 * +-----------------+ +---->+----------------+-----------+-----------------+
1344 * | BAR0 | | | Doorbell 1 +-----------> MSI|X ADDRESS 1 |
1345 * +-----------------+ | +----------------+ +-----------------+
1346 * | BAR1 | | | Doorbell 2 +---------+ | |
1347 * +-----------------+----+ +----------------+ | | |
1348 * | BAR2 | | Doorbell 3 +-------+ | +-----------------+
1349 * +-----------------+----+ +----------------+ | +-> MSI|X ADDRESS 2 |
1350 * | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
1351 * +-----------------+ | |----------------+ | | | |
1352 * | BAR4 | | | | | | +-----------------+
1353 * +-----------------+ | | MW1 +---+ | +-->+ MSI|X ADDRESS 3||
1354 * | BAR5 | | | | | | +-----------------+
1355 * +-----------------+ +---->-----------------+ | | | |
1356 * EP CONTROLLER 1 | | | | +-----------------+
1357 * | | | +---->+ MSI|X ADDRESS 4 |
1358 * +----------------+ | +-----------------+
1359 * (A) EP CONTROLLER 2 | | |
1360 * (OB SPACE) | | |
1361 * +-------> MW1 |
1362 * | |
1363 * | |
1364 * (B) +-----------------+
1365 * | |
1366 * | |
1367 * | |
1368 * | |
1369 * | |
1370 * +-----------------+
1371 * PCI Address Space
1372 * (Managed by HOST2)
1373 *
1374 * Allocate memory in OB space of EP CONTROLLER 2 in the above diagram. Allocate
1375 * for Doorbell 1, Doorbell 2, Doorbell 3, Doorbell 4, MW1 (and MW2, MW3, MW4).
1376 */
epf_ntb_alloc_peer_mem(struct device * dev,struct epf_ntb_epc * ntb_epc,enum epf_ntb_bar bar,struct epf_ntb_epc * peer_ntb_epc,size_t size)1377 static int epf_ntb_alloc_peer_mem(struct device *dev,
1378 struct epf_ntb_epc *ntb_epc,
1379 enum epf_ntb_bar bar,
1380 struct epf_ntb_epc *peer_ntb_epc,
1381 size_t size)
1382 {
1383 const struct pci_epc_features *epc_features;
1384 struct pci_epf_bar *epf_bar;
1385 struct pci_epc *peer_epc;
1386 phys_addr_t phys_addr;
1387 void __iomem *mw_addr;
1388 enum pci_barno barno;
1389 size_t align;
1390
1391 epc_features = ntb_epc->epc_features;
1392 align = epc_features->align;
1393
1394 if (size < 128)
1395 size = 128;
1396
1397 if (align)
1398 size = ALIGN(size, align);
1399 else
1400 size = roundup_pow_of_two(size);
1401
1402 peer_epc = peer_ntb_epc->epc;
1403 mw_addr = pci_epc_mem_alloc_addr(peer_epc, &phys_addr, size);
1404 if (!mw_addr) {
1405 dev_err(dev, "%s intf: Failed to allocate OB address\n",
1406 pci_epc_interface_string(peer_ntb_epc->type));
1407 return -ENOMEM;
1408 }
1409
1410 barno = ntb_epc->epf_ntb_bar[bar];
1411 epf_bar = &ntb_epc->epf_bar[barno];
1412 ntb_epc->mw_addr[barno] = mw_addr;
1413
1414 epf_bar->phys_addr = phys_addr;
1415 epf_bar->size = size;
1416 epf_bar->barno = barno;
1417 epf_bar->flags = PCI_BASE_ADDRESS_MEM_TYPE_32;
1418
1419 return 0;
1420 }
1421
1422 /**
1423 * epf_ntb_db_mw_bar_init() - Configure Doorbell and Memory window BARs
1424 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1425 * @type: PRIMARY interface or SECONDARY interface
1426 *
1427 * Wrapper for epf_ntb_alloc_peer_mem() and pci_epc_set_bar() that allocates
1428 * memory in OB address space of HOST2 and configures BAR of HOST1
1429 */
epf_ntb_db_mw_bar_init(struct epf_ntb * ntb,enum pci_epc_interface_type type)1430 static int epf_ntb_db_mw_bar_init(struct epf_ntb *ntb,
1431 enum pci_epc_interface_type type)
1432 {
1433 const struct pci_epc_features *epc_features;
1434 struct epf_ntb_epc *peer_ntb_epc, *ntb_epc;
1435 struct pci_epf_bar *epf_bar;
1436 struct epf_ntb_ctrl *ctrl;
1437 u32 num_mws, db_count;
1438 enum epf_ntb_bar bar;
1439 enum pci_barno barno;
1440 u8 func_no, vfunc_no;
1441 struct pci_epc *epc;
1442 struct device *dev;
1443 size_t align;
1444 int ret, i;
1445 u64 size;
1446
1447 ntb_epc = ntb->epc[type];
1448 peer_ntb_epc = ntb->epc[!type];
1449
1450 dev = &ntb->epf->dev;
1451 epc_features = ntb_epc->epc_features;
1452 align = epc_features->align;
1453 func_no = ntb_epc->func_no;
1454 vfunc_no = ntb_epc->vfunc_no;
1455 epc = ntb_epc->epc;
1456 num_mws = ntb->num_mws;
1457 db_count = ntb->db_count;
1458
1459 for (bar = BAR_DB_MW1, i = 0; i < num_mws; bar++, i++) {
1460 if (bar == BAR_DB_MW1) {
1461 align = align ? align : 4;
1462 size = db_count * align;
1463 size = ALIGN(size, ntb->mws_size[i]);
1464 ctrl = ntb_epc->reg;
1465 ctrl->mw1_offset = size;
1466 size += ntb->mws_size[i];
1467 } else {
1468 size = ntb->mws_size[i];
1469 }
1470
1471 ret = epf_ntb_alloc_peer_mem(dev, ntb_epc, bar,
1472 peer_ntb_epc, size);
1473 if (ret) {
1474 dev_err(dev, "%s intf: DoorBell mem alloc failed\n",
1475 pci_epc_interface_string(type));
1476 goto err_alloc_peer_mem;
1477 }
1478
1479 barno = ntb_epc->epf_ntb_bar[bar];
1480 epf_bar = &ntb_epc->epf_bar[barno];
1481
1482 ret = pci_epc_set_bar(epc, func_no, vfunc_no, epf_bar);
1483 if (ret) {
1484 dev_err(dev, "%s intf: DoorBell BAR set failed\n",
1485 pci_epc_interface_string(type));
1486 goto err_alloc_peer_mem;
1487 }
1488 }
1489
1490 return 0;
1491
1492 err_alloc_peer_mem:
1493 epf_ntb_db_mw_bar_cleanup(ntb, type);
1494
1495 return ret;
1496 }
1497
1498 /**
1499 * epf_ntb_epc_create_interface() - Create and initialize NTB EPC interface
1500 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1501 * @epc: struct pci_epc to which a particular NTB interface should be associated
1502 * @type: PRIMARY interface or SECONDARY interface
1503 *
1504 * Allocate memory for NTB EPC interface and initialize it.
1505 */
epf_ntb_epc_create_interface(struct epf_ntb * ntb,struct pci_epc * epc,enum pci_epc_interface_type type)1506 static int epf_ntb_epc_create_interface(struct epf_ntb *ntb,
1507 struct pci_epc *epc,
1508 enum pci_epc_interface_type type)
1509 {
1510 const struct pci_epc_features *epc_features;
1511 struct pci_epf_bar *epf_bar;
1512 struct epf_ntb_epc *ntb_epc;
1513 u8 func_no, vfunc_no;
1514 struct pci_epf *epf;
1515 struct device *dev;
1516
1517 dev = &ntb->epf->dev;
1518
1519 ntb_epc = devm_kzalloc(dev, sizeof(*ntb_epc), GFP_KERNEL);
1520 if (!ntb_epc)
1521 return -ENOMEM;
1522
1523 epf = ntb->epf;
1524 vfunc_no = epf->vfunc_no;
1525 if (type == PRIMARY_INTERFACE) {
1526 func_no = epf->func_no;
1527 epf_bar = epf->bar;
1528 } else {
1529 func_no = epf->sec_epc_func_no;
1530 epf_bar = epf->sec_epc_bar;
1531 }
1532
1533 ntb_epc->linkup = false;
1534 ntb_epc->epc = epc;
1535 ntb_epc->func_no = func_no;
1536 ntb_epc->vfunc_no = vfunc_no;
1537 ntb_epc->type = type;
1538 ntb_epc->epf_bar = epf_bar;
1539 ntb_epc->epf_ntb = ntb;
1540
1541 epc_features = pci_epc_get_features(epc, func_no, vfunc_no);
1542 if (!epc_features)
1543 return -EINVAL;
1544 ntb_epc->epc_features = epc_features;
1545
1546 ntb->epc[type] = ntb_epc;
1547
1548 return 0;
1549 }
1550
1551 /**
1552 * epf_ntb_epc_create() - Create and initialize NTB EPC interface
1553 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1554 *
1555 * Get a reference to EPC device and bind NTB function device to that EPC
1556 * for each of the interface. It is also a wrapper to
1557 * epf_ntb_epc_create_interface() to allocate memory for NTB EPC interface
1558 * and initialize it
1559 */
epf_ntb_epc_create(struct epf_ntb * ntb)1560 static int epf_ntb_epc_create(struct epf_ntb *ntb)
1561 {
1562 struct pci_epf *epf;
1563 struct device *dev;
1564 int ret;
1565
1566 epf = ntb->epf;
1567 dev = &epf->dev;
1568
1569 ret = epf_ntb_epc_create_interface(ntb, epf->epc, PRIMARY_INTERFACE);
1570 if (ret) {
1571 dev_err(dev, "PRIMARY intf: Fail to create NTB EPC\n");
1572 return ret;
1573 }
1574
1575 ret = epf_ntb_epc_create_interface(ntb, epf->sec_epc,
1576 SECONDARY_INTERFACE);
1577 if (ret)
1578 dev_err(dev, "SECONDARY intf: Fail to create NTB EPC\n");
1579
1580 return ret;
1581 }
1582
1583 /**
1584 * epf_ntb_init_epc_bar_interface() - Identify BARs to be used for each of
1585 * the NTB constructs (scratchpad region, doorbell, memorywindow)
1586 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1587 * @type: PRIMARY interface or SECONDARY interface
1588 *
1589 * Identify the free BARs to be used for each of BAR_CONFIG, BAR_PEER_SPAD,
1590 * BAR_DB_MW1, BAR_MW2, BAR_MW3 and BAR_MW4.
1591 */
epf_ntb_init_epc_bar_interface(struct epf_ntb * ntb,enum pci_epc_interface_type type)1592 static int epf_ntb_init_epc_bar_interface(struct epf_ntb *ntb,
1593 enum pci_epc_interface_type type)
1594 {
1595 const struct pci_epc_features *epc_features;
1596 struct epf_ntb_epc *ntb_epc;
1597 enum pci_barno barno;
1598 enum epf_ntb_bar bar;
1599 struct device *dev;
1600 u32 num_mws;
1601 int i;
1602
1603 barno = BAR_0;
1604 ntb_epc = ntb->epc[type];
1605 num_mws = ntb->num_mws;
1606 dev = &ntb->epf->dev;
1607 epc_features = ntb_epc->epc_features;
1608
1609 /* These are required BARs which are mandatory for NTB functionality */
1610 for (bar = BAR_CONFIG; bar <= BAR_DB_MW1; bar++, barno++) {
1611 barno = pci_epc_get_next_free_bar(epc_features, barno);
1612 if (barno < 0) {
1613 dev_err(dev, "%s intf: Fail to get NTB function BAR\n",
1614 pci_epc_interface_string(type));
1615 return barno;
1616 }
1617 ntb_epc->epf_ntb_bar[bar] = barno;
1618 }
1619
1620 /* These are optional BARs which don't impact NTB functionality */
1621 for (bar = BAR_MW2, i = 1; i < num_mws; bar++, barno++, i++) {
1622 barno = pci_epc_get_next_free_bar(epc_features, barno);
1623 if (barno < 0) {
1624 ntb->num_mws = i;
1625 dev_dbg(dev, "BAR not available for > MW%d\n", i + 1);
1626 }
1627 ntb_epc->epf_ntb_bar[bar] = barno;
1628 }
1629
1630 return 0;
1631 }
1632
1633 /**
1634 * epf_ntb_init_epc_bar() - Identify BARs to be used for each of the NTB
1635 * constructs (scratchpad region, doorbell, memorywindow)
1636 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1637 *
1638 * Wrapper to epf_ntb_init_epc_bar_interface() to identify the free BARs
1639 * to be used for each of BAR_CONFIG, BAR_PEER_SPAD, BAR_DB_MW1, BAR_MW2,
1640 * BAR_MW3 and BAR_MW4 for all the interfaces.
1641 */
epf_ntb_init_epc_bar(struct epf_ntb * ntb)1642 static int epf_ntb_init_epc_bar(struct epf_ntb *ntb)
1643 {
1644 enum pci_epc_interface_type type;
1645 struct device *dev;
1646 int ret;
1647
1648 dev = &ntb->epf->dev;
1649 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) {
1650 ret = epf_ntb_init_epc_bar_interface(ntb, type);
1651 if (ret) {
1652 dev_err(dev, "Fail to init EPC bar for %s interface\n",
1653 pci_epc_interface_string(type));
1654 return ret;
1655 }
1656 }
1657
1658 return 0;
1659 }
1660
1661 /**
1662 * epf_ntb_epc_init_interface() - Initialize NTB interface
1663 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1664 * @type: PRIMARY interface or SECONDARY interface
1665 *
1666 * Wrapper to initialize a particular EPC interface and start the workqueue
1667 * to check for commands from host. This function will write to the
1668 * EP controller HW for configuring it.
1669 */
epf_ntb_epc_init_interface(struct epf_ntb * ntb,enum pci_epc_interface_type type)1670 static int epf_ntb_epc_init_interface(struct epf_ntb *ntb,
1671 enum pci_epc_interface_type type)
1672 {
1673 struct epf_ntb_epc *ntb_epc;
1674 u8 func_no, vfunc_no;
1675 struct pci_epc *epc;
1676 struct pci_epf *epf;
1677 struct device *dev;
1678 int ret;
1679
1680 ntb_epc = ntb->epc[type];
1681 epf = ntb->epf;
1682 dev = &epf->dev;
1683 epc = ntb_epc->epc;
1684 func_no = ntb_epc->func_no;
1685 vfunc_no = ntb_epc->vfunc_no;
1686
1687 ret = epf_ntb_config_sspad_bar_set(ntb->epc[type]);
1688 if (ret) {
1689 dev_err(dev, "%s intf: Config/self SPAD BAR init failed\n",
1690 pci_epc_interface_string(type));
1691 return ret;
1692 }
1693
1694 ret = epf_ntb_peer_spad_bar_set(ntb, type);
1695 if (ret) {
1696 dev_err(dev, "%s intf: Peer SPAD BAR init failed\n",
1697 pci_epc_interface_string(type));
1698 goto err_peer_spad_bar_init;
1699 }
1700
1701 ret = epf_ntb_configure_interrupt(ntb, type);
1702 if (ret) {
1703 dev_err(dev, "%s intf: Interrupt configuration failed\n",
1704 pci_epc_interface_string(type));
1705 goto err_peer_spad_bar_init;
1706 }
1707
1708 ret = epf_ntb_db_mw_bar_init(ntb, type);
1709 if (ret) {
1710 dev_err(dev, "%s intf: DB/MW BAR init failed\n",
1711 pci_epc_interface_string(type));
1712 goto err_db_mw_bar_init;
1713 }
1714
1715 if (vfunc_no <= 1) {
1716 ret = pci_epc_write_header(epc, func_no, vfunc_no, epf->header);
1717 if (ret) {
1718 dev_err(dev, "%s intf: Configuration header write failed\n",
1719 pci_epc_interface_string(type));
1720 goto err_write_header;
1721 }
1722 }
1723
1724 INIT_DELAYED_WORK(&ntb->epc[type]->cmd_handler, epf_ntb_cmd_handler);
1725 queue_work(kpcintb_workqueue, &ntb->epc[type]->cmd_handler.work);
1726
1727 return 0;
1728
1729 err_write_header:
1730 epf_ntb_db_mw_bar_cleanup(ntb, type);
1731
1732 err_db_mw_bar_init:
1733 epf_ntb_peer_spad_bar_clear(ntb->epc[type]);
1734
1735 err_peer_spad_bar_init:
1736 epf_ntb_config_sspad_bar_clear(ntb->epc[type]);
1737
1738 return ret;
1739 }
1740
1741 /**
1742 * epf_ntb_epc_cleanup_interface() - Cleanup NTB interface
1743 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1744 * @type: PRIMARY interface or SECONDARY interface
1745 *
1746 * Wrapper to cleanup a particular NTB interface.
1747 */
epf_ntb_epc_cleanup_interface(struct epf_ntb * ntb,enum pci_epc_interface_type type)1748 static void epf_ntb_epc_cleanup_interface(struct epf_ntb *ntb,
1749 enum pci_epc_interface_type type)
1750 {
1751 struct epf_ntb_epc *ntb_epc;
1752
1753 if (type < 0)
1754 return;
1755
1756 ntb_epc = ntb->epc[type];
1757 cancel_delayed_work(&ntb_epc->cmd_handler);
1758 epf_ntb_db_mw_bar_cleanup(ntb, type);
1759 epf_ntb_peer_spad_bar_clear(ntb_epc);
1760 epf_ntb_config_sspad_bar_clear(ntb_epc);
1761 }
1762
1763 /**
1764 * epf_ntb_epc_cleanup() - Cleanup all NTB interfaces
1765 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1766 *
1767 * Wrapper to cleanup all NTB interfaces.
1768 */
epf_ntb_epc_cleanup(struct epf_ntb * ntb)1769 static void epf_ntb_epc_cleanup(struct epf_ntb *ntb)
1770 {
1771 enum pci_epc_interface_type type;
1772
1773 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++)
1774 epf_ntb_epc_cleanup_interface(ntb, type);
1775 }
1776
1777 /**
1778 * epf_ntb_epc_init() - Initialize all NTB interfaces
1779 * @ntb: NTB device that facilitates communication between HOST1 and HOST2
1780 *
1781 * Wrapper to initialize all NTB interface and start the workqueue
1782 * to check for commands from host.
1783 */
epf_ntb_epc_init(struct epf_ntb * ntb)1784 static int epf_ntb_epc_init(struct epf_ntb *ntb)
1785 {
1786 enum pci_epc_interface_type type;
1787 struct device *dev;
1788 int ret;
1789
1790 dev = &ntb->epf->dev;
1791
1792 for (type = PRIMARY_INTERFACE; type <= SECONDARY_INTERFACE; type++) {
1793 ret = epf_ntb_epc_init_interface(ntb, type);
1794 if (ret) {
1795 dev_err(dev, "%s intf: Failed to initialize\n",
1796 pci_epc_interface_string(type));
1797 goto err_init_type;
1798 }
1799 }
1800
1801 return 0;
1802
1803 err_init_type:
1804 epf_ntb_epc_cleanup_interface(ntb, type - 1);
1805
1806 return ret;
1807 }
1808
1809 /**
1810 * epf_ntb_bind() - Initialize endpoint controller to provide NTB functionality
1811 * @epf: NTB endpoint function device
1812 *
1813 * Initialize both the endpoint controllers associated with NTB function device.
1814 * Invoked when a primary interface or secondary interface is bound to EPC
1815 * device. This function will succeed only when EPC is bound to both the
1816 * interfaces.
1817 */
epf_ntb_bind(struct pci_epf * epf)1818 static int epf_ntb_bind(struct pci_epf *epf)
1819 {
1820 struct epf_ntb *ntb = epf_get_drvdata(epf);
1821 struct device *dev = &epf->dev;
1822 int ret;
1823
1824 if (!epf->epc) {
1825 dev_dbg(dev, "PRIMARY EPC interface not yet bound\n");
1826 return 0;
1827 }
1828
1829 if (!epf->sec_epc) {
1830 dev_dbg(dev, "SECONDARY EPC interface not yet bound\n");
1831 return 0;
1832 }
1833
1834 ret = epf_ntb_epc_create(ntb);
1835 if (ret) {
1836 dev_err(dev, "Failed to create NTB EPC\n");
1837 return ret;
1838 }
1839
1840 ret = epf_ntb_init_epc_bar(ntb);
1841 if (ret) {
1842 dev_err(dev, "Failed to create NTB EPC\n");
1843 return ret;
1844 }
1845
1846 ret = epf_ntb_config_spad_bar_alloc_interface(ntb);
1847 if (ret) {
1848 dev_err(dev, "Failed to allocate BAR memory\n");
1849 goto err_bar_alloc;
1850 }
1851
1852 ret = epf_ntb_epc_init(ntb);
1853 if (ret) {
1854 dev_err(dev, "Failed to initialize EPC\n");
1855 goto err_bar_alloc;
1856 }
1857
1858 epf_set_drvdata(epf, ntb);
1859
1860 return 0;
1861
1862 err_bar_alloc:
1863 epf_ntb_config_spad_bar_free(ntb);
1864
1865 return ret;
1866 }
1867
1868 /**
1869 * epf_ntb_unbind() - Cleanup the initialization from epf_ntb_bind()
1870 * @epf: NTB endpoint function device
1871 *
1872 * Cleanup the initialization from epf_ntb_bind()
1873 */
epf_ntb_unbind(struct pci_epf * epf)1874 static void epf_ntb_unbind(struct pci_epf *epf)
1875 {
1876 struct epf_ntb *ntb = epf_get_drvdata(epf);
1877
1878 epf_ntb_epc_cleanup(ntb);
1879 epf_ntb_config_spad_bar_free(ntb);
1880 }
1881
1882 #define EPF_NTB_R(_name) \
1883 static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
1884 char *page) \
1885 { \
1886 struct config_group *group = to_config_group(item); \
1887 struct epf_ntb *ntb = to_epf_ntb(group); \
1888 \
1889 return sysfs_emit(page, "%d\n", ntb->_name); \
1890 }
1891
1892 #define EPF_NTB_W(_name) \
1893 static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
1894 const char *page, size_t len) \
1895 { \
1896 struct config_group *group = to_config_group(item); \
1897 struct epf_ntb *ntb = to_epf_ntb(group); \
1898 u32 val; \
1899 \
1900 if (kstrtou32(page, 0, &val) < 0) \
1901 return -EINVAL; \
1902 \
1903 ntb->_name = val; \
1904 \
1905 return len; \
1906 }
1907
1908 #define EPF_NTB_MW_R(_name) \
1909 static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
1910 char *page) \
1911 { \
1912 struct config_group *group = to_config_group(item); \
1913 struct epf_ntb *ntb = to_epf_ntb(group); \
1914 int win_no; \
1915 \
1916 sscanf(#_name, "mw%d", &win_no); \
1917 \
1918 return sysfs_emit(page, "%lld\n", ntb->mws_size[win_no - 1]); \
1919 }
1920
1921 #define EPF_NTB_MW_W(_name) \
1922 static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
1923 const char *page, size_t len) \
1924 { \
1925 struct config_group *group = to_config_group(item); \
1926 struct epf_ntb *ntb = to_epf_ntb(group); \
1927 struct device *dev = &ntb->epf->dev; \
1928 int win_no; \
1929 u64 val; \
1930 \
1931 if (kstrtou64(page, 0, &val) < 0) \
1932 return -EINVAL; \
1933 \
1934 if (sscanf(#_name, "mw%d", &win_no) != 1) \
1935 return -EINVAL; \
1936 \
1937 if (ntb->num_mws < win_no) { \
1938 dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \
1939 return -EINVAL; \
1940 } \
1941 \
1942 ntb->mws_size[win_no - 1] = val; \
1943 \
1944 return len; \
1945 }
1946
epf_ntb_num_mws_store(struct config_item * item,const char * page,size_t len)1947 static ssize_t epf_ntb_num_mws_store(struct config_item *item,
1948 const char *page, size_t len)
1949 {
1950 struct config_group *group = to_config_group(item);
1951 struct epf_ntb *ntb = to_epf_ntb(group);
1952 u32 val;
1953
1954 if (kstrtou32(page, 0, &val) < 0)
1955 return -EINVAL;
1956
1957 if (val > MAX_MW)
1958 return -EINVAL;
1959
1960 ntb->num_mws = val;
1961
1962 return len;
1963 }
1964
1965 EPF_NTB_R(spad_count)
1966 EPF_NTB_W(spad_count)
1967 EPF_NTB_R(db_count)
1968 EPF_NTB_W(db_count)
1969 EPF_NTB_R(num_mws)
1970 EPF_NTB_MW_R(mw1)
1971 EPF_NTB_MW_W(mw1)
1972 EPF_NTB_MW_R(mw2)
1973 EPF_NTB_MW_W(mw2)
1974 EPF_NTB_MW_R(mw3)
1975 EPF_NTB_MW_W(mw3)
1976 EPF_NTB_MW_R(mw4)
1977 EPF_NTB_MW_W(mw4)
1978
1979 CONFIGFS_ATTR(epf_ntb_, spad_count);
1980 CONFIGFS_ATTR(epf_ntb_, db_count);
1981 CONFIGFS_ATTR(epf_ntb_, num_mws);
1982 CONFIGFS_ATTR(epf_ntb_, mw1);
1983 CONFIGFS_ATTR(epf_ntb_, mw2);
1984 CONFIGFS_ATTR(epf_ntb_, mw3);
1985 CONFIGFS_ATTR(epf_ntb_, mw4);
1986
1987 static struct configfs_attribute *epf_ntb_attrs[] = {
1988 &epf_ntb_attr_spad_count,
1989 &epf_ntb_attr_db_count,
1990 &epf_ntb_attr_num_mws,
1991 &epf_ntb_attr_mw1,
1992 &epf_ntb_attr_mw2,
1993 &epf_ntb_attr_mw3,
1994 &epf_ntb_attr_mw4,
1995 NULL,
1996 };
1997
1998 static const struct config_item_type ntb_group_type = {
1999 .ct_attrs = epf_ntb_attrs,
2000 .ct_owner = THIS_MODULE,
2001 };
2002
2003 /**
2004 * epf_ntb_add_cfs() - Add configfs directory specific to NTB
2005 * @epf: NTB endpoint function device
2006 * @group: A pointer to the config_group structure referencing a group of
2007 * config_items of a specific type that belong to a specific sub-system.
2008 *
2009 * Add configfs directory specific to NTB. This directory will hold
2010 * NTB specific properties like db_count, spad_count, num_mws etc.,
2011 */
epf_ntb_add_cfs(struct pci_epf * epf,struct config_group * group)2012 static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf,
2013 struct config_group *group)
2014 {
2015 struct epf_ntb *ntb = epf_get_drvdata(epf);
2016 struct config_group *ntb_group = &ntb->group;
2017 struct device *dev = &epf->dev;
2018
2019 config_group_init_type_name(ntb_group, dev_name(dev), &ntb_group_type);
2020
2021 return ntb_group;
2022 }
2023
2024 /**
2025 * epf_ntb_probe() - Probe NTB function driver
2026 * @epf: NTB endpoint function device
2027 * @id: NTB endpoint function device ID
2028 *
2029 * Probe NTB function driver when endpoint function bus detects a NTB
2030 * endpoint function.
2031 */
epf_ntb_probe(struct pci_epf * epf,const struct pci_epf_device_id * id)2032 static int epf_ntb_probe(struct pci_epf *epf,
2033 const struct pci_epf_device_id *id)
2034 {
2035 struct epf_ntb *ntb;
2036 struct device *dev;
2037
2038 dev = &epf->dev;
2039
2040 ntb = devm_kzalloc(dev, sizeof(*ntb), GFP_KERNEL);
2041 if (!ntb)
2042 return -ENOMEM;
2043
2044 epf->header = &epf_ntb_header;
2045 ntb->epf = epf;
2046 epf_set_drvdata(epf, ntb);
2047
2048 return 0;
2049 }
2050
2051 static const struct pci_epf_ops epf_ntb_ops = {
2052 .bind = epf_ntb_bind,
2053 .unbind = epf_ntb_unbind,
2054 .add_cfs = epf_ntb_add_cfs,
2055 };
2056
2057 static const struct pci_epf_device_id epf_ntb_ids[] = {
2058 {
2059 .name = "pci_epf_ntb",
2060 },
2061 {},
2062 };
2063
2064 static struct pci_epf_driver epf_ntb_driver = {
2065 .driver.name = "pci_epf_ntb",
2066 .probe = epf_ntb_probe,
2067 .id_table = epf_ntb_ids,
2068 .ops = &epf_ntb_ops,
2069 .owner = THIS_MODULE,
2070 };
2071
epf_ntb_init(void)2072 static int __init epf_ntb_init(void)
2073 {
2074 int ret;
2075
2076 kpcintb_workqueue = alloc_workqueue("kpcintb",
2077 WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_PERCPU, 0);
2078 if (!kpcintb_workqueue) {
2079 pr_err("Failed to allocate kpcintb workqueue\n");
2080 return -ENOMEM;
2081 }
2082
2083 ret = pci_epf_register_driver(&epf_ntb_driver);
2084 if (ret) {
2085 destroy_workqueue(kpcintb_workqueue);
2086 pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
2087 return ret;
2088 }
2089
2090 return 0;
2091 }
2092 module_init(epf_ntb_init);
2093
epf_ntb_exit(void)2094 static void __exit epf_ntb_exit(void)
2095 {
2096 pci_epf_unregister_driver(&epf_ntb_driver);
2097 destroy_workqueue(kpcintb_workqueue);
2098 }
2099 module_exit(epf_ntb_exit);
2100
2101 MODULE_DESCRIPTION("PCI EPF NTB DRIVER");
2102 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
2103 MODULE_LICENSE("GPL v2");
2104