1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver
4 * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver
5 * AD3532R/AD3532 16-channel, 16-bit Voltage Output DAC Driver
6 *
7 * Copyright 2025 Analog Devices Inc.
8 */
9
10 #include <linux/array_size.h>
11 #include <linux/bitfield.h>
12 #include <linux/bits.h>
13 #include <linux/cleanup.h>
14 #include <linux/delay.h>
15 #include <linux/dev_printk.h>
16 #include <linux/err.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/iio/iio.h>
19 #include <linux/kstrtox.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/spi/spi.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/units.h>
29
30 #define AD3530R_INTERFACE_CONFIG_A 0x00
31 #define AD3530R_OUTPUT_OPERATING_MODE_0 0x20
32 #define AD3530R_OUTPUT_OPERATING_MODE_1 0x21
33 #define AD3530R_OUTPUT_CONTROL_0 0x2A
34 #define AD3530R_REFERENCE_CONTROL_0 0x3C
35 #define AD3530R_SW_LDAC_TRIG_A 0xE5
36 #define AD3530R_INPUT_CH 0xEB
37 #define AD3530R_MAX_REG_ADDR 0xF9
38
39 #define AD3531R_SW_LDAC_TRIG_A 0xDD
40 #define AD3531R_INPUT_CH 0xE3
41
42 /* AD3532R/AD3532 bank 0 registers (channels 0-7) */
43 #define AD3532R_INTERFACE_CONFIG_A_0 0x1000
44 #define AD3532R_OUTPUT_OPERATING_MODE_0 0x1020
45 #define AD3532R_OUTPUT_OPERATING_MODE_1 0x1021
46 #define AD3532R_OUTPUT_CONTROL_0 0x102A
47 #define AD3532R_REFERENCE_CONTROL_0 0x103C
48 #define AD3532R_SW_LDAC_TRIG_0 0x10E5
49 #define AD3532R_INPUT_CH_0 0x10EB
50
51 /* AD3532R/AD3532 bank 1 registers (channels 8-15) */
52 #define AD3532R_INTERFACE_CONFIG_A_1 0x3000
53 #define AD3532R_OUTPUT_OPERATING_MODE_2 0x3020
54 #define AD3532R_OUTPUT_OPERATING_MODE_3 0x3021
55 #define AD3532R_OUTPUT_CONTROL_1 0x302A
56 #define AD3532R_REFERENCE_CONTROL_1 0x303C
57 #define AD3532R_SW_LDAC_TRIG_1 0x30E5
58 #define AD3532R_INPUT_CH_1 0x30EB
59 #define AD3532R_MAX_REG_ADDR 0x30F9
60
61 #define AD3530R_SLD_TRIG_A BIT(7)
62 #define AD3530R_OUTPUT_CONTROL_RANGE BIT(2)
63 #define AD3530R_REFERENCE_CONTROL_SEL BIT(0)
64 #define AD3530R_REG_VAL_MASK GENMASK(15, 0)
65 #define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan))
66
67 #define AD3530R_SW_RESET (BIT(7) | BIT(0))
68 #define AD3530R_INTERNAL_VREF_mV 2500
69 #define AD3530R_LDAC_PULSE_US 100
70
71 #define AD3530R_DAC_MAX_VAL GENMASK(15, 0)
72 #define AD3530R_CH_PER_REG 4
73 #define AD3530R_CH_PER_BANK 8
74 #define AD3531R_MAX_CHANNELS 4
75 #define AD3532R_MAX_CHANNELS 16
76
77 enum ad3530r_mode {
78 AD3530R_NORMAL_OP,
79 AD3530R_POWERDOWN_1K,
80 AD3530R_POWERDOWN_7K7,
81 AD3530R_POWERDOWN_32K,
82 };
83
84 struct ad3530r_chan {
85 enum ad3530r_mode powerdown_mode;
86 bool powerdown;
87 };
88
89 struct ad3530r_chip_info {
90 const char *name;
91 const struct iio_chan_spec *channels;
92 const struct regmap_config *regmap_config;
93 int (*input_ch_reg)(unsigned int channel);
94 int (*sw_ldac_trig_reg)(unsigned int channel);
95 const unsigned int *interface_config_a;
96 const unsigned int *output_control;
97 const unsigned int *reference_control;
98 const unsigned int *op_mode;
99 unsigned int num_channels;
100 unsigned int num_banks;
101 unsigned int num_op_mode_regs;
102 bool internal_ref_support;
103 };
104
105 struct ad3530r_state {
106 struct regmap *regmap;
107 /* lock to protect against multiple access to the device and shared data */
108 struct mutex lock;
109 struct ad3530r_chan chan[AD3532R_MAX_CHANNELS];
110 const struct ad3530r_chip_info *chip_info;
111 struct gpio_desc *ldac_gpio;
112 int vref_mV;
113 /*
114 * DMA (thus cache coherency maintenance) may require the transfer
115 * buffers to live in their own cache lines.
116 */
117 __be16 buf __aligned(IIO_DMA_MINALIGN);
118 };
119
ad3530r_input_ch_reg(unsigned int channel)120 static int ad3530r_input_ch_reg(unsigned int channel)
121 {
122 return 2 * channel + AD3530R_INPUT_CH;
123 }
124
ad3531r_input_ch_reg(unsigned int channel)125 static int ad3531r_input_ch_reg(unsigned int channel)
126 {
127 return 2 * channel + AD3531R_INPUT_CH;
128 }
129
ad3532r_input_ch_reg(unsigned int channel)130 static int ad3532r_input_ch_reg(unsigned int channel)
131 {
132 unsigned int bank = channel / AD3530R_CH_PER_BANK;
133 unsigned int local_ch = channel % AD3530R_CH_PER_BANK;
134
135 return 2 * local_ch + (bank ? AD3532R_INPUT_CH_1 : AD3532R_INPUT_CH_0);
136 }
137
138 static const char * const ad3530r_powerdown_modes[] = {
139 "1kohm_to_gnd",
140 "7.7kohm_to_gnd",
141 "32kohm_to_gnd",
142 };
143
144 static const char * const ad3531r_powerdown_modes[] = {
145 "500ohm_to_gnd",
146 "3.85kohm_to_gnd",
147 "16kohm_to_gnd",
148 };
149
150 static const char * const ad3532r_powerdown_modes[] = {
151 "1kohm_to_gnd",
152 "10kohm_to_gnd",
153 "three_state",
154 };
155
ad3530r_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)156 static int ad3530r_get_powerdown_mode(struct iio_dev *indio_dev,
157 const struct iio_chan_spec *chan)
158 {
159 struct ad3530r_state *st = iio_priv(indio_dev);
160
161 guard(mutex)(&st->lock);
162 return st->chan[chan->channel].powerdown_mode - 1;
163 }
164
ad3530r_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)165 static int ad3530r_set_powerdown_mode(struct iio_dev *indio_dev,
166 const struct iio_chan_spec *chan,
167 unsigned int mode)
168 {
169 struct ad3530r_state *st = iio_priv(indio_dev);
170
171 guard(mutex)(&st->lock);
172 st->chan[chan->channel].powerdown_mode = mode + 1;
173
174 return 0;
175 }
176
177 static const struct iio_enum ad3530r_powerdown_mode_enum = {
178 .items = ad3530r_powerdown_modes,
179 .num_items = ARRAY_SIZE(ad3530r_powerdown_modes),
180 .get = ad3530r_get_powerdown_mode,
181 .set = ad3530r_set_powerdown_mode,
182 };
183
184 static const struct iio_enum ad3531r_powerdown_mode_enum = {
185 .items = ad3531r_powerdown_modes,
186 .num_items = ARRAY_SIZE(ad3531r_powerdown_modes),
187 .get = ad3530r_get_powerdown_mode,
188 .set = ad3530r_set_powerdown_mode,
189 };
190
191 static const struct iio_enum ad3532r_powerdown_mode_enum = {
192 .items = ad3532r_powerdown_modes,
193 .num_items = ARRAY_SIZE(ad3532r_powerdown_modes),
194 .get = ad3530r_get_powerdown_mode,
195 .set = ad3530r_set_powerdown_mode,
196 };
197
ad3530r_get_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)198 static ssize_t ad3530r_get_dac_powerdown(struct iio_dev *indio_dev,
199 uintptr_t private,
200 const struct iio_chan_spec *chan,
201 char *buf)
202 {
203 struct ad3530r_state *st = iio_priv(indio_dev);
204
205 guard(mutex)(&st->lock);
206 return sysfs_emit(buf, "%d\n", st->chan[chan->channel].powerdown);
207 }
208
ad3530r_set_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)209 static ssize_t ad3530r_set_dac_powerdown(struct iio_dev *indio_dev,
210 uintptr_t private,
211 const struct iio_chan_spec *chan,
212 const char *buf, size_t len)
213 {
214 struct ad3530r_state *st = iio_priv(indio_dev);
215 int ret;
216 unsigned int reg, pdmode, mask, val;
217 bool powerdown;
218
219 ret = kstrtobool(buf, &powerdown);
220 if (ret)
221 return ret;
222
223 guard(mutex)(&st->lock);
224 reg = chan->channel < AD3531R_MAX_CHANNELS ?
225 AD3530R_OUTPUT_OPERATING_MODE_0 :
226 AD3530R_OUTPUT_OPERATING_MODE_1;
227 pdmode = powerdown ? st->chan[chan->channel].powerdown_mode : 0;
228 mask = chan->channel < AD3531R_MAX_CHANNELS ?
229 AD3530R_OP_MODE_CHAN_MSK(chan->channel) :
230 AD3530R_OP_MODE_CHAN_MSK(chan->channel - 4);
231 val = field_prep(mask, pdmode);
232
233 ret = regmap_update_bits(st->regmap, reg, mask, val);
234 if (ret)
235 return ret;
236
237 st->chan[chan->channel].powerdown = powerdown;
238
239 return len;
240 }
241
ad3532r_set_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)242 static ssize_t ad3532r_set_dac_powerdown(struct iio_dev *indio_dev,
243 uintptr_t private,
244 const struct iio_chan_spec *chan,
245 const char *buf, size_t len)
246 {
247 struct ad3530r_state *st = iio_priv(indio_dev);
248 unsigned int bank, local_ch, reg_in_bank, ch_in_reg;
249 unsigned int reg, mask, val;
250 bool powerdown;
251 int ret;
252
253 ret = kstrtobool(buf, &powerdown);
254 if (ret)
255 return ret;
256
257 bank = chan->channel / AD3530R_CH_PER_BANK;
258 local_ch = chan->channel % AD3530R_CH_PER_BANK;
259 reg_in_bank = local_ch / AD3530R_CH_PER_REG;
260 ch_in_reg = local_ch % AD3530R_CH_PER_REG;
261
262 reg = reg_in_bank + (bank ? AD3532R_OUTPUT_OPERATING_MODE_2 :
263 AD3532R_OUTPUT_OPERATING_MODE_0);
264 mask = AD3530R_OP_MODE_CHAN_MSK(ch_in_reg);
265
266 guard(mutex)(&st->lock);
267 if (powerdown) {
268 val = field_prep(mask, st->chan[chan->channel].powerdown_mode);
269 ret = regmap_update_bits(st->regmap, reg, mask, val);
270 } else {
271 ret = regmap_clear_bits(st->regmap, reg, mask);
272 }
273 if (ret)
274 return ret;
275
276 st->chan[chan->channel].powerdown = powerdown;
277
278 return len;
279 }
280
ad3530r_trigger_sw_ldac_reg(unsigned int channel)281 static int ad3530r_trigger_sw_ldac_reg(unsigned int channel)
282 {
283 return AD3530R_SW_LDAC_TRIG_A;
284 }
285
ad3531r_trigger_sw_ldac_reg(unsigned int channel)286 static int ad3531r_trigger_sw_ldac_reg(unsigned int channel)
287 {
288 return AD3531R_SW_LDAC_TRIG_A;
289 }
290
ad3532r_trigger_sw_ldac_reg(unsigned int channel)291 static int ad3532r_trigger_sw_ldac_reg(unsigned int channel)
292 {
293 unsigned int bank = channel / AD3530R_CH_PER_BANK;
294
295 return bank ? AD3532R_SW_LDAC_TRIG_1 : AD3532R_SW_LDAC_TRIG_0;
296 }
297
ad3530r_trigger_hw_ldac(struct gpio_desc * ldac_gpio)298 static int ad3530r_trigger_hw_ldac(struct gpio_desc *ldac_gpio)
299 {
300 gpiod_set_value_cansleep(ldac_gpio, 1);
301 fsleep(AD3530R_LDAC_PULSE_US);
302 gpiod_set_value_cansleep(ldac_gpio, 0);
303
304 return 0;
305 }
306
ad3530r_dac_write(struct ad3530r_state * st,unsigned int chan,unsigned int val)307 static int ad3530r_dac_write(struct ad3530r_state *st, unsigned int chan,
308 unsigned int val)
309 {
310 int ret;
311
312 guard(mutex)(&st->lock);
313 st->buf = cpu_to_be16(val);
314
315 ret = regmap_bulk_write(st->regmap, st->chip_info->input_ch_reg(chan),
316 &st->buf, sizeof(st->buf));
317 if (ret)
318 return ret;
319
320 if (st->ldac_gpio)
321 return ad3530r_trigger_hw_ldac(st->ldac_gpio);
322
323 return regmap_set_bits(st->regmap, st->chip_info->sw_ldac_trig_reg(chan),
324 AD3530R_SLD_TRIG_A);
325 }
326
ad3530r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)327 static int ad3530r_read_raw(struct iio_dev *indio_dev,
328 struct iio_chan_spec const *chan,
329 int *val, int *val2, long info)
330 {
331 struct ad3530r_state *st = iio_priv(indio_dev);
332 int ret;
333
334 guard(mutex)(&st->lock);
335 switch (info) {
336 case IIO_CHAN_INFO_RAW:
337 ret = regmap_bulk_read(st->regmap,
338 st->chip_info->input_ch_reg(chan->channel),
339 &st->buf, sizeof(st->buf));
340 if (ret)
341 return ret;
342
343 *val = FIELD_GET(AD3530R_REG_VAL_MASK, be16_to_cpu(st->buf));
344
345 return IIO_VAL_INT;
346 case IIO_CHAN_INFO_SCALE:
347 *val = st->vref_mV;
348 *val2 = 16;
349
350 return IIO_VAL_FRACTIONAL_LOG2;
351 default:
352 return -EINVAL;
353 }
354 }
355
ad3530r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)356 static int ad3530r_write_raw(struct iio_dev *indio_dev,
357 struct iio_chan_spec const *chan,
358 int val, int val2, long info)
359 {
360 struct ad3530r_state *st = iio_priv(indio_dev);
361
362 switch (info) {
363 case IIO_CHAN_INFO_RAW:
364 if (val < 0 || val > AD3530R_DAC_MAX_VAL)
365 return -EINVAL;
366
367 return ad3530r_dac_write(st, chan->channel, val);
368 default:
369 return -EINVAL;
370 }
371 }
372
ad3530r_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)373 static int ad3530r_reg_access(struct iio_dev *indio_dev, unsigned int reg,
374 unsigned int writeval, unsigned int *readval)
375 {
376 struct ad3530r_state *st = iio_priv(indio_dev);
377
378 if (readval)
379 return regmap_read(st->regmap, reg, readval);
380
381 return regmap_write(st->regmap, reg, writeval);
382 }
383
384 static const struct iio_chan_spec_ext_info ad3530r_ext_info[] = {
385 {
386 .name = "powerdown",
387 .shared = IIO_SEPARATE,
388 .read = ad3530r_get_dac_powerdown,
389 .write = ad3530r_set_dac_powerdown,
390 },
391 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3530r_powerdown_mode_enum),
392 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
393 &ad3530r_powerdown_mode_enum),
394 { }
395 };
396
397 static const struct iio_chan_spec_ext_info ad3531r_ext_info[] = {
398 {
399 .name = "powerdown",
400 .shared = IIO_SEPARATE,
401 .read = ad3530r_get_dac_powerdown,
402 .write = ad3530r_set_dac_powerdown,
403 },
404 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3531r_powerdown_mode_enum),
405 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
406 &ad3531r_powerdown_mode_enum),
407 { }
408 };
409
410 static const struct iio_chan_spec_ext_info ad3532r_ext_info[] = {
411 {
412 .name = "powerdown",
413 .shared = IIO_SEPARATE,
414 .read = ad3530r_get_dac_powerdown,
415 .write = ad3532r_set_dac_powerdown,
416 },
417 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3532r_powerdown_mode_enum),
418 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
419 &ad3532r_powerdown_mode_enum),
420 { }
421 };
422
423 #define AD3530R_CHAN(_chan, _ext_info) \
424 { \
425 .type = IIO_VOLTAGE, \
426 .indexed = 1, \
427 .channel = _chan, \
428 .output = 1, \
429 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
430 BIT(IIO_CHAN_INFO_SCALE), \
431 .ext_info = _ext_info, \
432 }
433
434 static const struct iio_chan_spec ad3530r_channels[] = {
435 AD3530R_CHAN(0, ad3530r_ext_info),
436 AD3530R_CHAN(1, ad3530r_ext_info),
437 AD3530R_CHAN(2, ad3530r_ext_info),
438 AD3530R_CHAN(3, ad3530r_ext_info),
439 AD3530R_CHAN(4, ad3530r_ext_info),
440 AD3530R_CHAN(5, ad3530r_ext_info),
441 AD3530R_CHAN(6, ad3530r_ext_info),
442 AD3530R_CHAN(7, ad3530r_ext_info),
443 };
444
445 static const struct iio_chan_spec ad3531r_channels[] = {
446 AD3530R_CHAN(0, ad3531r_ext_info),
447 AD3530R_CHAN(1, ad3531r_ext_info),
448 AD3530R_CHAN(2, ad3531r_ext_info),
449 AD3530R_CHAN(3, ad3531r_ext_info),
450 };
451
452 static const struct iio_chan_spec ad3532r_channels[] = {
453 AD3530R_CHAN(0, ad3532r_ext_info),
454 AD3530R_CHAN(1, ad3532r_ext_info),
455 AD3530R_CHAN(2, ad3532r_ext_info),
456 AD3530R_CHAN(3, ad3532r_ext_info),
457 AD3530R_CHAN(4, ad3532r_ext_info),
458 AD3530R_CHAN(5, ad3532r_ext_info),
459 AD3530R_CHAN(6, ad3532r_ext_info),
460 AD3530R_CHAN(7, ad3532r_ext_info),
461 AD3530R_CHAN(8, ad3532r_ext_info),
462 AD3530R_CHAN(9, ad3532r_ext_info),
463 AD3530R_CHAN(10, ad3532r_ext_info),
464 AD3530R_CHAN(11, ad3532r_ext_info),
465 AD3530R_CHAN(12, ad3532r_ext_info),
466 AD3530R_CHAN(13, ad3532r_ext_info),
467 AD3530R_CHAN(14, ad3532r_ext_info),
468 AD3530R_CHAN(15, ad3532r_ext_info),
469 };
470
471 static const unsigned int ad3530r_if_config[] = {
472 AD3530R_INTERFACE_CONFIG_A,
473 };
474
475 static const unsigned int ad3530r_out_ctrl[] = {
476 AD3530R_OUTPUT_CONTROL_0,
477 };
478
479 static const unsigned int ad3530r_ref_ctrl[] = {
480 AD3530R_REFERENCE_CONTROL_0,
481 };
482
483 static const unsigned int ad3530r_op_mode[] = {
484 AD3530R_OUTPUT_OPERATING_MODE_0,
485 AD3530R_OUTPUT_OPERATING_MODE_1,
486 };
487
488 static const unsigned int ad3531r_op_mode[] = {
489 AD3530R_OUTPUT_OPERATING_MODE_0,
490 };
491
492 static const unsigned int ad3532r_if_config[] = {
493 AD3532R_INTERFACE_CONFIG_A_0,
494 AD3532R_INTERFACE_CONFIG_A_1,
495 };
496
497 static const unsigned int ad3532r_out_ctrl[] = {
498 AD3532R_OUTPUT_CONTROL_0,
499 AD3532R_OUTPUT_CONTROL_1,
500 };
501
502 static const unsigned int ad3532r_ref_ctrl[] = {
503 AD3532R_REFERENCE_CONTROL_0,
504 AD3532R_REFERENCE_CONTROL_1,
505 };
506
507 static const unsigned int ad3532r_op_mode[] = {
508 AD3532R_OUTPUT_OPERATING_MODE_0,
509 AD3532R_OUTPUT_OPERATING_MODE_1,
510 AD3532R_OUTPUT_OPERATING_MODE_2,
511 AD3532R_OUTPUT_OPERATING_MODE_3,
512 };
513
514 static const struct regmap_config ad3530r_regmap_config = {
515 .reg_bits = 16,
516 .val_bits = 8,
517 .max_register = AD3530R_MAX_REG_ADDR,
518 };
519
520 static const struct regmap_config ad3532r_regmap_config = {
521 .reg_bits = 16,
522 .val_bits = 8,
523 .max_register = AD3532R_MAX_REG_ADDR,
524 };
525
526 static const struct ad3530r_chip_info ad3530_chip = {
527 .name = "ad3530",
528 .channels = ad3530r_channels,
529 .regmap_config = &ad3530r_regmap_config,
530 .num_channels = ARRAY_SIZE(ad3530r_channels),
531 .sw_ldac_trig_reg = ad3530r_trigger_sw_ldac_reg,
532 .input_ch_reg = ad3530r_input_ch_reg,
533 .interface_config_a = ad3530r_if_config,
534 .output_control = ad3530r_out_ctrl,
535 .reference_control = ad3530r_ref_ctrl,
536 .op_mode = ad3530r_op_mode,
537 .num_banks = ARRAY_SIZE(ad3530r_if_config),
538 .num_op_mode_regs = ARRAY_SIZE(ad3530r_op_mode),
539 .internal_ref_support = false,
540 };
541
542 static const struct ad3530r_chip_info ad3530r_chip = {
543 .name = "ad3530r",
544 .channels = ad3530r_channels,
545 .regmap_config = &ad3530r_regmap_config,
546 .num_channels = ARRAY_SIZE(ad3530r_channels),
547 .sw_ldac_trig_reg = ad3530r_trigger_sw_ldac_reg,
548 .input_ch_reg = ad3530r_input_ch_reg,
549 .interface_config_a = ad3530r_if_config,
550 .output_control = ad3530r_out_ctrl,
551 .reference_control = ad3530r_ref_ctrl,
552 .op_mode = ad3530r_op_mode,
553 .num_banks = ARRAY_SIZE(ad3530r_if_config),
554 .num_op_mode_regs = ARRAY_SIZE(ad3530r_op_mode),
555 .internal_ref_support = true,
556 };
557
558 static const struct ad3530r_chip_info ad3531_chip = {
559 .name = "ad3531",
560 .channels = ad3531r_channels,
561 .regmap_config = &ad3530r_regmap_config,
562 .num_channels = ARRAY_SIZE(ad3531r_channels),
563 .sw_ldac_trig_reg = ad3531r_trigger_sw_ldac_reg,
564 .input_ch_reg = ad3531r_input_ch_reg,
565 .interface_config_a = ad3530r_if_config,
566 .output_control = ad3530r_out_ctrl,
567 .reference_control = ad3530r_ref_ctrl,
568 .op_mode = ad3531r_op_mode,
569 .num_banks = ARRAY_SIZE(ad3530r_if_config),
570 .num_op_mode_regs = ARRAY_SIZE(ad3531r_op_mode),
571 .internal_ref_support = false,
572 };
573
574 static const struct ad3530r_chip_info ad3531r_chip = {
575 .name = "ad3531r",
576 .channels = ad3531r_channels,
577 .regmap_config = &ad3530r_regmap_config,
578 .num_channels = ARRAY_SIZE(ad3531r_channels),
579 .sw_ldac_trig_reg = ad3531r_trigger_sw_ldac_reg,
580 .input_ch_reg = ad3531r_input_ch_reg,
581 .interface_config_a = ad3530r_if_config,
582 .output_control = ad3530r_out_ctrl,
583 .reference_control = ad3530r_ref_ctrl,
584 .op_mode = ad3531r_op_mode,
585 .num_banks = ARRAY_SIZE(ad3530r_if_config),
586 .num_op_mode_regs = ARRAY_SIZE(ad3531r_op_mode),
587 .internal_ref_support = true,
588 };
589
590 static const struct ad3530r_chip_info ad3532_chip = {
591 .name = "ad3532",
592 .channels = ad3532r_channels,
593 .regmap_config = &ad3532r_regmap_config,
594 .num_channels = ARRAY_SIZE(ad3532r_channels),
595 .sw_ldac_trig_reg = ad3532r_trigger_sw_ldac_reg,
596 .input_ch_reg = ad3532r_input_ch_reg,
597 .interface_config_a = ad3532r_if_config,
598 .output_control = ad3532r_out_ctrl,
599 .reference_control = ad3532r_ref_ctrl,
600 .op_mode = ad3532r_op_mode,
601 .num_banks = ARRAY_SIZE(ad3532r_if_config),
602 .num_op_mode_regs = ARRAY_SIZE(ad3532r_op_mode),
603 .internal_ref_support = false,
604 };
605
606 static const struct ad3530r_chip_info ad3532r_chip = {
607 .name = "ad3532r",
608 .channels = ad3532r_channels,
609 .regmap_config = &ad3532r_regmap_config,
610 .num_channels = ARRAY_SIZE(ad3532r_channels),
611 .sw_ldac_trig_reg = ad3532r_trigger_sw_ldac_reg,
612 .input_ch_reg = ad3532r_input_ch_reg,
613 .interface_config_a = ad3532r_if_config,
614 .output_control = ad3532r_out_ctrl,
615 .reference_control = ad3532r_ref_ctrl,
616 .op_mode = ad3532r_op_mode,
617 .num_banks = ARRAY_SIZE(ad3532r_if_config),
618 .num_op_mode_regs = ARRAY_SIZE(ad3532r_op_mode),
619 .internal_ref_support = true,
620 };
621
ad3530r_set_reg_bank_bits(const struct ad3530r_state * st,const unsigned int * regs,unsigned int num_regs,unsigned int mask)622 static int ad3530r_set_reg_bank_bits(const struct ad3530r_state *st,
623 const unsigned int *regs,
624 unsigned int num_regs,
625 unsigned int mask)
626 {
627 int ret;
628
629 for (unsigned int i = 0; i < num_regs; i++) {
630 ret = regmap_set_bits(st->regmap, regs[i], mask);
631 if (ret)
632 return ret;
633 }
634
635 return 0;
636 }
637
ad3530r_write_reg_banks(const struct ad3530r_state * st,const unsigned int * regs,unsigned int num_regs,unsigned int val)638 static int ad3530r_write_reg_banks(const struct ad3530r_state *st,
639 const unsigned int *regs,
640 unsigned int num_regs,
641 unsigned int val)
642 {
643 int ret;
644
645 for (unsigned int i = 0; i < num_regs; i++) {
646 ret = regmap_write(st->regmap, regs[i], val);
647 if (ret)
648 return ret;
649 }
650
651 return 0;
652 }
653
ad3530r_setup(struct ad3530r_state * st,int external_vref_uV)654 static int ad3530r_setup(struct ad3530r_state *st, int external_vref_uV)
655 {
656 const struct ad3530r_chip_info *chip_info = st->chip_info;
657 struct device *dev = regmap_get_device(st->regmap);
658 struct gpio_desc *reset_gpio;
659 u8 range_multiplier, val;
660 int ret;
661
662 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
663 if (IS_ERR(reset_gpio))
664 return dev_err_probe(dev, PTR_ERR(reset_gpio),
665 "Failed to get reset GPIO\n");
666
667 if (reset_gpio) {
668 /* Perform hardware reset */
669 fsleep(1 * USEC_PER_MSEC);
670 gpiod_set_value_cansleep(reset_gpio, 0);
671 } else {
672 /* Perform software reset */
673 ret = ad3530r_set_reg_bank_bits(st, chip_info->interface_config_a,
674 chip_info->num_banks,
675 AD3530R_SW_RESET);
676 if (ret)
677 return ret;
678 }
679
680 fsleep(10 * USEC_PER_MSEC);
681
682 range_multiplier = 1;
683 if (device_property_read_bool(dev, "adi,range-double")) {
684 ret = ad3530r_set_reg_bank_bits(st, chip_info->output_control,
685 chip_info->num_banks,
686 AD3530R_OUTPUT_CONTROL_RANGE);
687 if (ret)
688 return ret;
689
690 range_multiplier = 2;
691 }
692
693 if (external_vref_uV) {
694 st->vref_mV = range_multiplier * external_vref_uV / MILLI;
695 } else {
696 ret = ad3530r_set_reg_bank_bits(st, chip_info->reference_control,
697 chip_info->num_banks,
698 AD3530R_REFERENCE_CONTROL_SEL);
699 if (ret)
700 return ret;
701
702 st->vref_mV = range_multiplier * AD3530R_INTERNAL_VREF_mV;
703 }
704
705 /* Set normal operating mode for all channels */
706 val = FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) |
707 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) |
708 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) |
709 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP);
710
711 ret = ad3530r_write_reg_banks(st, st->chip_info->op_mode,
712 st->chip_info->num_op_mode_regs, val);
713 if (ret)
714 return ret;
715
716 for (unsigned int i = 0; i < st->chip_info->num_channels; i++)
717 st->chan[i].powerdown_mode = AD3530R_POWERDOWN_32K;
718
719 st->ldac_gpio = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_LOW);
720 if (IS_ERR(st->ldac_gpio))
721 return dev_err_probe(dev, PTR_ERR(st->ldac_gpio),
722 "Failed to get ldac GPIO\n");
723
724 return 0;
725 }
726
727 static const struct iio_info ad3530r_info = {
728 .read_raw = ad3530r_read_raw,
729 .write_raw = ad3530r_write_raw,
730 .debugfs_reg_access = ad3530r_reg_access,
731 };
732
ad3530r_probe(struct spi_device * spi)733 static int ad3530r_probe(struct spi_device *spi)
734 {
735 static const char * const regulators[] = { "vdd", "iovdd" };
736 struct device *dev = &spi->dev;
737 struct iio_dev *indio_dev;
738 struct ad3530r_state *st;
739 int ret, external_vref_uV;
740
741 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
742 if (!indio_dev)
743 return -ENOMEM;
744
745 st = iio_priv(indio_dev);
746
747 st->chip_info = spi_get_device_match_data(spi);
748 if (!st->chip_info)
749 return -ENODEV;
750
751 st->regmap = devm_regmap_init_spi(spi, st->chip_info->regmap_config);
752 if (IS_ERR(st->regmap))
753 return dev_err_probe(dev, PTR_ERR(st->regmap),
754 "Failed to init regmap");
755
756 ret = devm_mutex_init(dev, &st->lock);
757 if (ret)
758 return ret;
759
760 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
761 regulators);
762 if (ret)
763 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
764
765 external_vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref");
766 if (external_vref_uV < 0 && external_vref_uV != -ENODEV)
767 return external_vref_uV;
768
769 if (external_vref_uV == -ENODEV)
770 external_vref_uV = 0;
771
772 if (!st->chip_info->internal_ref_support && external_vref_uV == 0)
773 return -ENODEV;
774
775 ret = ad3530r_setup(st, external_vref_uV);
776 if (ret)
777 return ret;
778
779 indio_dev->name = st->chip_info->name;
780 indio_dev->info = &ad3530r_info;
781 indio_dev->modes = INDIO_DIRECT_MODE;
782 indio_dev->channels = st->chip_info->channels;
783 indio_dev->num_channels = st->chip_info->num_channels;
784
785 return devm_iio_device_register(&spi->dev, indio_dev);
786 }
787
788 static const struct spi_device_id ad3530r_id[] = {
789 { .name = "ad3530", .driver_data = (kernel_ulong_t)&ad3530_chip },
790 { .name = "ad3530r", .driver_data = (kernel_ulong_t)&ad3530r_chip },
791 { .name = "ad3531", .driver_data = (kernel_ulong_t)&ad3531_chip },
792 { .name = "ad3531r", .driver_data = (kernel_ulong_t)&ad3531r_chip },
793 { .name = "ad3532", .driver_data = (kernel_ulong_t)&ad3532_chip },
794 { .name = "ad3532r", .driver_data = (kernel_ulong_t)&ad3532r_chip },
795 { }
796 };
797 MODULE_DEVICE_TABLE(spi, ad3530r_id);
798
799 static const struct of_device_id ad3530r_of_match[] = {
800 { .compatible = "adi,ad3530", .data = &ad3530_chip },
801 { .compatible = "adi,ad3530r", .data = &ad3530r_chip },
802 { .compatible = "adi,ad3531", .data = &ad3531_chip },
803 { .compatible = "adi,ad3531r", .data = &ad3531r_chip },
804 { .compatible = "adi,ad3532", .data = &ad3532_chip },
805 { .compatible = "adi,ad3532r", .data = &ad3532r_chip },
806 { }
807 };
808 MODULE_DEVICE_TABLE(of, ad3530r_of_match);
809
810 static struct spi_driver ad3530r_driver = {
811 .driver = {
812 .name = "ad3530r",
813 .of_match_table = ad3530r_of_match,
814 },
815 .probe = ad3530r_probe,
816 .id_table = ad3530r_id,
817 };
818 module_spi_driver(ad3530r_driver);
819
820 MODULE_AUTHOR("Kim Seer Paller <kimseer.paller@analog.com>");
821 MODULE_DESCRIPTION("Analog Devices AD3530R and Similar DACs Driver");
822 MODULE_LICENSE("GPL");
823