1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * IIO driver for MCP47FEB02 Multi-Channel DAC with I2C interface
4 *
5 * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Ariana Lazar <ariana.lazar@microchip.com>
8 *
9 * Datasheet links:
10 * [MCP47FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005375A.pdf
11 * [MCP47FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005405A.pdf
12 * [MCP47FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf
13 */
14 #include <linux/array_size.h>
15 #include <linux/bits.h>
16 #include <linux/bitfield.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/i2c.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/kstrtox.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/time64.h>
29 #include <linux/types.h>
30 #include <linux/units.h>
31
32 /* Register addresses must be left shifted with 3 positions in order to append command mask */
33 #define MCP47FEB02_DAC0_REG_ADDR 0x00
34 #define MCP47FEB02_VREF_REG_ADDR 0x40
35 #define MCP47FEB02_POWER_DOWN_REG_ADDR 0x48
36 #define MCP47FEB02_DAC_CTRL_MASK GENMASK(1, 0)
37
38 #define MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR 0x50
39 #define MCP47FEB02_GAIN_BIT_MASK BIT(0)
40 #define MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK BIT(6)
41 #define MCP47FEB02_GAIN_BITS_MASK GENMASK(15, 8)
42
43 #define MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR 0x58
44
45 #define MCP47FEB02_NV_DAC0_REG_ADDR 0x80
46 #define MCP47FEB02_NV_VREF_REG_ADDR 0xC0
47 #define MCP47FEB02_NV_POWER_DOWN_REG_ADDR 0xC8
48 #define MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR 0xD0
49 #define MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK GENMASK(7, 0)
50
51 /* Voltage reference, Power-Down control register and DAC Wiperlock status register fields */
52 #define DAC_CTRL_MASK(ch) (GENMASK(1, 0) << (2 * (ch)))
53 #define DAC_CTRL_VAL(ch, val) ((val) << (2 * (ch)))
54
55 /* Gain Control and I2C Slave Address Reguster fields */
56 #define DAC_GAIN_MASK(ch) (BIT(0) << (8 + (ch)))
57 #define DAC_GAIN_VAL(ch, val) ((val) << (8 + (ch)))
58
59 #define REG_ADDR(reg) ((reg) << 3)
60 #define NV_REG_ADDR(reg) ((NV_DAC_ADDR_OFFSET + (reg)) << 3)
61 #define READFLAG_MASK GENMASK(2, 1)
62
63 #define MCP47FEB02_MAX_CH 8
64 #define MCP47FEB02_MAX_SCALES_CH 3
65 #define MCP47FEB02_DAC_WIPER_UNLOCKED 0
66 #define MCP47FEB02_NORMAL_OPERATION 0
67 #define MCP47FEB02_INTERNAL_BAND_GAP_uV 2440000
68 #define NV_DAC_ADDR_OFFSET 0x10
69
70 enum mcp47feb02_vref_mode {
71 MCP47FEB02_VREF_VDD = 0,
72 MCP47FEB02_INTERNAL_BAND_GAP = 1,
73 MCP47FEB02_EXTERNAL_VREF_UNBUFFERED = 2,
74 MCP47FEB02_EXTERNAL_VREF_BUFFERED = 3,
75 };
76
77 enum mcp47feb02_scale {
78 MCP47FEB02_SCALE_VDD = 0,
79 MCP47FEB02_SCALE_GAIN_X1 = 1,
80 MCP47FEB02_SCALE_GAIN_X2 = 2,
81 };
82
83 enum mcp47feb02_gain_bit_mode {
84 MCP47FEB02_GAIN_BIT_X1 = 0,
85 MCP47FEB02_GAIN_BIT_X2 = 1,
86 };
87
88 static const char * const mcp47feb02_powerdown_modes[] = {
89 "1kohm_to_gnd",
90 "100kohm_to_gnd",
91 "open_circuit",
92 };
93
94 /**
95 * struct mcp47feb02_features - chip specific data
96 * @name: device name
97 * @phys_channels: number of hardware channels
98 * @resolution: DAC resolution
99 * @have_ext_vref1: does the hardware have an the second external voltage reference?
100 * @have_eeprom: does the hardware have an internal eeprom?
101 */
102 struct mcp47feb02_features {
103 const char *name;
104 unsigned int phys_channels;
105 unsigned int resolution;
106 bool have_ext_vref1;
107 bool have_eeprom;
108 };
109
110 static const struct mcp47feb02_features mcp47feb01_chip_features = {
111 .name = "mcp47feb01",
112 .phys_channels = 1,
113 .resolution = 8,
114 .have_ext_vref1 = false,
115 .have_eeprom = true,
116 };
117
118 static const struct mcp47feb02_features mcp47feb02_chip_features = {
119 .name = "mcp47feb02",
120 .phys_channels = 2,
121 .resolution = 8,
122 .have_ext_vref1 = false,
123 .have_eeprom = true,
124 };
125
126 static const struct mcp47feb02_features mcp47feb04_chip_features = {
127 .name = "mcp47feb04",
128 .phys_channels = 4,
129 .resolution = 8,
130 .have_ext_vref1 = true,
131 .have_eeprom = true,
132 };
133
134 static const struct mcp47feb02_features mcp47feb08_chip_features = {
135 .name = "mcp47feb08",
136 .phys_channels = 8,
137 .resolution = 8,
138 .have_ext_vref1 = true,
139 .have_eeprom = true,
140 };
141
142 static const struct mcp47feb02_features mcp47feb11_chip_features = {
143 .name = "mcp47feb11",
144 .phys_channels = 1,
145 .resolution = 10,
146 .have_ext_vref1 = false,
147 .have_eeprom = true,
148 };
149
150 static const struct mcp47feb02_features mcp47feb12_chip_features = {
151 .name = "mcp47feb12",
152 .phys_channels = 2,
153 .resolution = 10,
154 .have_ext_vref1 = false,
155 .have_eeprom = true,
156 };
157
158 static const struct mcp47feb02_features mcp47feb14_chip_features = {
159 .name = "mcp47feb14",
160 .phys_channels = 4,
161 .resolution = 10,
162 .have_ext_vref1 = true,
163 .have_eeprom = true,
164 };
165
166 static const struct mcp47feb02_features mcp47feb18_chip_features = {
167 .name = "mcp47feb18",
168 .phys_channels = 8,
169 .resolution = 10,
170 .have_ext_vref1 = true,
171 .have_eeprom = true,
172 };
173
174 static const struct mcp47feb02_features mcp47feb21_chip_features = {
175 .name = "mcp47feb21",
176 .phys_channels = 1,
177 .resolution = 12,
178 .have_ext_vref1 = false,
179 .have_eeprom = true,
180 };
181
182 static const struct mcp47feb02_features mcp47feb22_chip_features = {
183 .name = "mcp47feb22",
184 .phys_channels = 2,
185 .resolution = 12,
186 .have_ext_vref1 = false,
187 .have_eeprom = true,
188 };
189
190 static const struct mcp47feb02_features mcp47feb24_chip_features = {
191 .name = "mcp47feb24",
192 .phys_channels = 4,
193 .resolution = 12,
194 .have_ext_vref1 = true,
195 .have_eeprom = true,
196 };
197
198 static const struct mcp47feb02_features mcp47feb28_chip_features = {
199 .name = "mcp47feb28",
200 .phys_channels = 8,
201 .resolution = 12,
202 .have_ext_vref1 = true,
203 .have_eeprom = true,
204 };
205
206 static const struct mcp47feb02_features mcp47fvb01_chip_features = {
207 .name = "mcp47fvb01",
208 .phys_channels = 1,
209 .resolution = 8,
210 .have_ext_vref1 = false,
211 .have_eeprom = false,
212 };
213
214 static const struct mcp47feb02_features mcp47fvb02_chip_features = {
215 .name = "mcp47fvb02",
216 .phys_channels = 2,
217 .resolution = 8,
218 .have_ext_vref1 = false,
219 .have_eeprom = false,
220 };
221
222 static const struct mcp47feb02_features mcp47fvb04_chip_features = {
223 .name = "mcp47fvb04",
224 .phys_channels = 4,
225 .resolution = 8,
226 .have_ext_vref1 = true,
227 .have_eeprom = false,
228 };
229
230 static const struct mcp47feb02_features mcp47fvb08_chip_features = {
231 .name = "mcp47fvb08",
232 .phys_channels = 8,
233 .resolution = 8,
234 .have_ext_vref1 = true,
235 .have_eeprom = false,
236 };
237
238 static const struct mcp47feb02_features mcp47fvb11_chip_features = {
239 .name = "mcp47fvb11",
240 .phys_channels = 1,
241 .resolution = 10,
242 .have_ext_vref1 = false,
243 .have_eeprom = false,
244 };
245
246 static const struct mcp47feb02_features mcp47fvb12_chip_features = {
247 .name = "mcp47fvb12",
248 .phys_channels = 2,
249 .resolution = 10,
250 .have_ext_vref1 = false,
251 .have_eeprom = false,
252 };
253
254 static const struct mcp47feb02_features mcp47fvb14_chip_features = {
255 .name = "mcp47fvb14",
256 .phys_channels = 4,
257 .resolution = 10,
258 .have_ext_vref1 = true,
259 .have_eeprom = false,
260 };
261
262 static const struct mcp47feb02_features mcp47fvb18_chip_features = {
263 .name = "mcp47fvb18",
264 .phys_channels = 8,
265 .resolution = 10,
266 .have_ext_vref1 = true,
267 .have_eeprom = false,
268 };
269
270 static const struct mcp47feb02_features mcp47fvb21_chip_features = {
271 .name = "mcp47fvb21",
272 .phys_channels = 1,
273 .resolution = 12,
274 .have_ext_vref1 = false,
275 .have_eeprom = false,
276 };
277
278 static const struct mcp47feb02_features mcp47fvb22_chip_features = {
279 .name = "mcp47fvb22",
280 .phys_channels = 2,
281 .resolution = 12,
282 .have_ext_vref1 = false,
283 .have_eeprom = false,
284 };
285
286 static const struct mcp47feb02_features mcp47fvb24_chip_features = {
287 .name = "mcp47fvb24",
288 .phys_channels = 4,
289 .resolution = 12,
290 .have_ext_vref1 = true,
291 .have_eeprom = false,
292 };
293
294 static const struct mcp47feb02_features mcp47fvb28_chip_features = {
295 .name = "mcp47fvb28",
296 .phys_channels = 8,
297 .resolution = 12,
298 .have_ext_vref1 = true,
299 .have_eeprom = false,
300 };
301
302 /**
303 * struct mcp47feb02_channel_data - channel configuration
304 * @ref_mode: chosen voltage for reference
305 * @use_2x_gain: output driver gain control
306 * @powerdown: is false if the channel is in normal operation mode
307 * @powerdown_mode: selected power-down mode
308 * @dac_data: dac value
309 */
310 struct mcp47feb02_channel_data {
311 u8 ref_mode;
312 bool use_2x_gain;
313 bool powerdown;
314 u8 powerdown_mode;
315 u16 dac_data;
316 };
317
318 /**
319 * struct mcp47feb02_data - chip configuration
320 * @chdata: options configured for each channel on the device
321 * @lock: prevents concurrent reads/writes to driver's state members
322 * @chip_features: pointer to features struct
323 * @scale_1: scales set on channels that are based on Vref1
324 * @scale: scales set on channels that are based on Vref/Vref0
325 * @active_channels_mask: enabled channels
326 * @regmap: regmap for directly accessing device register
327 * @labels: table with channels labels
328 * @phys_channels: physical channels on the device
329 * @vref1_buffered: Vref1 buffer is enabled
330 * @vref_buffered: Vref/Vref0 buffer is enabled
331 * @use_vref1: vref1-supply is defined
332 * @use_vref: vref-supply is defined
333 */
334 struct mcp47feb02_data {
335 struct mcp47feb02_channel_data chdata[MCP47FEB02_MAX_CH];
336 struct mutex lock; /* prevents concurrent reads/writes to driver's state members */
337 const struct mcp47feb02_features *chip_features;
338 int scale_1[2 * MCP47FEB02_MAX_SCALES_CH];
339 int scale[2 * MCP47FEB02_MAX_SCALES_CH];
340 unsigned long active_channels_mask;
341 struct regmap *regmap;
342 const char *labels[MCP47FEB02_MAX_CH];
343 u16 phys_channels;
344 bool vref1_buffered;
345 bool vref_buffered;
346 bool use_vref1;
347 bool use_vref;
348 };
349
350 static const struct regmap_range mcp47feb02_readable_ranges[] = {
351 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
352 regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
353 };
354
355 static const struct regmap_range mcp47feb02_writable_ranges[] = {
356 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
357 regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
358 };
359
360 static const struct regmap_range mcp47feb02_volatile_ranges[] = {
361 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
362 regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
363 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
364 regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
365 };
366
367 static const struct regmap_access_table mcp47feb02_readable_table = {
368 .yes_ranges = mcp47feb02_readable_ranges,
369 .n_yes_ranges = ARRAY_SIZE(mcp47feb02_readable_ranges),
370 };
371
372 static const struct regmap_access_table mcp47feb02_writable_table = {
373 .yes_ranges = mcp47feb02_writable_ranges,
374 .n_yes_ranges = ARRAY_SIZE(mcp47feb02_writable_ranges),
375 };
376
377 static const struct regmap_access_table mcp47feb02_volatile_table = {
378 .yes_ranges = mcp47feb02_volatile_ranges,
379 .n_yes_ranges = ARRAY_SIZE(mcp47feb02_volatile_ranges),
380 };
381
382 static const struct regmap_config mcp47feb02_regmap_config = {
383 .name = "mcp47feb02_regmap",
384 .reg_bits = 8,
385 .val_bits = 16,
386 .rd_table = &mcp47feb02_readable_table,
387 .wr_table = &mcp47feb02_writable_table,
388 .volatile_table = &mcp47feb02_volatile_table,
389 .max_register = MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR,
390 .read_flag_mask = READFLAG_MASK,
391 .cache_type = REGCACHE_MAPLE,
392 .val_format_endian = REGMAP_ENDIAN_BIG,
393 };
394
395 /* For devices that doesn't have nonvolatile memory */
396 static const struct regmap_range mcp47fvb02_readable_ranges[] = {
397 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
398 };
399
400 static const struct regmap_range mcp47fvb02_writable_ranges[] = {
401 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
402 };
403
404 static const struct regmap_range mcp47fvb02_volatile_ranges[] = {
405 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
406 regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
407 };
408
409 static const struct regmap_access_table mcp47fvb02_readable_table = {
410 .yes_ranges = mcp47fvb02_readable_ranges,
411 .n_yes_ranges = ARRAY_SIZE(mcp47fvb02_readable_ranges),
412 };
413
414 static const struct regmap_access_table mcp47fvb02_writable_table = {
415 .yes_ranges = mcp47fvb02_writable_ranges,
416 .n_yes_ranges = ARRAY_SIZE(mcp47fvb02_writable_ranges),
417 };
418
419 static const struct regmap_access_table mcp47fvb02_volatile_table = {
420 .yes_ranges = mcp47fvb02_volatile_ranges,
421 .n_yes_ranges = ARRAY_SIZE(mcp47fvb02_volatile_ranges),
422 };
423
424 static const struct regmap_config mcp47fvb02_regmap_config = {
425 .name = "mcp47fvb02_regmap",
426 .reg_bits = 8,
427 .val_bits = 16,
428 .rd_table = &mcp47fvb02_readable_table,
429 .wr_table = &mcp47fvb02_writable_table,
430 .volatile_table = &mcp47fvb02_volatile_table,
431 .max_register = MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR,
432 .read_flag_mask = READFLAG_MASK,
433 .cache_type = REGCACHE_MAPLE,
434 .val_format_endian = REGMAP_ENDIAN_BIG,
435 };
436
mcp47feb02_write_to_eeprom(struct mcp47feb02_data * data,unsigned int reg,unsigned int val)437 static int mcp47feb02_write_to_eeprom(struct mcp47feb02_data *data, unsigned int reg,
438 unsigned int val)
439 {
440 int eewa_val, ret;
441
442 /*
443 * Wait until the currently occurring EEPROM Write Cycle is completed.
444 * Only serial commands to the volatile memory are allowed.
445 */
446 guard(mutex)(&data->lock);
447
448 ret = regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
449 eewa_val,
450 !(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK),
451 USEC_PER_MSEC, USEC_PER_MSEC * 5);
452 if (ret)
453 return ret;
454
455 return regmap_write(data->regmap, reg, val);
456 }
457
store_eeprom_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)458 static ssize_t store_eeprom_store(struct device *dev, struct device_attribute *attr,
459 const char *buf, size_t len)
460 {
461 struct mcp47feb02_data *data = iio_priv(dev_to_iio_dev(dev));
462 unsigned int i, val, val1, eewa_val;
463 bool state;
464 int ret;
465
466 ret = kstrtobool(buf, &state);
467 if (ret)
468 return ret;
469
470 if (!state)
471 return 0;
472
473 /*
474 * Verify DAC Wiper and DAC Configuration are unlocked. If both are disabled,
475 * writing to EEPROM is available.
476 */
477 ret = regmap_read(data->regmap, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR, &val);
478 if (ret)
479 return ret;
480
481 if (val) {
482 dev_err(dev, "DAC Wiper and DAC Configuration not are unlocked.\n");
483 return -EINVAL;
484 }
485
486 for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
487 ret = mcp47feb02_write_to_eeprom(data, NV_REG_ADDR(i),
488 data->chdata[i].dac_data);
489 if (ret)
490 return ret;
491 }
492
493 ret = regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &val);
494 if (ret)
495 return ret;
496
497 ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_VREF_REG_ADDR, val);
498 if (ret)
499 return ret;
500
501 ret = regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &val);
502 if (ret)
503 return ret;
504
505 ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_POWER_DOWN_REG_ADDR, val);
506 if (ret)
507 return ret;
508
509 ret = regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, eewa_val,
510 !(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK),
511 USEC_PER_MSEC, USEC_PER_MSEC * 5);
512 if (ret)
513 return ret;
514
515 ret = regmap_read(data->regmap, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR, &val);
516 if (ret)
517 return ret;
518
519 ret = regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &val1);
520 if (ret)
521 return ret;
522
523 ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR,
524 (val1 & MCP47FEB02_GAIN_BITS_MASK) |
525 (val & MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK));
526 if (ret)
527 return ret;
528
529 return len;
530 }
531
532 static IIO_DEVICE_ATTR_WO(store_eeprom, 0);
533
534 static struct attribute *mcp47feb02_attributes[] = {
535 &iio_dev_attr_store_eeprom.dev_attr.attr,
536 NULL
537 };
538
539 static const struct attribute_group mcp47feb02_attribute_group = {
540 .attrs = mcp47feb02_attributes,
541 };
542
mcp47feb02_suspend(struct device * dev)543 static int mcp47feb02_suspend(struct device *dev)
544 {
545 struct iio_dev *indio_dev = dev_get_drvdata(dev);
546 struct mcp47feb02_data *data = iio_priv(indio_dev);
547 int ret;
548 u8 ch;
549
550 guard(mutex)(&data->lock);
551
552 for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) {
553 u8 pd_mode;
554
555 data->chdata[ch].powerdown = true;
556 pd_mode = data->chdata[ch].powerdown_mode + 1;
557 ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
558 DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode));
559 if (ret)
560 return ret;
561
562 ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
563 if (ret)
564 return ret;
565 }
566
567 return 0;
568 }
569
mcp47feb02_resume(struct device * dev)570 static int mcp47feb02_resume(struct device *dev)
571 {
572 struct iio_dev *indio_dev = dev_get_drvdata(dev);
573 struct mcp47feb02_data *data = iio_priv(indio_dev);
574 u8 ch;
575
576 guard(mutex)(&data->lock);
577
578 for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) {
579 u8 pd_mode;
580 int ret;
581
582 data->chdata[ch].powerdown = false;
583 pd_mode = data->chdata[ch].powerdown_mode + 1;
584
585 ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
586 if (ret)
587 return ret;
588
589 ret = regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR,
590 DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode));
591 if (ret)
592 return ret;
593
594 ret = regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
595 DAC_GAIN_MASK(ch),
596 DAC_GAIN_VAL(ch, data->chdata[ch].use_2x_gain));
597 if (ret)
598 return ret;
599
600 ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
601 DAC_CTRL_MASK(ch),
602 DAC_CTRL_VAL(ch, MCP47FEB02_NORMAL_OPERATION));
603 if (ret)
604 return ret;
605 }
606
607 return 0;
608 }
609
mcp47feb02_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)610 static int mcp47feb02_get_powerdown_mode(struct iio_dev *indio_dev,
611 const struct iio_chan_spec *chan)
612 {
613 struct mcp47feb02_data *data = iio_priv(indio_dev);
614
615 return data->chdata[chan->address].powerdown_mode;
616 }
617
mcp47feb02_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * ch,unsigned int mode)618 static int mcp47feb02_set_powerdown_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *ch,
619 unsigned int mode)
620 {
621 struct mcp47feb02_data *data = iio_priv(indio_dev);
622
623 data->chdata[ch->address].powerdown_mode = mode;
624
625 return 0;
626 }
627
mcp47feb02_read_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * ch,char * buf)628 static ssize_t mcp47feb02_read_powerdown(struct iio_dev *indio_dev, uintptr_t private,
629 const struct iio_chan_spec *ch, char *buf)
630 {
631 struct mcp47feb02_data *data = iio_priv(indio_dev);
632
633 /* Print if channel is in a power-down mode or not */
634 return sysfs_emit(buf, "%d\n", data->chdata[ch->address].powerdown);
635 }
636
mcp47feb02_write_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * ch,const char * buf,size_t len)637 static ssize_t mcp47feb02_write_powerdown(struct iio_dev *indio_dev, uintptr_t private,
638 const struct iio_chan_spec *ch, const char *buf,
639 size_t len)
640 {
641 struct mcp47feb02_data *data = iio_priv(indio_dev);
642 u32 reg = ch->address;
643 u8 tmp_pd_mode;
644 bool state;
645 int ret;
646
647 guard(mutex)(&data->lock);
648
649 ret = kstrtobool(buf, &state);
650 if (ret)
651 return ret;
652
653 /*
654 * Set the channel to the specified power-down mode. Exiting power-down mode
655 * requires writing normal operation mode (0) to the channel-specific register bits.
656 */
657 tmp_pd_mode = state ? (data->chdata[reg].powerdown_mode + 1) : MCP47FEB02_NORMAL_OPERATION;
658 ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
659 DAC_CTRL_MASK(reg), DAC_CTRL_VAL(reg, tmp_pd_mode));
660 if (ret)
661 return ret;
662
663 data->chdata[reg].powerdown = state;
664
665 return len;
666 }
667
668 static DEFINE_SIMPLE_DEV_PM_OPS(mcp47feb02_pm_ops, mcp47feb02_suspend, mcp47feb02_resume);
669
670 static const struct iio_enum mcp47febxx_powerdown_mode_enum = {
671 .items = mcp47feb02_powerdown_modes,
672 .num_items = ARRAY_SIZE(mcp47feb02_powerdown_modes),
673 .get = mcp47feb02_get_powerdown_mode,
674 .set = mcp47feb02_set_powerdown_mode,
675 };
676
677 static const struct iio_chan_spec_ext_info mcp47feb02_ext_info[] = {
678 {
679 .name = "powerdown",
680 .read = mcp47feb02_read_powerdown,
681 .write = mcp47feb02_write_powerdown,
682 .shared = IIO_SEPARATE,
683 },
684 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp47febxx_powerdown_mode_enum),
685 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &mcp47febxx_powerdown_mode_enum),
686 { }
687 };
688
689 static const struct iio_chan_spec mcp47febxx_ch_template = {
690 .type = IIO_VOLTAGE,
691 .output = 1,
692 .indexed = 1,
693 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
694 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
695 .ext_info = mcp47feb02_ext_info,
696 };
697
mcp47feb02_init_scale(struct mcp47feb02_data * data,enum mcp47feb02_scale scale,int vref_uV,int scale_avail[])698 static void mcp47feb02_init_scale(struct mcp47feb02_data *data, enum mcp47feb02_scale scale,
699 int vref_uV, int scale_avail[])
700 {
701 u32 value_micro, value_int;
702 u64 tmp;
703
704 /* vref_uV should not be negative */
705 tmp = (u64)vref_uV * MILLI >> data->chip_features->resolution;
706 value_int = div_u64_rem(tmp, MICRO, &value_micro);
707 scale_avail[scale * 2] = value_int;
708 scale_avail[scale * 2 + 1] = value_micro;
709 }
710
mcp47feb02_init_scales_avail(struct mcp47feb02_data * data,int vdd_uV,int vref_uV,int vref1_uV)711 static int mcp47feb02_init_scales_avail(struct mcp47feb02_data *data, int vdd_uV,
712 int vref_uV, int vref1_uV)
713 {
714 int tmp_vref;
715
716 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_uV, data->scale);
717
718 if (data->use_vref)
719 tmp_vref = vref_uV;
720 else
721 tmp_vref = MCP47FEB02_INTERNAL_BAND_GAP_uV;
722
723 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1, tmp_vref, data->scale);
724 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2, tmp_vref * 2, data->scale);
725
726 if (data->phys_channels >= 4) {
727 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_uV, data->scale_1);
728
729 if (data->use_vref1)
730 tmp_vref = vref1_uV;
731 else
732 tmp_vref = MCP47FEB02_INTERNAL_BAND_GAP_uV;
733
734 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1,
735 tmp_vref, data->scale_1);
736 mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2,
737 tmp_vref * 2, data->scale_1);
738 }
739
740 return 0;
741 }
742
mcp47feb02_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * ch,const int ** vals,int * type,int * length,long info)743 static int mcp47feb02_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
744 const int **vals, int *type, int *length, long info)
745 {
746 struct mcp47feb02_data *data = iio_priv(indio_dev);
747
748 switch (info) {
749 case IIO_CHAN_INFO_SCALE:
750 switch (ch->type) {
751 case IIO_VOLTAGE:
752 if (data->phys_channels >= 4 && (ch->address % 2))
753 *vals = data->scale_1;
754 else
755 *vals = data->scale;
756
757 *length = 2 * MCP47FEB02_MAX_SCALES_CH;
758 *type = IIO_VAL_INT_PLUS_MICRO;
759 return IIO_AVAIL_LIST;
760 default:
761 return -EINVAL;
762 }
763 default:
764 return -EINVAL;
765 }
766 }
767
mcp47feb02_get_scale(int ch,struct mcp47feb02_data * data,int * val,int * val2)768 static void mcp47feb02_get_scale(int ch, struct mcp47feb02_data *data, int *val, int *val2)
769 {
770 enum mcp47feb02_scale current_scale;
771
772 if (data->chdata[ch].ref_mode == MCP47FEB02_VREF_VDD)
773 current_scale = MCP47FEB02_SCALE_VDD;
774 else if (data->chdata[ch].use_2x_gain)
775 current_scale = MCP47FEB02_SCALE_GAIN_X2;
776 else
777 current_scale = MCP47FEB02_SCALE_GAIN_X1;
778
779 if (data->phys_channels >= 4 && (ch % 2)) {
780 *val = data->scale_1[current_scale * 2];
781 *val2 = data->scale_1[current_scale * 2 + 1];
782 } else {
783 *val = data->scale[current_scale * 2];
784 *val2 = data->scale[current_scale * 2 + 1];
785 }
786 }
787
mcp47feb02_check_scale(struct mcp47feb02_data * data,int val,int val2,int scale[])788 static int mcp47feb02_check_scale(struct mcp47feb02_data *data, int val, int val2, int scale[])
789 {
790 unsigned int i;
791
792 for (i = 0; i < MCP47FEB02_MAX_SCALES_CH; i++) {
793 if (scale[i * 2] == val && scale[i * 2 + 1] == val2)
794 return i;
795 }
796
797 return -EINVAL;
798 }
799
mcp47feb02_ch_scale(struct mcp47feb02_data * data,int ch,int scale)800 static int mcp47feb02_ch_scale(struct mcp47feb02_data *data, int ch, int scale)
801 {
802 int tmp_val, ret;
803
804 if (scale == MCP47FEB02_SCALE_VDD) {
805 tmp_val = MCP47FEB02_VREF_VDD;
806 } else if (data->phys_channels >= 4 && (ch % 2)) {
807 if (data->use_vref1) {
808 if (data->vref1_buffered)
809 tmp_val = MCP47FEB02_EXTERNAL_VREF_BUFFERED;
810 else
811 tmp_val = MCP47FEB02_EXTERNAL_VREF_UNBUFFERED;
812 } else {
813 tmp_val = MCP47FEB02_INTERNAL_BAND_GAP;
814 }
815 } else if (data->use_vref) {
816 if (data->vref_buffered)
817 tmp_val = MCP47FEB02_EXTERNAL_VREF_BUFFERED;
818 else
819 tmp_val = MCP47FEB02_EXTERNAL_VREF_UNBUFFERED;
820 } else {
821 tmp_val = MCP47FEB02_INTERNAL_BAND_GAP;
822 }
823
824 ret = regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR,
825 DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, tmp_val));
826 if (ret)
827 return ret;
828
829 data->chdata[ch].ref_mode = tmp_val;
830
831 return 0;
832 }
833
834 /*
835 * Setting the scale in order to choose between VDD and (Vref or Band Gap) from the user
836 * space. The VREF pin is either an input or an output, therefore the user cannot
837 * simultaneously connect an external voltage reference to the pin and select the
838 * internal Band Gap.
839 * When the DAC’s voltage reference is configured as the VREF pin, the pin is an input.
840 * When the DAC’s voltage reference is configured as the internal Band Gap,
841 * the VREF pin is an output.
842 * If Vref/Vref1 voltage is not available, then the internal Band Gap will be used
843 * to calculate the values for the scale.
844 */
mcp47feb02_set_scale(struct mcp47feb02_data * data,int ch,int scale)845 static int mcp47feb02_set_scale(struct mcp47feb02_data *data, int ch, int scale)
846 {
847 int tmp_val, ret;
848
849 ret = mcp47feb02_ch_scale(data, ch, scale);
850 if (ret)
851 return ret;
852
853 if (scale == MCP47FEB02_SCALE_GAIN_X2)
854 tmp_val = MCP47FEB02_GAIN_BIT_X2;
855 else
856 tmp_val = MCP47FEB02_GAIN_BIT_X1;
857
858 ret = regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
859 DAC_GAIN_MASK(ch), DAC_GAIN_VAL(ch, tmp_val));
860 if (ret)
861 return ret;
862
863 data->chdata[ch].use_2x_gain = tmp_val;
864
865 return 0;
866 }
867
mcp47feb02_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * ch,int * val,int * val2,long mask)868 static int mcp47feb02_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
869 int *val, int *val2, long mask)
870 {
871 struct mcp47feb02_data *data = iio_priv(indio_dev);
872 int ret;
873
874 switch (mask) {
875 case IIO_CHAN_INFO_RAW:
876 ret = regmap_read(data->regmap, REG_ADDR(ch->address), val);
877 if (ret)
878 return ret;
879 return IIO_VAL_INT;
880 case IIO_CHAN_INFO_SCALE:
881 mcp47feb02_get_scale(ch->address, data, val, val2);
882 return IIO_VAL_INT_PLUS_MICRO;
883 default:
884 return -EINVAL;
885 }
886 }
887
mcp47feb02_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * ch,int val,int val2,long mask)888 static int mcp47feb02_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
889 int val, int val2, long mask)
890 {
891 struct mcp47feb02_data *data = iio_priv(indio_dev);
892 int *tmp_scale, ret;
893
894 guard(mutex)(&data->lock);
895
896 switch (mask) {
897 case IIO_CHAN_INFO_RAW:
898 ret = regmap_write(data->regmap, REG_ADDR(ch->address), val);
899 if (ret)
900 return ret;
901
902 data->chdata[ch->address].dac_data = val;
903 return 0;
904 case IIO_CHAN_INFO_SCALE:
905 if (data->phys_channels >= 4 && (ch->address % 2))
906 tmp_scale = data->scale_1;
907 else
908 tmp_scale = data->scale;
909
910 ret = mcp47feb02_check_scale(data, val, val2, tmp_scale);
911 if (ret < 0)
912 return ret;
913
914 return mcp47feb02_set_scale(data, ch->address, ret);
915 default:
916 return -EINVAL;
917 }
918 }
919
mcp47feb02_read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * ch,char * label)920 static int mcp47feb02_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
921 char *label)
922 {
923 struct mcp47feb02_data *data = iio_priv(indio_dev);
924
925 return sysfs_emit(label, "%s\n", data->labels[ch->address]);
926 }
927
928 static const struct iio_info mcp47feb02_info = {
929 .read_raw = mcp47feb02_read_raw,
930 .write_raw = mcp47feb02_write_raw,
931 .read_label = mcp47feb02_read_label,
932 .read_avail = &mcp47feb02_read_avail,
933 .attrs = &mcp47feb02_attribute_group,
934 };
935
936 static const struct iio_info mcp47fvb02_info = {
937 .read_raw = mcp47feb02_read_raw,
938 .write_raw = mcp47feb02_write_raw,
939 .read_label = mcp47feb02_read_label,
940 .read_avail = &mcp47feb02_read_avail,
941 };
942
mcp47feb02_parse_fw(struct iio_dev * indio_dev,const struct mcp47feb02_features * chip_features)943 static int mcp47feb02_parse_fw(struct iio_dev *indio_dev,
944 const struct mcp47feb02_features *chip_features)
945 {
946 struct iio_chan_spec chanspec = mcp47febxx_ch_template;
947 struct mcp47feb02_data *data = iio_priv(indio_dev);
948 struct device *dev = regmap_get_device(data->regmap);
949 struct iio_chan_spec *channels;
950 u32 num_channels;
951 u8 chan_idx = 0;
952
953 num_channels = device_get_child_node_count(dev);
954 if (num_channels > chip_features->phys_channels)
955 return dev_err_probe(dev, -EINVAL, "More channels than the chip supports\n");
956
957 if (!num_channels)
958 return dev_err_probe(dev, -EINVAL, "No channel specified in the devicetree.\n");
959
960 channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL);
961 if (!channels)
962 return -ENOMEM;
963
964 device_for_each_child_node_scoped(dev, child) {
965 u32 reg = 0;
966 int ret;
967
968 ret = fwnode_property_read_u32(child, "reg", ®);
969 if (ret)
970 return dev_err_probe(dev, ret, "Invalid channel number\n");
971
972 if (reg >= chip_features->phys_channels)
973 return dev_err_probe(dev, -EINVAL,
974 "The index of the channels does not match the chip\n");
975
976 set_bit(reg, &data->active_channels_mask);
977
978 ret = fwnode_property_read_string(child, "label", &data->labels[reg]);
979 if (ret)
980 return dev_err_probe(dev, ret, "%pfw: invalid label\n",
981 fwnode_get_name(child));
982
983 chanspec.address = reg;
984 chanspec.channel = reg;
985 channels[chan_idx] = chanspec;
986 chan_idx++;
987 }
988
989 indio_dev->num_channels = num_channels;
990 indio_dev->channels = channels;
991 indio_dev->modes = INDIO_DIRECT_MODE;
992 data->phys_channels = chip_features->phys_channels;
993
994 data->vref_buffered = device_property_read_bool(dev, "microchip,vref-buffered");
995
996 if (chip_features->have_ext_vref1)
997 data->vref1_buffered = device_property_read_bool(dev, "microchip,vref1-buffered");
998
999 return 0;
1000 }
1001
mcp47feb02_init_ctrl_regs(struct mcp47feb02_data * data)1002 static int mcp47feb02_init_ctrl_regs(struct mcp47feb02_data *data)
1003 {
1004 unsigned int i, vref_ch, gain_ch, pd_ch;
1005 int ret;
1006
1007 ret = regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &vref_ch);
1008 if (ret)
1009 return ret;
1010
1011 ret = regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &gain_ch);
1012 if (ret)
1013 return ret;
1014
1015 ret = regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &pd_ch);
1016 if (ret)
1017 return ret;
1018
1019 gain_ch = gain_ch & MCP47FEB02_GAIN_BITS_MASK;
1020 for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
1021 struct device *dev = regmap_get_device(data->regmap);
1022 unsigned int pd_tmp;
1023
1024 data->chdata[i].ref_mode = (vref_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_MASK;
1025 data->chdata[i].use_2x_gain = (gain_ch >> i) & MCP47FEB02_GAIN_BIT_MASK;
1026
1027 /*
1028 * Inform the user that the current voltage reference read from the volatile
1029 * register of the chip is different from the one specified in the device tree.
1030 * Considering that the user cannot have an external voltage reference connected
1031 * to the pin and select the internal Band Gap at the same time, in order to avoid
1032 * miscofiguring the reference voltage, the volatile register will not be written.
1033 * In order to overwrite the setting from volatile register with the one from the
1034 * device tree, the user needs to write the chosen scale.
1035 */
1036 switch (data->chdata[i].ref_mode) {
1037 case MCP47FEB02_INTERNAL_BAND_GAP:
1038 if (data->phys_channels >= 4 && (i % 2) && data->use_vref1) {
1039 dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i);
1040 dev_dbg(dev, "ch[%u]: reference voltage set to VREF1", i);
1041 break;
1042 }
1043 if ((data->phys_channels < 4 || (data->phys_channels >= 4 && !(i % 2))) &&
1044 data->use_vref) {
1045 dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i);
1046 dev_dbg(dev, "ch[%u]: reference voltage set to VREF", i);
1047 break;
1048 }
1049 break;
1050 case MCP47FEB02_EXTERNAL_VREF_UNBUFFERED:
1051 case MCP47FEB02_EXTERNAL_VREF_BUFFERED:
1052 if (data->phys_channels >= 4 && (i % 2) && !data->use_vref1) {
1053 dev_dbg(dev, "ch[%u]: was configured to use VREF1", i);
1054 dev_dbg(dev,
1055 "ch[%u]: reference voltage set to internal band gap", i);
1056 break;
1057 }
1058 if ((data->phys_channels < 4 || (data->phys_channels >= 4 && !(i % 2))) &&
1059 !data->use_vref) {
1060 dev_dbg(dev, "ch[%u]: was configured to use VREF", i);
1061 dev_dbg(dev,
1062 "ch[%u]: reference voltage set to internal band gap", i);
1063 break;
1064 }
1065 break;
1066 }
1067
1068 pd_tmp = (pd_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_MASK;
1069 data->chdata[i].powerdown_mode = pd_tmp ? (pd_tmp - 1) : pd_tmp;
1070 data->chdata[i].powerdown = !!(data->chdata[i].powerdown_mode);
1071 }
1072
1073 return 0;
1074 }
1075
mcp47feb02_init_ch_scales(struct mcp47feb02_data * data,int vdd_uV,int vref_uV,int vref1_uV)1076 static int mcp47feb02_init_ch_scales(struct mcp47feb02_data *data, int vdd_uV,
1077 int vref_uV, int vref1_uV)
1078 {
1079 unsigned int i;
1080
1081 for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
1082 struct device *dev = regmap_get_device(data->regmap);
1083 int ret;
1084
1085 ret = mcp47feb02_init_scales_avail(data, vdd_uV, vref_uV, vref1_uV);
1086 if (ret)
1087 return dev_err_probe(dev, ret, "failed to init scales for ch %u\n", i);
1088 }
1089
1090 return 0;
1091 }
1092
mcp47feb02_probe(struct i2c_client * client)1093 static int mcp47feb02_probe(struct i2c_client *client)
1094 {
1095 const struct mcp47feb02_features *chip_features;
1096 struct device *dev = &client->dev;
1097 struct mcp47feb02_data *data;
1098 struct iio_dev *indio_dev;
1099 int vref1_uV, vref_uV, vdd_uV, ret;
1100
1101 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1102 if (!indio_dev)
1103 return -ENOMEM;
1104
1105 data = iio_priv(indio_dev);
1106 chip_features = i2c_get_match_data(client);
1107 if (!chip_features)
1108 return -EINVAL;
1109
1110 data->chip_features = chip_features;
1111
1112 if (chip_features->have_eeprom) {
1113 data->regmap = devm_regmap_init_i2c(client, &mcp47feb02_regmap_config);
1114 indio_dev->info = &mcp47feb02_info;
1115 } else {
1116 data->regmap = devm_regmap_init_i2c(client, &mcp47fvb02_regmap_config);
1117 indio_dev->info = &mcp47fvb02_info;
1118 }
1119 if (IS_ERR(data->regmap))
1120 return dev_err_probe(dev, PTR_ERR(data->regmap), "Error initializing i2c regmap\n");
1121
1122 indio_dev->name = chip_features->name;
1123
1124 ret = mcp47feb02_parse_fw(indio_dev, chip_features);
1125 if (ret)
1126 return dev_err_probe(dev, ret, "Error parsing firmware data\n");
1127
1128 ret = devm_mutex_init(dev, &data->lock);
1129 if (ret)
1130 return ret;
1131
1132 ret = devm_regulator_get_enable_read_voltage(dev, "vdd");
1133 if (ret < 0)
1134 return ret;
1135
1136 vdd_uV = ret;
1137
1138 if (device_property_present(dev, "vref-supply")) {
1139 vref_uV = devm_regulator_get_enable_read_voltage(dev, "vref");
1140 if (vref_uV < 0)
1141 return vref_uV;
1142
1143 if (vref_uV == 0)
1144 return dev_err_probe(dev, -EINVAL, "Vref is 0 uV.\n");
1145
1146 data->use_vref = true;
1147 } else {
1148 vref_uV = 0;
1149 dev_dbg(dev, "Using internal band gap as voltage reference.\n");
1150 }
1151
1152 if (chip_features->have_ext_vref1 &&
1153 device_property_present(dev, "vref1-supply")) {
1154 vref1_uV = devm_regulator_get_enable_read_voltage(dev, "vref1");
1155 if (vref1_uV < 0)
1156 return vref1_uV;
1157
1158 if (vref1_uV == 0)
1159 return dev_err_probe(dev, -EINVAL, "Vref1 is 0 uV.\n");
1160
1161 data->use_vref1 = true;
1162 } else {
1163 vref1_uV = 0;
1164 dev_dbg(dev, "Using internal band gap as voltage reference 1.\n");
1165 }
1166
1167 ret = mcp47feb02_init_ctrl_regs(data);
1168 if (ret)
1169 return dev_err_probe(dev, ret, "Error initialising vref register\n");
1170
1171 ret = mcp47feb02_init_ch_scales(data, vdd_uV, vref_uV, vref1_uV);
1172 if (ret)
1173 return ret;
1174
1175 return devm_iio_device_register(dev, indio_dev);
1176 }
1177
1178 static const struct i2c_device_id mcp47feb02_id[] = {
1179 { .name = "mcp47feb01", .driver_data = (kernel_ulong_t)&mcp47feb01_chip_features },
1180 { .name = "mcp47feb02", .driver_data = (kernel_ulong_t)&mcp47feb02_chip_features },
1181 { .name = "mcp47feb04", .driver_data = (kernel_ulong_t)&mcp47feb04_chip_features },
1182 { .name = "mcp47feb08", .driver_data = (kernel_ulong_t)&mcp47feb08_chip_features },
1183 { .name = "mcp47feb11", .driver_data = (kernel_ulong_t)&mcp47feb11_chip_features },
1184 { .name = "mcp47feb12", .driver_data = (kernel_ulong_t)&mcp47feb12_chip_features },
1185 { .name = "mcp47feb14", .driver_data = (kernel_ulong_t)&mcp47feb14_chip_features },
1186 { .name = "mcp47feb18", .driver_data = (kernel_ulong_t)&mcp47feb18_chip_features },
1187 { .name = "mcp47feb21", .driver_data = (kernel_ulong_t)&mcp47feb21_chip_features },
1188 { .name = "mcp47feb22", .driver_data = (kernel_ulong_t)&mcp47feb22_chip_features },
1189 { .name = "mcp47feb24", .driver_data = (kernel_ulong_t)&mcp47feb24_chip_features },
1190 { .name = "mcp47feb28", .driver_data = (kernel_ulong_t)&mcp47feb28_chip_features },
1191 { .name = "mcp47fvb01", .driver_data = (kernel_ulong_t)&mcp47fvb01_chip_features },
1192 { .name = "mcp47fvb02", .driver_data = (kernel_ulong_t)&mcp47fvb02_chip_features },
1193 { .name = "mcp47fvb04", .driver_data = (kernel_ulong_t)&mcp47fvb04_chip_features },
1194 { .name = "mcp47fvb08", .driver_data = (kernel_ulong_t)&mcp47fvb08_chip_features },
1195 { .name = "mcp47fvb11", .driver_data = (kernel_ulong_t)&mcp47fvb11_chip_features },
1196 { .name = "mcp47fvb12", .driver_data = (kernel_ulong_t)&mcp47fvb12_chip_features },
1197 { .name = "mcp47fvb14", .driver_data = (kernel_ulong_t)&mcp47fvb14_chip_features },
1198 { .name = "mcp47fvb18", .driver_data = (kernel_ulong_t)&mcp47fvb18_chip_features },
1199 { .name = "mcp47fvb21", .driver_data = (kernel_ulong_t)&mcp47fvb21_chip_features },
1200 { .name = "mcp47fvb22", .driver_data = (kernel_ulong_t)&mcp47fvb22_chip_features },
1201 { .name = "mcp47fvb24", .driver_data = (kernel_ulong_t)&mcp47fvb24_chip_features },
1202 { .name = "mcp47fvb28", .driver_data = (kernel_ulong_t)&mcp47fvb28_chip_features },
1203 { }
1204 };
1205 MODULE_DEVICE_TABLE(i2c, mcp47feb02_id);
1206
1207 static const struct of_device_id mcp47feb02_of_match[] = {
1208 { .compatible = "microchip,mcp47feb01", .data = &mcp47feb01_chip_features },
1209 { .compatible = "microchip,mcp47feb02", .data = &mcp47feb02_chip_features },
1210 { .compatible = "microchip,mcp47feb04", .data = &mcp47feb04_chip_features },
1211 { .compatible = "microchip,mcp47feb08", .data = &mcp47feb08_chip_features },
1212 { .compatible = "microchip,mcp47feb11", .data = &mcp47feb11_chip_features },
1213 { .compatible = "microchip,mcp47feb12", .data = &mcp47feb12_chip_features },
1214 { .compatible = "microchip,mcp47feb14", .data = &mcp47feb14_chip_features },
1215 { .compatible = "microchip,mcp47feb18", .data = &mcp47feb18_chip_features },
1216 { .compatible = "microchip,mcp47feb21", .data = &mcp47feb21_chip_features },
1217 { .compatible = "microchip,mcp47feb22", .data = &mcp47feb22_chip_features },
1218 { .compatible = "microchip,mcp47feb24", .data = &mcp47feb24_chip_features },
1219 { .compatible = "microchip,mcp47feb28", .data = &mcp47feb28_chip_features },
1220 { .compatible = "microchip,mcp47fvb01", .data = &mcp47fvb01_chip_features },
1221 { .compatible = "microchip,mcp47fvb02", .data = &mcp47fvb02_chip_features },
1222 { .compatible = "microchip,mcp47fvb04", .data = &mcp47fvb04_chip_features },
1223 { .compatible = "microchip,mcp47fvb08", .data = &mcp47fvb08_chip_features },
1224 { .compatible = "microchip,mcp47fvb11", .data = &mcp47fvb11_chip_features },
1225 { .compatible = "microchip,mcp47fvb12", .data = &mcp47fvb12_chip_features },
1226 { .compatible = "microchip,mcp47fvb14", .data = &mcp47fvb14_chip_features },
1227 { .compatible = "microchip,mcp47fvb18", .data = &mcp47fvb18_chip_features },
1228 { .compatible = "microchip,mcp47fvb21", .data = &mcp47fvb21_chip_features },
1229 { .compatible = "microchip,mcp47fvb22", .data = &mcp47fvb22_chip_features },
1230 { .compatible = "microchip,mcp47fvb24", .data = &mcp47fvb24_chip_features },
1231 { .compatible = "microchip,mcp47fvb28", .data = &mcp47fvb28_chip_features },
1232 { }
1233 };
1234 MODULE_DEVICE_TABLE(of, mcp47feb02_of_match);
1235
1236 static struct i2c_driver mcp47feb02_driver = {
1237 .driver = {
1238 .name = "mcp47feb02",
1239 .of_match_table = mcp47feb02_of_match,
1240 .pm = pm_sleep_ptr(&mcp47feb02_pm_ops),
1241 },
1242 .probe = mcp47feb02_probe,
1243 .id_table = mcp47feb02_id,
1244 };
1245 module_i2c_driver(mcp47feb02_driver);
1246
1247 MODULE_AUTHOR("Ariana Lazar <ariana.lazar@microchip.com>");
1248 MODULE_DESCRIPTION("IIO driver for MCP47FEB02 Multi-Channel DAC with I2C interface");
1249 MODULE_LICENSE("GPL");
1250