1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * AMCC SoC PPC4xx Crypto Driver 4 * 5 * Copyright (c) 2008 Applied Micro Circuits Corporation. 6 * All rights reserved. James Hsiao <jhsiao@amcc.com> 7 * 8 * This filr defines the register set for Security Subsystem 9 */ 10 11 #ifndef __CRYPTO4XX_REG_DEF_H__ 12 #define __CRYPTO4XX_REG_DEF_H__ 13 14 /* CRYPTO4XX Register offset */ 15 #define CRYPTO4XX_DESCRIPTOR 0x00000000 16 #define CRYPTO4XX_CTRL_STAT 0x00000000 17 #define CRYPTO4XX_SOURCE 0x00000004 18 #define CRYPTO4XX_DEST 0x00000008 19 #define CRYPTO4XX_SA 0x0000000C 20 #define CRYPTO4XX_SA_LENGTH 0x00000010 21 #define CRYPTO4XX_LENGTH 0x00000014 22 23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040 24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044 25 #define CRYPTO4XX_PDR_BASE 0x00000048 26 #define CRYPTO4XX_RDR_BASE 0x0000004c 27 #define CRYPTO4XX_RING_SIZE 0x00000050 28 #define CRYPTO4XX_RING_CTRL 0x00000054 29 #define CRYPTO4XX_INT_RING_STAT 0x00000058 30 #define CRYPTO4XX_EXT_RING_STAT 0x0000005c 31 #define CRYPTO4XX_IO_THRESHOLD 0x00000060 32 #define CRYPTO4XX_GATH_RING_BASE 0x00000064 33 #define CRYPTO4XX_SCAT_RING_BASE 0x00000068 34 #define CRYPTO4XX_PART_RING_SIZE 0x0000006c 35 #define CRYPTO4XX_PART_RING_CFG 0x00000070 36 37 #define CRYPTO4XX_PDR_BASE_UADDR 0x00000080 38 #define CRYPTO4XX_RDR_BASE_UADDR 0x00000084 39 #define CRYPTO4XX_PKT_SRC_UADDR 0x00000088 40 #define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c 41 #define CRYPTO4XX_SA_UADDR 0x00000090 42 #define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0 43 #define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4 44 45 #define CRYPTO4XX_SEQ_RD 0x00000408 46 #define CRYPTO4XX_SEQ_MASK_RD 0x0000040C 47 48 #define CRYPTO4XX_SA_CMD_0 0x00010600 49 #define CRYPTO4XX_SA_CMD_1 0x00010604 50 51 #define CRYPTO4XX_STATE_PTR 0x000106dc 52 #define CRYPTO4XX_STATE_IV 0x00010700 53 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710 54 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714 55 56 #define CRYPTO4XX_STATE_IDIGEST_0 0x00010718 57 #define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c 58 59 #define CRYPTO4XX_DATA_IN 0x00018000 60 #define CRYPTO4XX_DATA_OUT 0x0001c000 61 62 #define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0 63 #define CRYPTO4XX_INT_MASK_STAT 0x000500a4 64 #define CRYPTO4XX_INT_CLR 0x000500a4 65 #define CRYPTO4XX_INT_EN 0x000500a8 66 67 #define CRYPTO4XX_INT_PKA 0x00000002 68 #define CRYPTO4XX_INT_PDR_DONE 0x00008000 69 #define CRYPTO4XX_INT_MA_WR_ERR 0x00020000 70 #define CRYPTO4XX_INT_MA_RD_ERR 0x00010000 71 #define CRYPTO4XX_INT_PE_ERR 0x00000200 72 #define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040 73 #define CRYPTO4XX_INT_SLAVE_ERR 0x00000010 74 #define CRYPTO4XX_INT_MASTER_ERR 0x00000008 75 #define CRYPTO4XX_INT_ERROR 0x00030258 76 77 #define CRYPTO4XX_INT_CFG 0x000500ac 78 #define CRYPTO4XX_INT_DESCR_RD 0x000500b0 79 #define CRYPTO4XX_INT_DESCR_CNT 0x000500b4 80 #define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8 81 82 #define CRYPTO4XX_DEVICE_CTRL 0x00060080 83 #define CRYPTO4XX_DEVICE_ID 0x00060084 84 #define CRYPTO4XX_DEVICE_INFO 0x00060088 85 #define CRYPTO4XX_DMA_USER_SRC 0x00060094 86 #define CRYPTO4XX_DMA_USER_DEST 0x00060098 87 #define CRYPTO4XX_DMA_USER_CMD 0x0006009C 88 89 #define CRYPTO4XX_DMA_CFG 0x000600d4 90 #define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8 91 #define CRYPTO4XX_ENDIAN_CFG 0x000600d8 92 93 #define CRYPTO4XX_PRNG_CTRL 0x00070004 94 #define CRYPTO4XX_PRNG_SEED_L 0x00070008 95 #define CRYPTO4XX_PRNG_SEED_H 0x0007000c 96 /* 97 * Initialize CRYPTO ENGINE registers, and memory bases. 98 */ 99 #define PPC4XX_PDR_POLL 0x3ff 100 #define PPC4XX_OUTPUT_THRESHOLD 2 101 #define PPC4XX_INPUT_THRESHOLD 2 102 #define PPC4XX_PD_SIZE 6 103 #define PPC4XX_CTX_DONE_INT 0x2000 104 #define PPC4XX_PD_DONE_INT 0x8000 105 #define PPC4XX_TMO_ERR_INT 0x40000 106 #define PPC4XX_BYTE_ORDER 0x22222 107 #define PPC4XX_INTERRUPT_CLR 0x3ffff 108 #define PPC4XX_PRNG_CTRL_AUTO_EN 0x3 109 #define PPC4XX_DC_3DES_EN 1 110 #define PPC4XX_TRNG_EN 0x00020000 111 #define PPC4XX_INT_DESCR_CNT 7 112 #define PPC4XX_INT_TIMEOUT_CNT 0 113 #define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF 114 #define PPC4XX_INT_CFG 1 115 /* 116 * all follow define are ad hoc 117 */ 118 #define PPC4XX_RING_RETRY 100 119 #define PPC4XX_RING_POLL 100 120 #define PPC4XX_SDR_SIZE PPC4XX_NUM_SD 121 #define PPC4XX_GDR_SIZE PPC4XX_NUM_GD 122 123 /* 124 * Generic Security Association (SA) with all possible fields. These will 125 * never likely used except for reference purpose. These structure format 126 * can be not changed as the hardware expects them to be layout as defined. 127 * Field can be removed or reduced but ordering can not be changed. 128 */ 129 #define CRYPTO4XX_DMA_CFG_OFFSET 0x40 130 union ce_pe_dma_cfg { 131 struct { 132 u32 rsv:7; 133 u32 dir_host:1; 134 u32 rsv1:2; 135 u32 bo_td_en:1; 136 u32 dis_pdr_upd:1; 137 u32 bo_sgpd_en:1; 138 u32 bo_data_en:1; 139 u32 bo_sa_en:1; 140 u32 bo_pd_en:1; 141 u32 rsv2:4; 142 u32 dynamic_sa_en:1; 143 u32 pdr_mode:2; 144 u32 pe_mode:1; 145 u32 rsv3:5; 146 u32 reset_sg:1; 147 u32 reset_pdr:1; 148 u32 reset_pe:1; 149 } bf; 150 u32 w; 151 } __attribute__((packed)); 152 153 #define CRYPTO4XX_PDR_BASE_OFFSET 0x48 154 #define CRYPTO4XX_RDR_BASE_OFFSET 0x4c 155 #define CRYPTO4XX_RING_SIZE_OFFSET 0x50 156 union ce_ring_size { 157 struct { 158 u32 ring_offset:16; 159 u32 rsv:6; 160 u32 ring_size:10; 161 } bf; 162 u32 w; 163 } __attribute__((packed)); 164 165 #define CRYPTO4XX_RING_CONTROL_OFFSET 0x54 166 union ce_ring_control { 167 struct { 168 u32 continuous:1; 169 u32 rsv:5; 170 u32 ring_retry_divisor:10; 171 u32 rsv1:4; 172 u32 ring_poll_divisor:10; 173 } bf; 174 u32 w; 175 } __attribute__((packed)); 176 177 #define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60 178 union ce_io_threshold { 179 struct { 180 u32 rsv:6; 181 u32 output_threshold:10; 182 u32 rsv1:6; 183 u32 input_threshold:10; 184 } bf; 185 u32 w; 186 } __attribute__((packed)); 187 188 #define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64 189 #define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68 190 191 union ce_part_ring_size { 192 struct { 193 u32 sdr_size:16; 194 u32 gdr_size:16; 195 } bf; 196 u32 w; 197 } __attribute__((packed)); 198 199 #define MAX_BURST_SIZE_32 0 200 #define MAX_BURST_SIZE_64 1 201 #define MAX_BURST_SIZE_128 2 202 #define MAX_BURST_SIZE_256 3 203 204 /* gather descriptor control length */ 205 struct gd_ctl_len { 206 u32 len:16; 207 u32 rsv:14; 208 u32 done:1; 209 u32 ready:1; 210 } __attribute__((packed)); 211 212 struct ce_gd { 213 u32 ptr; 214 struct gd_ctl_len ctl_len; 215 } __attribute__((packed)); 216 217 struct sd_ctl { 218 u32 ctl:30; 219 u32 done:1; 220 u32 rdy:1; 221 } __attribute__((packed)); 222 223 struct ce_sd { 224 u32 ptr; 225 struct sd_ctl ctl; 226 } __attribute__((packed)); 227 228 #define PD_PAD_CTL_32 0x10 229 #define PD_PAD_CTL_64 0x20 230 #define PD_PAD_CTL_128 0x40 231 #define PD_PAD_CTL_256 0x80 232 union ce_pd_ctl { 233 struct { 234 u32 pd_pad_ctl:8; 235 u32 status:8; 236 u32 next_hdr:8; 237 u32 rsv:2; 238 u32 cached_sa:1; 239 u32 hash_final:1; 240 u32 init_arc4:1; 241 u32 rsv1:1; 242 u32 pe_done:1; 243 u32 host_ready:1; 244 } bf; 245 u32 w; 246 } __attribute__((packed)); 247 #define PD_CTL_HASH_FINAL BIT(4) 248 #define PD_CTL_PE_DONE BIT(1) 249 #define PD_CTL_HOST_READY BIT(0) 250 251 union ce_pd_ctl_len { 252 struct { 253 u32 bypass:8; 254 u32 pe_done:1; 255 u32 host_ready:1; 256 u32 rsv:2; 257 u32 pkt_len:20; 258 } bf; 259 u32 w; 260 } __attribute__((packed)); 261 262 struct ce_pd { 263 union ce_pd_ctl pd_ctl; 264 u32 src; 265 u32 dest; 266 u32 sa; /* get from ctx->sa_dma_addr */ 267 u32 sa_len; /* only if dynamic sa is used */ 268 union ce_pd_ctl_len pd_ctl_len; 269 270 } __attribute__((packed)); 271 #endif 272