1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/iio/iio.h> 16 #include <linux/iio/buffer.h> 17 #include <linux/iio/timer/stm32-lptim-trigger.h> 18 #include <linux/iio/timer/stm32-timer-trigger.h> 19 #include <linux/iio/trigger.h> 20 #include <linux/iio/trigger_consumer.h> 21 #include <linux/iio/triggered_buffer.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/module.h> 26 #include <linux/nvmem-consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 31 #include "stm32-adc-core.h" 32 33 /* Number of linear calibration shadow registers / LINCALRDYW control bits */ 34 #define STM32H7_LINCALFACT_NUM 6 35 36 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 37 #define STM32H7_BOOST_CLKRATE 20000000UL 38 39 #define STM32_ADC_CH_MAX 20 /* max number of channels */ 40 #define STM32_ADC_CH_SZ 16 /* max channel name size */ 41 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 42 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 43 #define STM32_ADC_TIMEOUT_US 100000 44 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 45 #define STM32_ADC_HW_STOP_DELAY_MS 100 46 #define STM32_ADC_VREFINT_VOLTAGE 3300 47 48 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE 49 50 /* External trigger enable */ 51 enum stm32_adc_exten { 52 STM32_EXTEN_SWTRIG, 53 STM32_EXTEN_HWTRIG_RISING_EDGE, 54 STM32_EXTEN_HWTRIG_FALLING_EDGE, 55 STM32_EXTEN_HWTRIG_BOTH_EDGES, 56 }; 57 58 /* extsel - trigger mux selection value */ 59 enum stm32_adc_extsel { 60 STM32_EXT0, 61 STM32_EXT1, 62 STM32_EXT2, 63 STM32_EXT3, 64 STM32_EXT4, 65 STM32_EXT5, 66 STM32_EXT6, 67 STM32_EXT7, 68 STM32_EXT8, 69 STM32_EXT9, 70 STM32_EXT10, 71 STM32_EXT11, 72 STM32_EXT12, 73 STM32_EXT13, 74 STM32_EXT14, 75 STM32_EXT15, 76 STM32_EXT16, 77 STM32_EXT17, 78 STM32_EXT18, 79 STM32_EXT19, 80 STM32_EXT20, 81 }; 82 83 enum stm32_adc_int_ch { 84 STM32_ADC_INT_CH_NONE = -1, 85 STM32_ADC_INT_CH_VDDCORE, 86 STM32_ADC_INT_CH_VDDCPU, 87 STM32_ADC_INT_CH_VDDQ_DDR, 88 STM32_ADC_INT_CH_VREFINT, 89 STM32_ADC_INT_CH_VBAT, 90 STM32_ADC_INT_CH_NB, 91 }; 92 93 /** 94 * struct stm32_adc_ic - ADC internal channels 95 * @name: name of the internal channel 96 * @idx: internal channel enum index 97 */ 98 struct stm32_adc_ic { 99 const char *name; 100 u32 idx; 101 }; 102 103 static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { 104 { "vddcore", STM32_ADC_INT_CH_VDDCORE }, 105 { "vddcpu", STM32_ADC_INT_CH_VDDCPU }, 106 { "vddq_ddr", STM32_ADC_INT_CH_VDDQ_DDR }, 107 { "vrefint", STM32_ADC_INT_CH_VREFINT }, 108 { "vbat", STM32_ADC_INT_CH_VBAT }, 109 }; 110 111 /** 112 * struct stm32_adc_trig_info - ADC trigger info 113 * @name: name of the trigger, corresponding to its source 114 * @extsel: trigger selection 115 */ 116 struct stm32_adc_trig_info { 117 const char *name; 118 enum stm32_adc_extsel extsel; 119 }; 120 121 /** 122 * struct stm32_adc_calib - optional adc calibration data 123 * @lincalfact: Linearity calibration factor 124 * @lincal_saved: Indicates that linear calibration factors are saved 125 */ 126 struct stm32_adc_calib { 127 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 128 bool lincal_saved; 129 }; 130 131 /** 132 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc 133 * @reg: register offset 134 * @mask: bitfield mask 135 * @shift: left shift 136 */ 137 struct stm32_adc_regs { 138 int reg; 139 int mask; 140 int shift; 141 }; 142 143 /** 144 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data 145 * @vrefint_cal: vrefint calibration value from nvmem 146 * @vrefint_data: vrefint actual value 147 */ 148 struct stm32_adc_vrefint { 149 u32 vrefint_cal; 150 u32 vrefint_data; 151 }; 152 153 /** 154 * struct stm32_adc_regspec - stm32 registers definition 155 * @dr: data register offset 156 * @ier_eoc: interrupt enable register & eocie bitfield 157 * @ier_ovr: interrupt enable register & overrun bitfield 158 * @isr_eoc: interrupt status register & eoc bitfield 159 * @isr_ovr: interrupt status register & overrun bitfield 160 * @sqr: reference to sequence registers array 161 * @exten: trigger control register & bitfield 162 * @extsel: trigger selection register & bitfield 163 * @res: resolution selection register & bitfield 164 * @difsel: differential mode selection register & bitfield 165 * @smpr: smpr1 & smpr2 registers offset array 166 * @smp_bits: smpr1 & smpr2 index and bitfields 167 * @or_vddcore: option register & vddcore bitfield 168 * @or_vddcpu: option register & vddcpu bitfield 169 * @or_vddq_ddr: option register & vddq_ddr bitfield 170 * @ccr_vbat: common register & vbat bitfield 171 * @ccr_vref: common register & vrefint bitfield 172 */ 173 struct stm32_adc_regspec { 174 const u32 dr; 175 const struct stm32_adc_regs ier_eoc; 176 const struct stm32_adc_regs ier_ovr; 177 const struct stm32_adc_regs isr_eoc; 178 const struct stm32_adc_regs isr_ovr; 179 const struct stm32_adc_regs *sqr; 180 const struct stm32_adc_regs exten; 181 const struct stm32_adc_regs extsel; 182 const struct stm32_adc_regs res; 183 const struct stm32_adc_regs difsel; 184 const u32 smpr[2]; 185 const struct stm32_adc_regs *smp_bits; 186 const struct stm32_adc_regs or_vddcore; 187 const struct stm32_adc_regs or_vddcpu; 188 const struct stm32_adc_regs or_vddq_ddr; 189 const struct stm32_adc_regs ccr_vbat; 190 const struct stm32_adc_regs ccr_vref; 191 }; 192 193 struct stm32_adc; 194 195 /** 196 * struct stm32_adc_cfg - stm32 compatible configuration data 197 * @regs: registers descriptions 198 * @adc_info: per instance input channels definitions 199 * @trigs: external trigger sources 200 * @clk_required: clock is required 201 * @has_vregready: vregready status flag presence 202 * @has_boostmode: boost mode support flag 203 * @has_linearcal: linear calibration support flag 204 * @has_presel: channel preselection support flag 205 * @has_oversampling: oversampling support flag 206 * @prepare: optional prepare routine (power-up, enable) 207 * @start_conv: routine to start conversions 208 * @stop_conv: routine to stop conversions 209 * @unprepare: optional unprepare routine (disable, power-down) 210 * @irq_clear: routine to clear irqs 211 * @set_ovs: routine to set oversampling configuration 212 * @smp_cycles: programmable sampling time (ADC clock cycles) 213 * @ts_int_ch: pointer to array of internal channels minimum sampling time in ns 214 */ 215 struct stm32_adc_cfg { 216 const struct stm32_adc_regspec *regs; 217 const struct stm32_adc_info *adc_info; 218 const struct stm32_adc_trig_info *trigs; 219 bool clk_required; 220 bool has_vregready; 221 bool has_boostmode; 222 bool has_linearcal; 223 bool has_presel; 224 bool has_oversampling; 225 int (*prepare)(struct iio_dev *); 226 void (*start_conv)(struct iio_dev *, bool dma); 227 void (*stop_conv)(struct iio_dev *); 228 void (*unprepare)(struct iio_dev *); 229 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); 230 void (*set_ovs)(struct iio_dev *indio_dev, u32 ovs_idx); 231 const unsigned int *smp_cycles; 232 const unsigned int *ts_int_ch; 233 }; 234 235 /** 236 * struct stm32_adc - private data of each ADC IIO instance 237 * @common: reference to ADC block common data 238 * @offset: ADC instance register offset in ADC block 239 * @cfg: compatible configuration data 240 * @completion: end of single conversion completion 241 * @buffer: data buffer + 8 bytes for timestamp if enabled 242 * @clk: clock for this adc instance 243 * @irq: interrupt for this adc instance 244 * @lock: spinlock 245 * @bufi: data buffer index 246 * @num_conv: expected number of scan conversions 247 * @res: data resolution (e.g. RES bitfield value) 248 * @trigger_polarity: external trigger polarity (e.g. exten) 249 * @dma_chan: dma channel 250 * @rx_buf: dma rx buffer cpu address 251 * @rx_dma_buf: dma rx buffer bus address 252 * @rx_buf_sz: dma rx buffer size 253 * @difsel: bitmask to set single-ended/differential channel 254 * @pcsel: bitmask to preselect channels on some devices 255 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 256 * @cal: optional calibration data on some devices 257 * @vrefint: internal reference voltage data 258 * @chan_name: channel name array 259 * @num_diff: number of differential channels 260 * @int_ch: internal channel indexes array 261 * @nsmps: number of channels with optional sample time 262 * @ovs_idx: current oversampling ratio index (in oversampling array) 263 */ 264 struct stm32_adc { 265 struct stm32_adc_common *common; 266 u32 offset; 267 const struct stm32_adc_cfg *cfg; 268 struct completion completion; 269 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8); 270 struct clk *clk; 271 int irq; 272 spinlock_t lock; /* interrupt lock */ 273 unsigned int bufi; 274 unsigned int num_conv; 275 u32 res; 276 u32 trigger_polarity; 277 struct dma_chan *dma_chan; 278 u8 *rx_buf; 279 dma_addr_t rx_dma_buf; 280 unsigned int rx_buf_sz; 281 u32 difsel; 282 u32 pcsel; 283 u32 smpr_val[2]; 284 struct stm32_adc_calib cal; 285 struct stm32_adc_vrefint vrefint; 286 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 287 u32 num_diff; 288 int int_ch[STM32_ADC_INT_CH_NB]; 289 int nsmps; 290 int ovs_idx; 291 }; 292 293 struct stm32_adc_diff_channel { 294 u32 vinp; 295 u32 vinn; 296 }; 297 298 /** 299 * struct stm32_adc_info - stm32 ADC, per instance config data 300 * @max_channels: Number of channels 301 * @resolutions: available resolutions 302 * @oversampling: available oversampling ratios 303 * @num_res: number of available resolutions 304 * @num_ovs: number of available oversampling ratios 305 */ 306 struct stm32_adc_info { 307 int max_channels; 308 const unsigned int *resolutions; 309 const unsigned int *oversampling; 310 const unsigned int num_res; 311 const unsigned int num_ovs; 312 }; 313 314 static const unsigned int stm32h7_adc_oversampling_avail[] = { 315 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 316 }; 317 318 static const unsigned int stm32mp13_adc_oversampling_avail[] = { 319 1, 2, 4, 8, 16, 32, 64, 128, 256, 320 }; 321 322 static const unsigned int stm32f4_adc_resolutions[] = { 323 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 324 12, 10, 8, 6, 325 }; 326 327 /* stm32f4 can have up to 16 channels */ 328 static const struct stm32_adc_info stm32f4_adc_info = { 329 .max_channels = 16, 330 .resolutions = stm32f4_adc_resolutions, 331 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 332 }; 333 334 static const unsigned int stm32h7_adc_resolutions[] = { 335 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 336 16, 14, 12, 10, 8, 337 }; 338 339 /* stm32h7 can have up to 20 channels */ 340 static const struct stm32_adc_info stm32h7_adc_info = { 341 .max_channels = STM32_ADC_CH_MAX, 342 .resolutions = stm32h7_adc_resolutions, 343 .oversampling = stm32h7_adc_oversampling_avail, 344 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 345 .num_ovs = ARRAY_SIZE(stm32h7_adc_oversampling_avail), 346 }; 347 348 /* stm32mp13 can have up to 19 channels */ 349 static const struct stm32_adc_info stm32mp13_adc_info = { 350 .max_channels = 19, 351 .resolutions = stm32f4_adc_resolutions, 352 .oversampling = stm32mp13_adc_oversampling_avail, 353 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 354 .num_ovs = ARRAY_SIZE(stm32mp13_adc_oversampling_avail), 355 }; 356 357 /* 358 * stm32f4_sq - describe regular sequence registers 359 * - L: sequence len (register & bit field) 360 * - SQ1..SQ16: sequence entries (register & bit field) 361 */ 362 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 363 /* L: len bit field description to be kept as first element */ 364 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 365 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 366 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 367 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 368 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 369 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 370 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 371 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 372 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 373 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 374 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 375 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 376 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 377 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 378 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 379 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 380 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 381 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 382 }; 383 384 /* STM32F4 external trigger sources for all instances */ 385 static const struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 386 { TIM1_CH1, STM32_EXT0 }, 387 { TIM1_CH2, STM32_EXT1 }, 388 { TIM1_CH3, STM32_EXT2 }, 389 { TIM2_CH2, STM32_EXT3 }, 390 { TIM2_CH3, STM32_EXT4 }, 391 { TIM2_CH4, STM32_EXT5 }, 392 { TIM2_TRGO, STM32_EXT6 }, 393 { TIM3_CH1, STM32_EXT7 }, 394 { TIM3_TRGO, STM32_EXT8 }, 395 { TIM4_CH4, STM32_EXT9 }, 396 { TIM5_CH1, STM32_EXT10 }, 397 { TIM5_CH2, STM32_EXT11 }, 398 { TIM5_CH3, STM32_EXT12 }, 399 { TIM8_CH1, STM32_EXT13 }, 400 { TIM8_TRGO, STM32_EXT14 }, 401 {}, /* sentinel */ 402 }; 403 404 /* 405 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 406 * Sorted so it can be indexed by channel number. 407 */ 408 static const struct stm32_adc_regs stm32f4_smp_bits[] = { 409 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 410 { 1, GENMASK(2, 0), 0 }, 411 { 1, GENMASK(5, 3), 3 }, 412 { 1, GENMASK(8, 6), 6 }, 413 { 1, GENMASK(11, 9), 9 }, 414 { 1, GENMASK(14, 12), 12 }, 415 { 1, GENMASK(17, 15), 15 }, 416 { 1, GENMASK(20, 18), 18 }, 417 { 1, GENMASK(23, 21), 21 }, 418 { 1, GENMASK(26, 24), 24 }, 419 { 1, GENMASK(29, 27), 27 }, 420 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 421 { 0, GENMASK(2, 0), 0 }, 422 { 0, GENMASK(5, 3), 3 }, 423 { 0, GENMASK(8, 6), 6 }, 424 { 0, GENMASK(11, 9), 9 }, 425 { 0, GENMASK(14, 12), 12 }, 426 { 0, GENMASK(17, 15), 15 }, 427 { 0, GENMASK(20, 18), 18 }, 428 { 0, GENMASK(23, 21), 21 }, 429 { 0, GENMASK(26, 24), 24 }, 430 }; 431 432 /* STM32F4 programmable sampling time (ADC clock cycles) */ 433 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 434 3, 15, 28, 56, 84, 112, 144, 480, 435 }; 436 437 static const struct stm32_adc_regspec stm32f4_adc_regspec = { 438 .dr = STM32F4_ADC_DR, 439 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 440 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE }, 441 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 442 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR }, 443 .sqr = stm32f4_sq, 444 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 445 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 446 STM32F4_EXTSEL_SHIFT }, 447 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 448 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 449 .smp_bits = stm32f4_smp_bits, 450 }; 451 452 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 453 /* L: len bit field description to be kept as first element */ 454 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 455 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 456 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 457 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 458 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 459 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 460 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 461 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 462 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 463 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 464 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 465 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 466 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 467 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 468 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 469 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 470 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 471 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 472 }; 473 474 /* STM32H7 external trigger sources for all instances */ 475 static const struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 476 { TIM1_CH1, STM32_EXT0 }, 477 { TIM1_CH2, STM32_EXT1 }, 478 { TIM1_CH3, STM32_EXT2 }, 479 { TIM2_CH2, STM32_EXT3 }, 480 { TIM3_TRGO, STM32_EXT4 }, 481 { TIM4_CH4, STM32_EXT5 }, 482 { TIM8_TRGO, STM32_EXT7 }, 483 { TIM8_TRGO2, STM32_EXT8 }, 484 { TIM1_TRGO, STM32_EXT9 }, 485 { TIM1_TRGO2, STM32_EXT10 }, 486 { TIM2_TRGO, STM32_EXT11 }, 487 { TIM4_TRGO, STM32_EXT12 }, 488 { TIM6_TRGO, STM32_EXT13 }, 489 { TIM15_TRGO, STM32_EXT14 }, 490 { TIM3_CH4, STM32_EXT15 }, 491 { LPTIM1_OUT, STM32_EXT18 }, 492 { LPTIM2_OUT, STM32_EXT19 }, 493 { LPTIM3_OUT, STM32_EXT20 }, 494 { } 495 }; 496 497 /* 498 * stm32h7_smp_bits - describe sampling time register index & bit fields 499 * Sorted so it can be indexed by channel number. 500 */ 501 static const struct stm32_adc_regs stm32h7_smp_bits[] = { 502 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 503 { 0, GENMASK(2, 0), 0 }, 504 { 0, GENMASK(5, 3), 3 }, 505 { 0, GENMASK(8, 6), 6 }, 506 { 0, GENMASK(11, 9), 9 }, 507 { 0, GENMASK(14, 12), 12 }, 508 { 0, GENMASK(17, 15), 15 }, 509 { 0, GENMASK(20, 18), 18 }, 510 { 0, GENMASK(23, 21), 21 }, 511 { 0, GENMASK(26, 24), 24 }, 512 { 0, GENMASK(29, 27), 27 }, 513 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 514 { 1, GENMASK(2, 0), 0 }, 515 { 1, GENMASK(5, 3), 3 }, 516 { 1, GENMASK(8, 6), 6 }, 517 { 1, GENMASK(11, 9), 9 }, 518 { 1, GENMASK(14, 12), 12 }, 519 { 1, GENMASK(17, 15), 15 }, 520 { 1, GENMASK(20, 18), 18 }, 521 { 1, GENMASK(23, 21), 21 }, 522 { 1, GENMASK(26, 24), 24 }, 523 { 1, GENMASK(29, 27), 27 }, 524 }; 525 526 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 527 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 528 1, 2, 8, 16, 32, 64, 387, 810, 529 }; 530 531 static const struct stm32_adc_regspec stm32h7_adc_regspec = { 532 .dr = STM32H7_ADC_DR, 533 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 534 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 535 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 536 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 537 .sqr = stm32h7_sq, 538 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 539 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 540 STM32H7_EXTSEL_SHIFT }, 541 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 542 .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 543 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 544 .smp_bits = stm32h7_smp_bits, 545 }; 546 547 /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */ 548 static const unsigned int stm32mp13_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 549 2, 6, 12, 24, 47, 92, 247, 640, 550 }; 551 552 static const struct stm32_adc_regspec stm32mp13_adc_regspec = { 553 .dr = STM32H7_ADC_DR, 554 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 555 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 556 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 557 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 558 .sqr = stm32h7_sq, 559 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 560 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 561 STM32H7_EXTSEL_SHIFT }, 562 .res = { STM32H7_ADC_CFGR, STM32MP13_RES_MASK, STM32MP13_RES_SHIFT }, 563 .difsel = { STM32MP13_ADC_DIFSEL, STM32MP13_DIFSEL_MASK}, 564 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 565 .smp_bits = stm32h7_smp_bits, 566 .or_vddcore = { STM32MP13_ADC2_OR, STM32MP13_OP0 }, 567 .or_vddcpu = { STM32MP13_ADC2_OR, STM32MP13_OP1 }, 568 .or_vddq_ddr = { STM32MP13_ADC2_OR, STM32MP13_OP2 }, 569 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 570 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 571 }; 572 573 static const struct stm32_adc_regspec stm32mp1_adc_regspec = { 574 .dr = STM32H7_ADC_DR, 575 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 576 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 577 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 578 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 579 .sqr = stm32h7_sq, 580 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 581 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 582 STM32H7_EXTSEL_SHIFT }, 583 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 584 .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 585 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 586 .smp_bits = stm32h7_smp_bits, 587 .or_vddcore = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 588 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 589 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 590 }; 591 592 /* 593 * STM32 ADC registers access routines 594 * @adc: stm32 adc instance 595 * @reg: reg offset in adc instance 596 * 597 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 598 * for adc1, adc2 and adc3. 599 */ 600 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 601 { 602 return readl_relaxed(adc->common->base + adc->offset + reg); 603 } 604 605 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 606 607 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 608 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 609 cond, sleep_us, timeout_us) 610 611 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 612 { 613 return readw_relaxed(adc->common->base + adc->offset + reg); 614 } 615 616 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 617 { 618 writel_relaxed(val, adc->common->base + adc->offset + reg); 619 } 620 621 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 622 { 623 unsigned long flags; 624 625 spin_lock_irqsave(&adc->lock, flags); 626 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 627 spin_unlock_irqrestore(&adc->lock, flags); 628 } 629 630 static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 631 { 632 spin_lock(&adc->common->lock); 633 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, 634 adc->common->base + reg); 635 spin_unlock(&adc->common->lock); 636 } 637 638 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 639 { 640 unsigned long flags; 641 642 spin_lock_irqsave(&adc->lock, flags); 643 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 644 spin_unlock_irqrestore(&adc->lock, flags); 645 } 646 647 static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 648 { 649 spin_lock(&adc->common->lock); 650 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, 651 adc->common->base + reg); 652 spin_unlock(&adc->common->lock); 653 } 654 655 /** 656 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 657 * @adc: stm32 adc instance 658 */ 659 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 660 { 661 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 662 adc->cfg->regs->ier_eoc.mask); 663 }; 664 665 /** 666 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 667 * @adc: stm32 adc instance 668 */ 669 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 670 { 671 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 672 adc->cfg->regs->ier_eoc.mask); 673 } 674 675 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) 676 { 677 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, 678 adc->cfg->regs->ier_ovr.mask); 679 } 680 681 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) 682 { 683 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, 684 adc->cfg->regs->ier_ovr.mask); 685 } 686 687 static void stm32_adc_set_res(struct stm32_adc *adc) 688 { 689 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 690 u32 val; 691 692 val = stm32_adc_readl(adc, res->reg); 693 val = (val & ~res->mask) | (adc->res << res->shift); 694 stm32_adc_writel(adc, res->reg, val); 695 } 696 697 static int stm32_adc_hw_stop(struct device *dev) 698 { 699 struct iio_dev *indio_dev = dev_get_drvdata(dev); 700 struct stm32_adc *adc = iio_priv(indio_dev); 701 702 if (adc->cfg->unprepare) 703 adc->cfg->unprepare(indio_dev); 704 705 clk_disable_unprepare(adc->clk); 706 707 return 0; 708 } 709 710 static int stm32_adc_hw_start(struct device *dev) 711 { 712 struct iio_dev *indio_dev = dev_get_drvdata(dev); 713 struct stm32_adc *adc = iio_priv(indio_dev); 714 int ret; 715 716 ret = clk_prepare_enable(adc->clk); 717 if (ret) 718 return ret; 719 720 stm32_adc_set_res(adc); 721 722 if (adc->cfg->prepare) { 723 ret = adc->cfg->prepare(indio_dev); 724 if (ret) 725 goto err_clk_dis; 726 } 727 728 return 0; 729 730 err_clk_dis: 731 clk_disable_unprepare(adc->clk); 732 733 return ret; 734 } 735 736 static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) 737 { 738 struct stm32_adc *adc = iio_priv(indio_dev); 739 u32 i; 740 741 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 742 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 743 continue; 744 745 switch (i) { 746 case STM32_ADC_INT_CH_VDDCORE: 747 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); 748 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, 749 adc->cfg->regs->or_vddcore.mask); 750 break; 751 case STM32_ADC_INT_CH_VDDCPU: 752 dev_dbg(&indio_dev->dev, "Enable VDDCPU\n"); 753 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, 754 adc->cfg->regs->or_vddcpu.mask); 755 break; 756 case STM32_ADC_INT_CH_VDDQ_DDR: 757 dev_dbg(&indio_dev->dev, "Enable VDDQ_DDR\n"); 758 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 759 adc->cfg->regs->or_vddq_ddr.mask); 760 break; 761 case STM32_ADC_INT_CH_VREFINT: 762 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); 763 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 764 adc->cfg->regs->ccr_vref.mask); 765 break; 766 case STM32_ADC_INT_CH_VBAT: 767 dev_dbg(&indio_dev->dev, "Enable VBAT\n"); 768 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 769 adc->cfg->regs->ccr_vbat.mask); 770 break; 771 } 772 } 773 } 774 775 static void stm32_adc_int_ch_disable(struct stm32_adc *adc) 776 { 777 u32 i; 778 779 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 780 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 781 continue; 782 783 switch (i) { 784 case STM32_ADC_INT_CH_VDDCORE: 785 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, 786 adc->cfg->regs->or_vddcore.mask); 787 break; 788 case STM32_ADC_INT_CH_VDDCPU: 789 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, 790 adc->cfg->regs->or_vddcpu.mask); 791 break; 792 case STM32_ADC_INT_CH_VDDQ_DDR: 793 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 794 adc->cfg->regs->or_vddq_ddr.mask); 795 break; 796 case STM32_ADC_INT_CH_VREFINT: 797 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 798 adc->cfg->regs->ccr_vref.mask); 799 break; 800 case STM32_ADC_INT_CH_VBAT: 801 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 802 adc->cfg->regs->ccr_vbat.mask); 803 break; 804 } 805 } 806 } 807 808 /** 809 * stm32f4_adc_start_conv() - Start conversions for regular channels. 810 * @indio_dev: IIO device instance 811 * @dma: use dma to transfer conversion result 812 * 813 * Start conversions for regular channels. 814 * Also take care of normal or DMA mode. Circular DMA may be used for regular 815 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 816 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 817 */ 818 static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) 819 { 820 struct stm32_adc *adc = iio_priv(indio_dev); 821 822 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 823 824 if (dma) 825 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 826 STM32F4_DMA | STM32F4_DDS); 827 828 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 829 830 /* Wait for Power-up time (tSTAB from datasheet) */ 831 usleep_range(2, 3); 832 833 /* Software start ? (e.g. trigger detection disabled ?) */ 834 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 835 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 836 } 837 838 static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) 839 { 840 struct stm32_adc *adc = iio_priv(indio_dev); 841 842 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 843 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 844 845 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 846 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 847 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 848 } 849 850 static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 851 { 852 struct stm32_adc *adc = iio_priv(indio_dev); 853 854 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 855 } 856 857 static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) 858 { 859 struct stm32_adc *adc = iio_priv(indio_dev); 860 enum stm32h7_adc_dmngt dmngt; 861 unsigned long flags; 862 u32 val; 863 864 if (dma) 865 dmngt = STM32H7_DMNGT_DMA_CIRC; 866 else 867 dmngt = STM32H7_DMNGT_DR_ONLY; 868 869 spin_lock_irqsave(&adc->lock, flags); 870 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 871 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 872 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 873 spin_unlock_irqrestore(&adc->lock, flags); 874 875 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 876 } 877 878 static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) 879 { 880 struct stm32_adc *adc = iio_priv(indio_dev); 881 int ret; 882 u32 val; 883 884 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 885 886 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 887 !(val & (STM32H7_ADSTART)), 888 100, STM32_ADC_TIMEOUT_US); 889 if (ret) 890 dev_warn(&indio_dev->dev, "stop failed\n"); 891 892 /* STM32H7_DMNGT_MASK covers STM32MP13_DMAEN & STM32MP13_DMACFG */ 893 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 894 } 895 896 static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 897 { 898 struct stm32_adc *adc = iio_priv(indio_dev); 899 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 900 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 901 } 902 903 static void stm32mp13_adc_start_conv(struct iio_dev *indio_dev, bool dma) 904 { 905 struct stm32_adc *adc = iio_priv(indio_dev); 906 907 if (dma) 908 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, 909 STM32MP13_DMAEN | STM32MP13_DMACFG); 910 911 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 912 } 913 914 static void stm32h7_adc_set_ovs(struct iio_dev *indio_dev, u32 ovs_idx) 915 { 916 struct stm32_adc *adc = iio_priv(indio_dev); 917 u32 ovsr_bits, bits, msk; 918 919 msk = STM32H7_ROVSE | STM32H7_OVSR_MASK | STM32H7_OVSS_MASK; 920 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); 921 922 if (!ovs_idx) 923 return; 924 925 /* 926 * Only the oversampling ratios corresponding to 2^ovs_idx are exposed in sysfs. 927 * Oversampling ratios [2,3,...,1024] are mapped on OVSR register values [1,2,...,1023]. 928 * OVSR = 2^ovs_idx - 1 929 * These ratio increase the resolution by ovs_idx bits. Apply a right shift to keep initial 930 * resolution given by "assigned-resolution-bits" property. 931 * OVSS = ovs_idx 932 */ 933 ovsr_bits = GENMASK(ovs_idx - 1, 0); 934 bits = STM32H7_ROVSE | STM32H7_OVSS(ovs_idx) | STM32H7_OVSR(ovsr_bits); 935 936 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); 937 } 938 939 static void stm32mp13_adc_set_ovs(struct iio_dev *indio_dev, u32 ovs_idx) 940 { 941 struct stm32_adc *adc = iio_priv(indio_dev); 942 u32 bits, msk; 943 944 msk = STM32H7_ROVSE | STM32MP13_OVSR_MASK | STM32MP13_OVSS_MASK; 945 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); 946 947 if (!ovs_idx) 948 return; 949 950 /* 951 * The oversampling ratios [2,4,8,..,256] are mapped on OVSR register values [0,1,...,7]. 952 * OVSR = ovs_idx - 1 953 * These ratio increase the resolution by ovs_idx bits. Apply a right shift to keep initial 954 * resolution given by "assigned-resolution-bits" property. 955 * OVSS = ovs_idx 956 */ 957 bits = STM32H7_ROVSE | STM32MP13_OVSS(ovs_idx); 958 if (ovs_idx - 1) 959 bits |= STM32MP13_OVSR(ovs_idx - 1); 960 961 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); 962 } 963 964 static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) 965 { 966 struct stm32_adc *adc = iio_priv(indio_dev); 967 int ret; 968 u32 val; 969 970 /* Exit deep power down, then enable ADC voltage regulator */ 971 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 972 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 973 974 if (adc->cfg->has_boostmode && 975 adc->common->rate > STM32H7_BOOST_CLKRATE) 976 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 977 978 /* Wait for startup time */ 979 if (!adc->cfg->has_vregready) { 980 usleep_range(10, 20); 981 return 0; 982 } 983 984 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 985 val & STM32MP1_VREGREADY, 100, 986 STM32_ADC_TIMEOUT_US); 987 if (ret) { 988 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 989 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 990 } 991 992 return ret; 993 } 994 995 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 996 { 997 if (adc->cfg->has_boostmode) 998 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 999 1000 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 1001 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 1002 } 1003 1004 static int stm32h7_adc_enable(struct iio_dev *indio_dev) 1005 { 1006 struct stm32_adc *adc = iio_priv(indio_dev); 1007 int ret; 1008 u32 val; 1009 1010 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 1011 1012 /* Poll for ADRDY to be set (after adc startup time) */ 1013 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 1014 val & STM32H7_ADRDY, 1015 100, STM32_ADC_TIMEOUT_US); 1016 if (ret) { 1017 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 1018 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 1019 } else { 1020 /* Clear ADRDY by writing one */ 1021 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 1022 } 1023 1024 return ret; 1025 } 1026 1027 static void stm32h7_adc_disable(struct iio_dev *indio_dev) 1028 { 1029 struct stm32_adc *adc = iio_priv(indio_dev); 1030 int ret; 1031 u32 val; 1032 1033 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) 1034 return; 1035 1036 /* Disable ADC and wait until it's effectively disabled */ 1037 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 1038 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1039 !(val & STM32H7_ADEN), 100, 1040 STM32_ADC_TIMEOUT_US); 1041 if (ret) 1042 dev_warn(&indio_dev->dev, "Failed to disable\n"); 1043 } 1044 1045 /** 1046 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 1047 * @indio_dev: IIO device instance 1048 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable 1049 */ 1050 static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) 1051 { 1052 struct stm32_adc *adc = iio_priv(indio_dev); 1053 int i, ret; 1054 u32 lincalrdyw_mask, val; 1055 1056 /* Read linearity calibration */ 1057 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1058 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 1059 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 1060 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1061 1062 /* Poll: wait calib data to be ready in CALFACT2 register */ 1063 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1064 !(val & lincalrdyw_mask), 1065 100, STM32_ADC_TIMEOUT_US); 1066 if (ret) { 1067 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 1068 return ret; 1069 } 1070 1071 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 1072 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 1073 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 1074 1075 lincalrdyw_mask >>= 1; 1076 } 1077 adc->cal.lincal_saved = true; 1078 1079 return 0; 1080 } 1081 1082 /** 1083 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 1084 * @indio_dev: IIO device instance 1085 * Note: ADC must be enabled, with no on-going conversions. 1086 */ 1087 static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) 1088 { 1089 struct stm32_adc *adc = iio_priv(indio_dev); 1090 int i, ret; 1091 u32 lincalrdyw_mask, val; 1092 1093 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1094 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 1095 /* 1096 * Write saved calibration data to shadow registers: 1097 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 1098 * data write. Then poll to wait for complete transfer. 1099 */ 1100 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 1101 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 1102 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1103 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1104 val & lincalrdyw_mask, 1105 100, STM32_ADC_TIMEOUT_US); 1106 if (ret) { 1107 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 1108 return ret; 1109 } 1110 1111 /* 1112 * Read back calibration data, has two effects: 1113 * - It ensures bits LINCALRDYW[6..1] are kept cleared 1114 * for next time calibration needs to be restored. 1115 * - BTW, bit clear triggers a read, then check data has been 1116 * correctly written. 1117 */ 1118 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1119 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1120 !(val & lincalrdyw_mask), 1121 100, STM32_ADC_TIMEOUT_US); 1122 if (ret) { 1123 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 1124 return ret; 1125 } 1126 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 1127 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 1128 dev_err(&indio_dev->dev, "calfact not consistent\n"); 1129 return -EIO; 1130 } 1131 1132 lincalrdyw_mask >>= 1; 1133 } 1134 1135 return 0; 1136 } 1137 1138 /* 1139 * Fixed timeout value for ADC calibration. 1140 * worst cases: 1141 * - low clock frequency 1142 * - maximum prescalers 1143 * Calibration requires: 1144 * - 131,072 ADC clock cycle for the linear calibration 1145 * - 20 ADC clock cycle for the offset calibration 1146 * 1147 * Set to 100ms for now 1148 */ 1149 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000 1150 1151 /** 1152 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC 1153 * @indio_dev: IIO device instance 1154 * @do_lincal: linear calibration request flag 1155 * Note: Must be called once ADC is out of power down. 1156 * 1157 * Run offset calibration unconditionally. 1158 * Run linear calibration if requested & supported. 1159 */ 1160 static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev, int do_lincal) 1161 { 1162 struct stm32_adc *adc = iio_priv(indio_dev); 1163 int ret; 1164 u32 msk = STM32H7_ADCALDIF; 1165 u32 val; 1166 1167 if (adc->cfg->has_linearcal && do_lincal) 1168 msk |= STM32H7_ADCALLIN; 1169 /* ADC must be disabled for calibration */ 1170 stm32h7_adc_disable(indio_dev); 1171 1172 /* 1173 * Select calibration mode: 1174 * - Offset calibration for single ended inputs 1175 * - No linearity calibration (do it later, before reading it) 1176 */ 1177 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1178 1179 /* Start calibration, then wait for completion */ 1180 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1181 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1182 !(val & STM32H7_ADCAL), 100, 1183 STM32H7_ADC_CALIB_TIMEOUT_US); 1184 if (ret) { 1185 dev_err(&indio_dev->dev, "calibration (single-ended) error %d\n", ret); 1186 goto out; 1187 } 1188 1189 /* 1190 * Select calibration mode, then start calibration: 1191 * - Offset calibration for differential input 1192 * - Linearity calibration (needs to be done only once for single/diff) 1193 * will run simultaneously with offset calibration. 1194 */ 1195 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); 1196 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1197 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1198 !(val & STM32H7_ADCAL), 100, 1199 STM32H7_ADC_CALIB_TIMEOUT_US); 1200 if (ret) { 1201 dev_err(&indio_dev->dev, "calibration (diff%s) error %d\n", 1202 (msk & STM32H7_ADCALLIN) ? "+linear" : "", ret); 1203 goto out; 1204 } 1205 1206 out: 1207 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1208 1209 return ret; 1210 } 1211 1212 /** 1213 * stm32h7_adc_check_selfcalib() - Check linear calibration status 1214 * @indio_dev: IIO device instance 1215 * 1216 * Used to check if linear calibration has been done. 1217 * Return true if linear calibration factors are already saved in private data 1218 * or if a linear calibration has been done at boot stage. 1219 */ 1220 static int stm32h7_adc_check_selfcalib(struct iio_dev *indio_dev) 1221 { 1222 struct stm32_adc *adc = iio_priv(indio_dev); 1223 u32 val; 1224 1225 if (adc->cal.lincal_saved) 1226 return true; 1227 1228 /* 1229 * Check if linear calibration factors are available in ADC registers, 1230 * by checking that all LINCALRDYWx bits are set. 1231 */ 1232 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK; 1233 if (val == STM32H7_LINCALRDYW_MASK) 1234 return true; 1235 1236 return false; 1237 } 1238 1239 /** 1240 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 1241 * @indio_dev: IIO device instance 1242 * Leave power down mode. 1243 * Configure channels as single ended or differential before enabling ADC. 1244 * Enable ADC. 1245 * Restore calibration data. 1246 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 1247 * - Only one input is selected for single ended (e.g. 'vinp') 1248 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 1249 */ 1250 static int stm32h7_adc_prepare(struct iio_dev *indio_dev) 1251 { 1252 struct stm32_adc *adc = iio_priv(indio_dev); 1253 int lincal_done = false; 1254 int ret; 1255 1256 ret = stm32h7_adc_exit_pwr_down(indio_dev); 1257 if (ret) 1258 return ret; 1259 1260 if (adc->cfg->has_linearcal) 1261 lincal_done = stm32h7_adc_check_selfcalib(indio_dev); 1262 1263 /* Always run offset calibration. Run linear calibration only once */ 1264 ret = stm32h7_adc_selfcalib(indio_dev, !lincal_done); 1265 if (ret < 0) 1266 goto pwr_dwn; 1267 1268 stm32_adc_int_ch_enable(indio_dev); 1269 1270 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); 1271 1272 ret = stm32h7_adc_enable(indio_dev); 1273 if (ret) 1274 goto ch_disable; 1275 1276 if (adc->cfg->has_linearcal) { 1277 if (!adc->cal.lincal_saved) 1278 ret = stm32h7_adc_read_selfcalib(indio_dev); 1279 else 1280 ret = stm32h7_adc_restore_selfcalib(indio_dev); 1281 1282 if (ret) 1283 goto disable; 1284 } 1285 1286 if (adc->cfg->has_presel) 1287 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1288 1289 return 0; 1290 1291 disable: 1292 stm32h7_adc_disable(indio_dev); 1293 ch_disable: 1294 stm32_adc_int_ch_disable(adc); 1295 pwr_dwn: 1296 stm32h7_adc_enter_pwr_down(adc); 1297 1298 return ret; 1299 } 1300 1301 static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) 1302 { 1303 struct stm32_adc *adc = iio_priv(indio_dev); 1304 1305 if (adc->cfg->has_presel) 1306 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1307 stm32h7_adc_disable(indio_dev); 1308 stm32_adc_int_ch_disable(adc); 1309 stm32h7_adc_enter_pwr_down(adc); 1310 } 1311 1312 /** 1313 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 1314 * @indio_dev: IIO device 1315 * @scan_mask: channels to be converted 1316 * 1317 * Conversion sequence : 1318 * Apply sampling time settings for all channels. 1319 * Configure ADC scan sequence based on selected channels in scan_mask. 1320 * Add channels to SQR registers, from scan_mask LSB to MSB, then 1321 * program sequence len. 1322 */ 1323 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 1324 const unsigned long *scan_mask) 1325 { 1326 struct stm32_adc *adc = iio_priv(indio_dev); 1327 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1328 const struct iio_chan_spec *chan; 1329 u32 val, bit; 1330 int i = 0; 1331 1332 /* Apply sampling time settings */ 1333 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1334 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1335 1336 for_each_set_bit(bit, scan_mask, iio_get_masklength(indio_dev)) { 1337 chan = indio_dev->channels + bit; 1338 /* 1339 * Assign one channel per SQ entry in regular 1340 * sequence, starting with SQ1. 1341 */ 1342 i++; 1343 if (i > STM32_ADC_MAX_SQ) 1344 return -EINVAL; 1345 1346 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1347 __func__, chan->channel, i); 1348 1349 val = stm32_adc_readl(adc, sqr[i].reg); 1350 val &= ~sqr[i].mask; 1351 val |= chan->channel << sqr[i].shift; 1352 stm32_adc_writel(adc, sqr[i].reg, val); 1353 } 1354 1355 if (!i) 1356 return -EINVAL; 1357 1358 /* Sequence len */ 1359 val = stm32_adc_readl(adc, sqr[0].reg); 1360 val &= ~sqr[0].mask; 1361 val |= ((i - 1) << sqr[0].shift); 1362 stm32_adc_writel(adc, sqr[0].reg, val); 1363 1364 return 0; 1365 } 1366 1367 /** 1368 * stm32_adc_get_trig_extsel() - Get external trigger selection 1369 * @indio_dev: IIO device structure 1370 * @trig: trigger 1371 * 1372 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1373 */ 1374 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1375 struct iio_trigger *trig) 1376 { 1377 struct stm32_adc *adc = iio_priv(indio_dev); 1378 int i; 1379 1380 /* lookup triggers registered by stm32 timer trigger driver */ 1381 for (i = 0; adc->cfg->trigs[i].name; i++) { 1382 /** 1383 * Checking both stm32 timer trigger type and trig name 1384 * should be safe against arbitrary trigger names. 1385 */ 1386 if ((is_stm32_timer_trigger(trig) || 1387 is_stm32_lptim_trigger(trig)) && 1388 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1389 return adc->cfg->trigs[i].extsel; 1390 } 1391 } 1392 1393 return -EINVAL; 1394 } 1395 1396 /** 1397 * stm32_adc_set_trig() - Set a regular trigger 1398 * @indio_dev: IIO device 1399 * @trig: IIO trigger 1400 * 1401 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1402 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1403 * - if HW trigger enabled, set source & polarity 1404 */ 1405 static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1406 struct iio_trigger *trig) 1407 { 1408 struct stm32_adc *adc = iio_priv(indio_dev); 1409 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1410 unsigned long flags; 1411 int ret; 1412 1413 if (trig) { 1414 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1415 if (ret < 0) 1416 return ret; 1417 1418 /* set trigger source and polarity (default to rising edge) */ 1419 extsel = ret; 1420 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1421 } 1422 1423 spin_lock_irqsave(&adc->lock, flags); 1424 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1425 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1426 val |= exten << adc->cfg->regs->exten.shift; 1427 val |= extsel << adc->cfg->regs->extsel.shift; 1428 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1429 spin_unlock_irqrestore(&adc->lock, flags); 1430 1431 return 0; 1432 } 1433 1434 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1435 const struct iio_chan_spec *chan, 1436 unsigned int type) 1437 { 1438 struct stm32_adc *adc = iio_priv(indio_dev); 1439 1440 adc->trigger_polarity = type; 1441 1442 return 0; 1443 } 1444 1445 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1446 const struct iio_chan_spec *chan) 1447 { 1448 struct stm32_adc *adc = iio_priv(indio_dev); 1449 1450 return adc->trigger_polarity; 1451 } 1452 1453 static const char * const stm32_trig_pol_items[] = { 1454 "rising-edge", "falling-edge", "both-edges", 1455 }; 1456 1457 static const struct iio_enum stm32_adc_trig_pol = { 1458 .items = stm32_trig_pol_items, 1459 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1460 .get = stm32_adc_get_trig_pol, 1461 .set = stm32_adc_set_trig_pol, 1462 }; 1463 1464 /** 1465 * stm32_adc_single_conv() - Performs a single conversion 1466 * @indio_dev: IIO device 1467 * @chan: IIO channel 1468 * @res: conversion result 1469 * 1470 * The function performs a single conversion on a given channel: 1471 * - Apply sampling time settings 1472 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1473 * - Use SW trigger 1474 * - Start conversion, then wait for interrupt completion. 1475 */ 1476 static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1477 const struct iio_chan_spec *chan, 1478 int *res) 1479 { 1480 struct stm32_adc *adc = iio_priv(indio_dev); 1481 struct device *dev = indio_dev->dev.parent; 1482 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1483 long time_left; 1484 u32 val; 1485 int ret; 1486 1487 reinit_completion(&adc->completion); 1488 1489 adc->bufi = 0; 1490 1491 ret = pm_runtime_resume_and_get(dev); 1492 if (ret < 0) 1493 return ret; 1494 1495 /* Apply sampling time settings */ 1496 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1497 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1498 1499 /* Program chan number in regular sequence (SQ1) */ 1500 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1501 val &= ~regs->sqr[1].mask; 1502 val |= chan->channel << regs->sqr[1].shift; 1503 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1504 1505 /* Set regular sequence len (0 for 1 conversion) */ 1506 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1507 1508 /* Trigger detection disabled (conversion can be launched in SW) */ 1509 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1510 1511 stm32_adc_conv_irq_enable(adc); 1512 1513 adc->cfg->start_conv(indio_dev, false); 1514 1515 time_left = wait_for_completion_interruptible_timeout( 1516 &adc->completion, STM32_ADC_TIMEOUT); 1517 if (time_left == 0) { 1518 ret = -ETIMEDOUT; 1519 } else if (time_left < 0) { 1520 ret = time_left; 1521 } else { 1522 *res = adc->buffer[0]; 1523 ret = IIO_VAL_INT; 1524 } 1525 1526 adc->cfg->stop_conv(indio_dev); 1527 1528 stm32_adc_conv_irq_disable(adc); 1529 1530 pm_runtime_put_autosuspend(dev); 1531 1532 return ret; 1533 } 1534 1535 static int stm32_adc_write_raw(struct iio_dev *indio_dev, 1536 struct iio_chan_spec const *chan, 1537 int val, int val2, long mask) 1538 { 1539 struct stm32_adc *adc = iio_priv(indio_dev); 1540 struct device *dev = indio_dev->dev.parent; 1541 int nb = adc->cfg->adc_info->num_ovs; 1542 unsigned int idx; 1543 int ret; 1544 1545 switch (mask) { 1546 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1547 if (val2) 1548 return -EINVAL; 1549 1550 for (idx = 0; idx < nb; idx++) 1551 if (adc->cfg->adc_info->oversampling[idx] == val) 1552 break; 1553 if (idx >= nb) 1554 return -EINVAL; 1555 1556 if (!iio_device_claim_direct(indio_dev)) 1557 return -EBUSY; 1558 1559 ret = pm_runtime_resume_and_get(dev); 1560 if (ret < 0) 1561 goto err; 1562 1563 adc->cfg->set_ovs(indio_dev, idx); 1564 1565 pm_runtime_put_autosuspend(dev); 1566 1567 adc->ovs_idx = idx; 1568 1569 err: 1570 iio_device_release_direct(indio_dev); 1571 1572 return ret; 1573 default: 1574 return -EINVAL; 1575 } 1576 } 1577 1578 static int stm32_adc_read_avail(struct iio_dev *indio_dev, 1579 struct iio_chan_spec const *chan, 1580 const int **vals, int *type, int *length, long m) 1581 { 1582 struct stm32_adc *adc = iio_priv(indio_dev); 1583 1584 switch (m) { 1585 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1586 *type = IIO_VAL_INT; 1587 *length = adc->cfg->adc_info->num_ovs; 1588 *vals = adc->cfg->adc_info->oversampling; 1589 return IIO_AVAIL_LIST; 1590 default: 1591 return -EINVAL; 1592 } 1593 } 1594 1595 static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1596 struct iio_chan_spec const *chan, 1597 int *val, int *val2, long mask) 1598 { 1599 struct stm32_adc *adc = iio_priv(indio_dev); 1600 int ret; 1601 1602 switch (mask) { 1603 case IIO_CHAN_INFO_RAW: 1604 case IIO_CHAN_INFO_PROCESSED: 1605 if (!iio_device_claim_direct(indio_dev)) 1606 return -EBUSY; 1607 if (chan->type == IIO_VOLTAGE) 1608 ret = stm32_adc_single_conv(indio_dev, chan, val); 1609 else 1610 ret = -EINVAL; 1611 iio_device_release_direct(indio_dev); 1612 if (ret < 0) 1613 return ret; 1614 1615 if (mask == IIO_CHAN_INFO_PROCESSED) { 1616 if (*val == 0) 1617 return -EINVAL; 1618 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; 1619 } 1620 1621 return ret; 1622 1623 case IIO_CHAN_INFO_SCALE: 1624 if (chan->differential) { 1625 *val = adc->common->vref_mv * 2; 1626 *val2 = chan->scan_type.realbits; 1627 } else { 1628 *val = adc->common->vref_mv; 1629 *val2 = chan->scan_type.realbits; 1630 } 1631 return IIO_VAL_FRACTIONAL_LOG2; 1632 1633 case IIO_CHAN_INFO_OFFSET: 1634 if (chan->differential) 1635 /* ADC_full_scale / 2 */ 1636 *val = -((1 << chan->scan_type.realbits) / 2); 1637 else 1638 *val = 0; 1639 return IIO_VAL_INT; 1640 1641 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1642 *val = adc->cfg->adc_info->oversampling[adc->ovs_idx]; 1643 return IIO_VAL_INT; 1644 1645 default: 1646 return -EINVAL; 1647 } 1648 } 1649 1650 static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 1651 { 1652 struct stm32_adc *adc = iio_priv(indio_dev); 1653 1654 adc->cfg->irq_clear(indio_dev, msk); 1655 } 1656 1657 static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) 1658 { 1659 struct iio_dev *indio_dev = data; 1660 struct stm32_adc *adc = iio_priv(indio_dev); 1661 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1662 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1663 1664 /* Check ovr status right now, as ovr mask should be already disabled */ 1665 if (status & regs->isr_ovr.mask) { 1666 /* 1667 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1668 * This requires to stop ADC first. OVR bit state in ISR, 1669 * is propagated to CSR register by hardware. 1670 */ 1671 adc->cfg->stop_conv(indio_dev); 1672 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); 1673 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); 1674 return IRQ_HANDLED; 1675 } 1676 1677 return IRQ_NONE; 1678 } 1679 1680 static irqreturn_t stm32_adc_isr(int irq, void *data) 1681 { 1682 struct iio_dev *indio_dev = data; 1683 struct stm32_adc *adc = iio_priv(indio_dev); 1684 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1685 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1686 1687 if (status & regs->isr_ovr.mask) { 1688 /* 1689 * Overrun occurred on regular conversions: data for wrong 1690 * channel may be read. Unconditionally disable interrupts 1691 * to stop processing data and print error message. 1692 * Restarting the capture can be done by disabling, then 1693 * re-enabling it (e.g. write 0, then 1 to buffer/enable). 1694 */ 1695 stm32_adc_ovr_irq_disable(adc); 1696 stm32_adc_conv_irq_disable(adc); 1697 return IRQ_WAKE_THREAD; 1698 } 1699 1700 if (status & regs->isr_eoc.mask) { 1701 /* Reading DR also clears EOC status flag */ 1702 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1703 if (iio_buffer_enabled(indio_dev)) { 1704 adc->bufi++; 1705 if (adc->bufi >= adc->num_conv) { 1706 stm32_adc_conv_irq_disable(adc); 1707 iio_trigger_poll(indio_dev->trig); 1708 } 1709 } else { 1710 complete(&adc->completion); 1711 } 1712 return IRQ_HANDLED; 1713 } 1714 1715 return IRQ_NONE; 1716 } 1717 1718 /** 1719 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1720 * @indio_dev: IIO device 1721 * @trig: new trigger 1722 * 1723 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1724 * driver, -EINVAL otherwise. 1725 */ 1726 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1727 struct iio_trigger *trig) 1728 { 1729 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1730 } 1731 1732 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1733 { 1734 struct stm32_adc *adc = iio_priv(indio_dev); 1735 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1736 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1737 1738 /* 1739 * dma cyclic transfers are used, buffer is split into two periods. 1740 * There should be : 1741 * - always one buffer (period) dma is working on 1742 * - one buffer (period) driver can push data. 1743 */ 1744 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1745 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1746 1747 return 0; 1748 } 1749 1750 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1751 const unsigned long *scan_mask) 1752 { 1753 struct stm32_adc *adc = iio_priv(indio_dev); 1754 struct device *dev = indio_dev->dev.parent; 1755 int ret; 1756 1757 ret = pm_runtime_resume_and_get(dev); 1758 if (ret < 0) 1759 return ret; 1760 1761 adc->num_conv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev)); 1762 1763 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1764 pm_runtime_put_autosuspend(dev); 1765 1766 return ret; 1767 } 1768 1769 static int stm32_adc_fwnode_xlate(struct iio_dev *indio_dev, 1770 const struct fwnode_reference_args *iiospec) 1771 { 1772 int i; 1773 1774 for (i = 0; i < indio_dev->num_channels; i++) 1775 if (indio_dev->channels[i].channel == iiospec->args[0]) 1776 return i; 1777 1778 return -EINVAL; 1779 } 1780 1781 /** 1782 * stm32_adc_debugfs_reg_access - read or write register value 1783 * @indio_dev: IIO device structure 1784 * @reg: register offset 1785 * @writeval: value to write 1786 * @readval: value to read 1787 * 1788 * To read a value from an ADC register: 1789 * echo [ADC reg offset] > direct_reg_access 1790 * cat direct_reg_access 1791 * 1792 * To write a value in a ADC register: 1793 * echo [ADC_reg_offset] [value] > direct_reg_access 1794 */ 1795 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1796 unsigned reg, unsigned writeval, 1797 unsigned *readval) 1798 { 1799 struct stm32_adc *adc = iio_priv(indio_dev); 1800 struct device *dev = indio_dev->dev.parent; 1801 int ret; 1802 1803 ret = pm_runtime_resume_and_get(dev); 1804 if (ret < 0) 1805 return ret; 1806 1807 if (!readval) 1808 stm32_adc_writel(adc, reg, writeval); 1809 else 1810 *readval = stm32_adc_readl(adc, reg); 1811 1812 pm_runtime_put_autosuspend(dev); 1813 1814 return 0; 1815 } 1816 1817 static const struct iio_info stm32_adc_iio_info = { 1818 .read_raw = stm32_adc_read_raw, 1819 .write_raw = stm32_adc_write_raw, 1820 .read_avail = stm32_adc_read_avail, 1821 .validate_trigger = stm32_adc_validate_trigger, 1822 .hwfifo_set_watermark = stm32_adc_set_watermark, 1823 .update_scan_mode = stm32_adc_update_scan_mode, 1824 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1825 .fwnode_xlate = stm32_adc_fwnode_xlate, 1826 }; 1827 1828 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1829 { 1830 struct dma_tx_state state; 1831 enum dma_status status; 1832 1833 status = dmaengine_tx_status(adc->dma_chan, 1834 adc->dma_chan->cookie, 1835 &state); 1836 if (status == DMA_IN_PROGRESS) { 1837 /* Residue is size in bytes from end of buffer */ 1838 unsigned int i = adc->rx_buf_sz - state.residue; 1839 unsigned int size; 1840 1841 /* Return available bytes */ 1842 if (i >= adc->bufi) 1843 size = i - adc->bufi; 1844 else 1845 size = adc->rx_buf_sz + i - adc->bufi; 1846 1847 return size; 1848 } 1849 1850 return 0; 1851 } 1852 1853 static void stm32_adc_dma_buffer_done(void *data) 1854 { 1855 struct iio_dev *indio_dev = data; 1856 struct stm32_adc *adc = iio_priv(indio_dev); 1857 int residue = stm32_adc_dma_residue(adc); 1858 1859 /* 1860 * In DMA mode the trigger services of IIO are not used 1861 * (e.g. no call to iio_trigger_poll). 1862 * Calling irq handler associated to the hardware trigger is not 1863 * relevant as the conversions have already been done. Data 1864 * transfers are performed directly in DMA callback instead. 1865 * This implementation avoids to call trigger irq handler that 1866 * may sleep, in an atomic context (DMA irq handler context). 1867 */ 1868 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1869 1870 while (residue >= indio_dev->scan_bytes) { 1871 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1872 1873 iio_push_to_buffers(indio_dev, buffer); 1874 1875 residue -= indio_dev->scan_bytes; 1876 adc->bufi += indio_dev->scan_bytes; 1877 if (adc->bufi >= adc->rx_buf_sz) 1878 adc->bufi = 0; 1879 } 1880 } 1881 1882 static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1883 { 1884 struct stm32_adc *adc = iio_priv(indio_dev); 1885 struct dma_async_tx_descriptor *desc; 1886 dma_cookie_t cookie; 1887 int ret; 1888 1889 if (!adc->dma_chan) 1890 return 0; 1891 1892 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1893 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1894 1895 /* Prepare a DMA cyclic transaction */ 1896 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1897 adc->rx_dma_buf, 1898 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1899 DMA_DEV_TO_MEM, 1900 DMA_PREP_INTERRUPT); 1901 if (!desc) 1902 return -EBUSY; 1903 1904 desc->callback = stm32_adc_dma_buffer_done; 1905 desc->callback_param = indio_dev; 1906 1907 cookie = dmaengine_submit(desc); 1908 ret = dma_submit_error(cookie); 1909 if (ret) { 1910 dmaengine_terminate_sync(adc->dma_chan); 1911 return ret; 1912 } 1913 1914 /* Issue pending DMA requests */ 1915 dma_async_issue_pending(adc->dma_chan); 1916 1917 return 0; 1918 } 1919 1920 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1921 { 1922 struct stm32_adc *adc = iio_priv(indio_dev); 1923 struct device *dev = indio_dev->dev.parent; 1924 int ret; 1925 1926 ret = pm_runtime_resume_and_get(dev); 1927 if (ret < 0) 1928 return ret; 1929 1930 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1931 if (ret) { 1932 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1933 goto err_pm_put; 1934 } 1935 1936 ret = stm32_adc_dma_start(indio_dev); 1937 if (ret) { 1938 dev_err(&indio_dev->dev, "Can't start dma\n"); 1939 goto err_clr_trig; 1940 } 1941 1942 /* Reset adc buffer index */ 1943 adc->bufi = 0; 1944 1945 stm32_adc_ovr_irq_enable(adc); 1946 1947 if (!adc->dma_chan) 1948 stm32_adc_conv_irq_enable(adc); 1949 1950 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); 1951 1952 return 0; 1953 1954 err_clr_trig: 1955 stm32_adc_set_trig(indio_dev, NULL); 1956 err_pm_put: 1957 pm_runtime_put_autosuspend(dev); 1958 1959 return ret; 1960 } 1961 1962 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1963 { 1964 struct stm32_adc *adc = iio_priv(indio_dev); 1965 struct device *dev = indio_dev->dev.parent; 1966 1967 adc->cfg->stop_conv(indio_dev); 1968 if (!adc->dma_chan) 1969 stm32_adc_conv_irq_disable(adc); 1970 1971 stm32_adc_ovr_irq_disable(adc); 1972 1973 if (adc->dma_chan) 1974 dmaengine_terminate_sync(adc->dma_chan); 1975 1976 if (stm32_adc_set_trig(indio_dev, NULL)) 1977 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1978 1979 pm_runtime_put_autosuspend(dev); 1980 1981 return 0; 1982 } 1983 1984 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1985 .postenable = &stm32_adc_buffer_postenable, 1986 .predisable = &stm32_adc_buffer_predisable, 1987 }; 1988 1989 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1990 { 1991 struct iio_poll_func *pf = p; 1992 struct iio_dev *indio_dev = pf->indio_dev; 1993 struct stm32_adc *adc = iio_priv(indio_dev); 1994 1995 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1996 1997 /* reset buffer index */ 1998 adc->bufi = 0; 1999 iio_push_to_buffers_with_ts(indio_dev, adc->buffer, sizeof(adc->buffer), 2000 pf->timestamp); 2001 iio_trigger_notify_done(indio_dev->trig); 2002 2003 /* re-enable eoc irq */ 2004 stm32_adc_conv_irq_enable(adc); 2005 2006 return IRQ_HANDLED; 2007 } 2008 2009 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 2010 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 2011 { 2012 .name = "trigger_polarity_available", 2013 .shared = IIO_SHARED_BY_ALL, 2014 .read = iio_enum_available_read, 2015 .private = (uintptr_t)&stm32_adc_trig_pol, 2016 }, 2017 { } 2018 }; 2019 2020 static void stm32_adc_debugfs_init(struct iio_dev *indio_dev) 2021 { 2022 struct stm32_adc *adc = iio_priv(indio_dev); 2023 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 2024 struct stm32_adc_calib *cal = &adc->cal; 2025 char buf[16]; 2026 unsigned int i; 2027 2028 if (!adc->cfg->has_linearcal) 2029 return; 2030 2031 for (i = 0; i < STM32H7_LINCALFACT_NUM; i++) { 2032 snprintf(buf, sizeof(buf), "lincalfact%d", i + 1); 2033 debugfs_create_u32(buf, 0444, d, &cal->lincalfact[i]); 2034 } 2035 } 2036 2037 static int stm32_adc_fw_get_resolution(struct iio_dev *indio_dev) 2038 { 2039 struct device *dev = &indio_dev->dev; 2040 struct stm32_adc *adc = iio_priv(indio_dev); 2041 unsigned int i; 2042 u32 res; 2043 2044 if (device_property_read_u32(dev, "assigned-resolution-bits", &res)) 2045 res = adc->cfg->adc_info->resolutions[0]; 2046 2047 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 2048 if (res == adc->cfg->adc_info->resolutions[i]) 2049 break; 2050 if (i >= adc->cfg->adc_info->num_res) { 2051 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 2052 return -EINVAL; 2053 } 2054 2055 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 2056 adc->res = i; 2057 2058 return 0; 2059 } 2060 2061 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 2062 { 2063 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 2064 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 2065 unsigned int i, smp, r = smpr->reg; 2066 2067 /* 2068 * For internal channels, ensure that the sampling time cannot 2069 * be lower than the one specified in the datasheet 2070 */ 2071 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2072 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE) 2073 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]); 2074 2075 /* Determine sampling time (ADC clock cycles) */ 2076 period_ns = NSEC_PER_SEC / adc->common->rate; 2077 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 2078 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 2079 break; 2080 if (smp > STM32_ADC_MAX_SMP) 2081 smp = STM32_ADC_MAX_SMP; 2082 2083 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 2084 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 2085 } 2086 2087 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 2088 struct iio_chan_spec *chan, u32 vinp, 2089 u32 vinn, int scan_index, bool differential) 2090 { 2091 struct stm32_adc *adc = iio_priv(indio_dev); 2092 char *name = adc->chan_name[vinp]; 2093 2094 chan->type = IIO_VOLTAGE; 2095 chan->channel = vinp; 2096 if (differential) { 2097 chan->differential = 1; 2098 chan->channel2 = vinn; 2099 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 2100 } else { 2101 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 2102 } 2103 chan->datasheet_name = name; 2104 chan->scan_index = scan_index; 2105 chan->indexed = 1; 2106 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 2107 chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); 2108 else 2109 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 2110 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 2111 BIT(IIO_CHAN_INFO_OFFSET); 2112 if (adc->cfg->has_oversampling) { 2113 chan->info_mask_shared_by_all |= BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 2114 chan->info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 2115 } 2116 chan->scan_type.sign = 'u'; 2117 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 2118 chan->scan_type.storagebits = 16; 2119 chan->ext_info = stm32_adc_ext_info; 2120 2121 /* pre-build selected channels mask */ 2122 adc->pcsel |= BIT(chan->channel); 2123 if (differential) { 2124 /* pre-build diff channels mask */ 2125 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; 2126 /* Also add negative input to pre-selected channels */ 2127 adc->pcsel |= BIT(chan->channel2); 2128 } 2129 } 2130 2131 static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) 2132 { 2133 struct device *dev = &indio_dev->dev; 2134 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2135 int num_channels = 0, ret; 2136 2137 dev_dbg(&indio_dev->dev, "using legacy channel config\n"); 2138 2139 ret = device_property_count_u32(dev, "st,adc-channels"); 2140 if (ret > adc_info->max_channels) { 2141 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 2142 return -EINVAL; 2143 } else if (ret > 0) { 2144 num_channels += ret; 2145 } 2146 2147 /* 2148 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret 2149 * to get the *real* number of channels. 2150 */ 2151 ret = device_property_count_u32(dev, "st,adc-diff-channels"); 2152 if (ret > 0) { 2153 ret /= (int)(sizeof(struct stm32_adc_diff_channel) / sizeof(u32)); 2154 if (ret > adc_info->max_channels) { 2155 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 2156 return -EINVAL; 2157 } else if (ret > 0) { 2158 adc->num_diff = ret; 2159 num_channels += ret; 2160 } 2161 } 2162 2163 /* Optional sample time is provided either for each, or all channels */ 2164 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); 2165 if (adc->nsmps > 1 && adc->nsmps != num_channels) { 2166 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 2167 return -EINVAL; 2168 } 2169 2170 return num_channels; 2171 } 2172 2173 static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, 2174 struct stm32_adc *adc, 2175 struct iio_chan_spec *channels, 2176 int nchans) 2177 { 2178 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2179 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 2180 struct device *dev = &indio_dev->dev; 2181 u32 num_diff = adc->num_diff; 2182 int num_se = nchans - num_diff; 2183 int size = num_diff * sizeof(*diff) / sizeof(u32); 2184 int scan_index = 0, ret, i, c; 2185 u32 smp = 0, smps[STM32_ADC_CH_MAX], chans[STM32_ADC_CH_MAX]; 2186 2187 if (num_diff) { 2188 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", 2189 (u32 *)diff, size); 2190 if (ret) { 2191 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); 2192 return ret; 2193 } 2194 2195 for (i = 0; i < num_diff; i++) { 2196 if (diff[i].vinp >= adc_info->max_channels || 2197 diff[i].vinn >= adc_info->max_channels) { 2198 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 2199 diff[i].vinp, diff[i].vinn); 2200 return -EINVAL; 2201 } 2202 2203 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 2204 diff[i].vinp, diff[i].vinn, 2205 scan_index, true); 2206 scan_index++; 2207 } 2208 } 2209 if (num_se > 0) { 2210 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); 2211 if (ret) { 2212 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret); 2213 return ret; 2214 } 2215 2216 for (c = 0; c < num_se; c++) { 2217 if (chans[c] >= adc_info->max_channels) { 2218 dev_err(&indio_dev->dev, "Invalid channel %d\n", 2219 chans[c]); 2220 return -EINVAL; 2221 } 2222 2223 /* Channel can't be configured both as single-ended & diff */ 2224 for (i = 0; i < num_diff; i++) { 2225 if (chans[c] == diff[i].vinp) { 2226 dev_err(&indio_dev->dev, "channel %d misconfigured\n", 2227 chans[c]); 2228 return -EINVAL; 2229 } 2230 } 2231 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 2232 chans[c], 0, scan_index, false); 2233 scan_index++; 2234 } 2235 } 2236 2237 if (adc->nsmps > 0) { 2238 ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs", 2239 smps, adc->nsmps); 2240 if (ret) 2241 return ret; 2242 } 2243 2244 for (i = 0; i < scan_index; i++) { 2245 /* 2246 * This check is used with the above logic so that smp value 2247 * will only be modified if valid u32 value can be decoded. This 2248 * allows to get either no value, 1 shared value for all indexes, 2249 * or one value per channel. The point is to have the same 2250 * behavior as 'of_property_read_u32_index()'. 2251 */ 2252 if (i < adc->nsmps) 2253 smp = smps[i]; 2254 2255 /* Prepare sampling time settings */ 2256 stm32_adc_smpr_init(adc, channels[i].channel, smp); 2257 } 2258 2259 return scan_index; 2260 } 2261 2262 static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, 2263 int chan) 2264 { 2265 struct stm32_adc *adc = iio_priv(indio_dev); 2266 u16 vrefint; 2267 int i, ret; 2268 2269 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 2270 if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { 2271 bool na; 2272 2273 /* Check internal channel availability */ 2274 switch (i) { 2275 case STM32_ADC_INT_CH_VDDCORE: 2276 na = !adc->cfg->regs->or_vddcore.reg; 2277 break; 2278 case STM32_ADC_INT_CH_VDDCPU: 2279 na = !adc->cfg->regs->or_vddcpu.reg; 2280 break; 2281 case STM32_ADC_INT_CH_VDDQ_DDR: 2282 na = !adc->cfg->regs->or_vddq_ddr.reg; 2283 break; 2284 case STM32_ADC_INT_CH_VREFINT: 2285 na = !adc->cfg->regs->ccr_vref.reg; 2286 break; 2287 case STM32_ADC_INT_CH_VBAT: 2288 na = !adc->cfg->regs->ccr_vbat.reg; 2289 break; 2290 default: 2291 return -EINVAL; 2292 } 2293 2294 if (na) { 2295 /* 2296 * Channel label matches an internal STM32 ADC channel. 2297 * Warn about it, as there's normally no restriction on the 2298 * name but that's not among available internal channels. 2299 */ 2300 dev_warn(&indio_dev->dev, "no %s internal channel\n", ch_name); 2301 return 0; 2302 } 2303 2304 if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) { 2305 adc->int_ch[i] = chan; 2306 break; 2307 } 2308 2309 /* Get calibration data for vrefint channel */ 2310 ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); 2311 if (ret && ret != -ENOENT) { 2312 return dev_err_probe(indio_dev->dev.parent, ret, 2313 "nvmem access error\n"); 2314 } 2315 if (ret == -ENOENT) { 2316 dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n"); 2317 return ret; 2318 } else if (!vrefint) { 2319 dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n"); 2320 return -ENOENT; 2321 } 2322 adc->int_ch[i] = chan; 2323 adc->vrefint.vrefint_cal = vrefint; 2324 } 2325 } 2326 2327 return 0; 2328 } 2329 2330 static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, 2331 struct stm32_adc *adc, 2332 struct iio_chan_spec *channels) 2333 { 2334 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2335 struct device *dev = &indio_dev->dev; 2336 const char *name; 2337 int val, scan_index = 0, ret; 2338 bool differential; 2339 u32 vin[2]; 2340 2341 device_for_each_child_node_scoped(dev, child) { 2342 ret = fwnode_property_read_u32(child, "reg", &val); 2343 if (ret) 2344 return dev_err_probe(dev, ret, 2345 "Missing channel index\n"); 2346 2347 ret = fwnode_property_read_string(child, "label", &name); 2348 /* label is optional */ 2349 if (!ret) { 2350 if (strlen(name) >= STM32_ADC_CH_SZ) 2351 return dev_err_probe(dev, -EINVAL, 2352 "Label %s exceeds %d characters\n", 2353 name, STM32_ADC_CH_SZ); 2354 2355 strscpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2356 ret = stm32_adc_populate_int_ch(indio_dev, name, val); 2357 if (ret == -ENOENT) 2358 continue; 2359 else if (ret) 2360 return ret; 2361 } else if (ret != -EINVAL) { 2362 return dev_err_probe(dev, ret, "Invalid label\n"); 2363 } 2364 2365 if (val >= adc_info->max_channels) 2366 return dev_err_probe(dev, -EINVAL, 2367 "Invalid channel %d\n", val); 2368 2369 differential = false; 2370 ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2); 2371 /* diff-channels is optional */ 2372 if (!ret) { 2373 differential = true; 2374 if (vin[0] != val || vin[1] >= adc_info->max_channels) 2375 return dev_err_probe(dev, -EINVAL, 2376 "Invalid channel in%d-in%d\n", 2377 vin[0], vin[1]); 2378 } else if (ret != -EINVAL) { 2379 return dev_err_probe(dev, ret, 2380 "Invalid diff-channels property\n"); 2381 } 2382 2383 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 2384 vin[1], scan_index, differential); 2385 2386 val = 0; 2387 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val); 2388 /* st,min-sample-time-ns is optional */ 2389 if (ret && ret != -EINVAL) 2390 return dev_err_probe(dev, ret, 2391 "Invalid st,min-sample-time-ns property\n"); 2392 2393 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2394 if (differential) 2395 stm32_adc_smpr_init(adc, vin[1], val); 2396 2397 scan_index++; 2398 } 2399 2400 return scan_index; 2401 } 2402 2403 static int stm32_adc_chan_fw_init(struct iio_dev *indio_dev, bool timestamping) 2404 { 2405 struct stm32_adc *adc = iio_priv(indio_dev); 2406 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2407 struct iio_chan_spec *channels; 2408 int scan_index = 0, num_channels = 0, ret, i; 2409 bool legacy = false; 2410 2411 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2412 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; 2413 2414 num_channels = device_get_child_node_count(&indio_dev->dev); 2415 /* If no channels have been found, fallback to channels legacy properties. */ 2416 if (!num_channels) { 2417 legacy = true; 2418 2419 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); 2420 if (!ret) { 2421 dev_err(indio_dev->dev.parent, "No channel found\n"); 2422 return -ENODATA; 2423 } else if (ret < 0) { 2424 return ret; 2425 } 2426 2427 num_channels = ret; 2428 } 2429 2430 if (num_channels > adc_info->max_channels) { 2431 dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", 2432 num_channels, adc_info->max_channels); 2433 return -EINVAL; 2434 } 2435 2436 if (timestamping) 2437 num_channels++; 2438 2439 channels = devm_kcalloc(&indio_dev->dev, num_channels, 2440 sizeof(struct iio_chan_spec), GFP_KERNEL); 2441 if (!channels) 2442 return -ENOMEM; 2443 2444 if (legacy) 2445 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, 2446 timestamping ? num_channels - 1 : num_channels); 2447 else 2448 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); 2449 if (ret < 0) 2450 return ret; 2451 scan_index = ret; 2452 2453 if (timestamping) { 2454 channels[scan_index] = IIO_CHAN_SOFT_TIMESTAMP(scan_index); 2455 scan_index++; 2456 } 2457 2458 indio_dev->num_channels = scan_index; 2459 indio_dev->channels = channels; 2460 2461 return 0; 2462 } 2463 2464 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 2465 { 2466 struct stm32_adc *adc = iio_priv(indio_dev); 2467 struct dma_slave_config config = { }; 2468 int ret; 2469 2470 adc->dma_chan = dma_request_chan(dev, "rx"); 2471 if (IS_ERR(adc->dma_chan)) { 2472 ret = PTR_ERR(adc->dma_chan); 2473 if (ret != -ENODEV) 2474 return dev_err_probe(dev, ret, 2475 "DMA channel request failed with\n"); 2476 2477 /* DMA is optional: fall back to IRQ mode */ 2478 adc->dma_chan = NULL; 2479 return 0; 2480 } 2481 2482 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 2483 STM32_DMA_BUFFER_SIZE, 2484 &adc->rx_dma_buf, GFP_KERNEL); 2485 if (!adc->rx_buf) { 2486 ret = -ENOMEM; 2487 goto err_release; 2488 } 2489 2490 /* Configure DMA channel to read data register */ 2491 config.src_addr = (dma_addr_t)adc->common->phys_base; 2492 config.src_addr += adc->offset + adc->cfg->regs->dr; 2493 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2494 2495 ret = dmaengine_slave_config(adc->dma_chan, &config); 2496 if (ret) 2497 goto err_free; 2498 2499 return 0; 2500 2501 err_free: 2502 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 2503 adc->rx_buf, adc->rx_dma_buf); 2504 err_release: 2505 dma_release_channel(adc->dma_chan); 2506 2507 return ret; 2508 } 2509 2510 static int stm32_adc_probe(struct platform_device *pdev) 2511 { 2512 struct iio_dev *indio_dev; 2513 struct device *dev = &pdev->dev; 2514 irqreturn_t (*handler)(int irq, void *p) = NULL; 2515 struct stm32_adc *adc; 2516 bool timestamping = false; 2517 int ret; 2518 2519 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 2520 if (!indio_dev) 2521 return -ENOMEM; 2522 2523 adc = iio_priv(indio_dev); 2524 adc->common = dev_get_drvdata(pdev->dev.parent); 2525 spin_lock_init(&adc->lock); 2526 init_completion(&adc->completion); 2527 adc->cfg = device_get_match_data(dev); 2528 2529 indio_dev->name = dev_name(&pdev->dev); 2530 device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev)); 2531 indio_dev->info = &stm32_adc_iio_info; 2532 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 2533 2534 platform_set_drvdata(pdev, indio_dev); 2535 2536 ret = device_property_read_u32(dev, "reg", &adc->offset); 2537 if (ret != 0) { 2538 dev_err(&pdev->dev, "missing reg property\n"); 2539 return -EINVAL; 2540 } 2541 2542 adc->irq = platform_get_irq(pdev, 0); 2543 if (adc->irq < 0) 2544 return adc->irq; 2545 2546 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, 2547 stm32_adc_threaded_isr, 2548 0, pdev->name, indio_dev); 2549 if (ret) { 2550 dev_err(&pdev->dev, "failed to request IRQ\n"); 2551 return ret; 2552 } 2553 2554 adc->clk = devm_clk_get(&pdev->dev, NULL); 2555 if (IS_ERR(adc->clk)) { 2556 ret = PTR_ERR(adc->clk); 2557 if (ret == -ENOENT && !adc->cfg->clk_required) { 2558 adc->clk = NULL; 2559 } else { 2560 dev_err(&pdev->dev, "Can't get clock\n"); 2561 return ret; 2562 } 2563 } 2564 2565 ret = stm32_adc_fw_get_resolution(indio_dev); 2566 if (ret < 0) 2567 return ret; 2568 2569 ret = stm32_adc_dma_request(dev, indio_dev); 2570 if (ret < 0) 2571 return ret; 2572 2573 if (!adc->dma_chan) { 2574 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp 2575 * in the primary trigger IRQ handler and stm32_adc_trigger_handler 2576 * runs in the IRQ thread to push out buffer along with timestamp. 2577 */ 2578 handler = &stm32_adc_trigger_handler; 2579 timestamping = true; 2580 } 2581 2582 ret = stm32_adc_chan_fw_init(indio_dev, timestamping); 2583 if (ret < 0) 2584 goto err_dma_disable; 2585 2586 ret = iio_triggered_buffer_setup(indio_dev, 2587 &iio_pollfunc_store_time, handler, 2588 &stm32_adc_buffer_setup_ops); 2589 if (ret) { 2590 dev_err(&pdev->dev, "buffer setup failed\n"); 2591 goto err_dma_disable; 2592 } 2593 2594 /* Get stm32-adc-core PM online */ 2595 pm_runtime_get_noresume(dev); 2596 pm_runtime_set_active(dev); 2597 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS); 2598 pm_runtime_use_autosuspend(dev); 2599 pm_runtime_enable(dev); 2600 2601 ret = stm32_adc_hw_start(dev); 2602 if (ret) 2603 goto err_buffer_cleanup; 2604 2605 ret = iio_device_register(indio_dev); 2606 if (ret) { 2607 dev_err(&pdev->dev, "iio dev register failed\n"); 2608 goto err_hw_stop; 2609 } 2610 2611 pm_runtime_put_autosuspend(dev); 2612 2613 if (IS_ENABLED(CONFIG_DEBUG_FS)) 2614 stm32_adc_debugfs_init(indio_dev); 2615 2616 return 0; 2617 2618 err_hw_stop: 2619 stm32_adc_hw_stop(dev); 2620 2621 err_buffer_cleanup: 2622 pm_runtime_disable(dev); 2623 pm_runtime_set_suspended(dev); 2624 pm_runtime_put_noidle(dev); 2625 iio_triggered_buffer_cleanup(indio_dev); 2626 2627 err_dma_disable: 2628 if (adc->dma_chan) { 2629 dma_free_coherent(adc->dma_chan->device->dev, 2630 STM32_DMA_BUFFER_SIZE, 2631 adc->rx_buf, adc->rx_dma_buf); 2632 dma_release_channel(adc->dma_chan); 2633 } 2634 2635 return ret; 2636 } 2637 2638 static void stm32_adc_remove(struct platform_device *pdev) 2639 { 2640 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2641 struct stm32_adc *adc = iio_priv(indio_dev); 2642 2643 pm_runtime_get_sync(&pdev->dev); 2644 /* iio_device_unregister() also removes debugfs entries */ 2645 iio_device_unregister(indio_dev); 2646 stm32_adc_hw_stop(&pdev->dev); 2647 pm_runtime_disable(&pdev->dev); 2648 pm_runtime_set_suspended(&pdev->dev); 2649 pm_runtime_put_noidle(&pdev->dev); 2650 iio_triggered_buffer_cleanup(indio_dev); 2651 if (adc->dma_chan) { 2652 dma_free_coherent(adc->dma_chan->device->dev, 2653 STM32_DMA_BUFFER_SIZE, 2654 adc->rx_buf, adc->rx_dma_buf); 2655 dma_release_channel(adc->dma_chan); 2656 } 2657 } 2658 2659 static int stm32_adc_suspend(struct device *dev) 2660 { 2661 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2662 2663 if (iio_buffer_enabled(indio_dev)) 2664 stm32_adc_buffer_predisable(indio_dev); 2665 2666 return pm_runtime_force_suspend(dev); 2667 } 2668 2669 static int stm32_adc_resume(struct device *dev) 2670 { 2671 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2672 int ret; 2673 2674 ret = pm_runtime_force_resume(dev); 2675 if (ret < 0) 2676 return ret; 2677 2678 if (!iio_buffer_enabled(indio_dev)) 2679 return 0; 2680 2681 ret = stm32_adc_update_scan_mode(indio_dev, 2682 indio_dev->active_scan_mask); 2683 if (ret < 0) 2684 return ret; 2685 2686 return stm32_adc_buffer_postenable(indio_dev); 2687 } 2688 2689 static int stm32_adc_runtime_suspend(struct device *dev) 2690 { 2691 return stm32_adc_hw_stop(dev); 2692 } 2693 2694 static int stm32_adc_runtime_resume(struct device *dev) 2695 { 2696 return stm32_adc_hw_start(dev); 2697 } 2698 2699 static const struct dev_pm_ops stm32_adc_pm_ops = { 2700 SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume) 2701 RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume, 2702 NULL) 2703 }; 2704 2705 static const struct stm32_adc_cfg stm32f4_adc_cfg = { 2706 .regs = &stm32f4_adc_regspec, 2707 .adc_info = &stm32f4_adc_info, 2708 .trigs = stm32f4_adc_trigs, 2709 .clk_required = true, 2710 .start_conv = stm32f4_adc_start_conv, 2711 .stop_conv = stm32f4_adc_stop_conv, 2712 .smp_cycles = stm32f4_adc_smp_cycles, 2713 .irq_clear = stm32f4_adc_irq_clear, 2714 }; 2715 2716 static const unsigned int stm32_adc_min_ts_h7[] = { 0, 0, 0, 4300, 9000 }; 2717 static_assert(ARRAY_SIZE(stm32_adc_min_ts_h7) == STM32_ADC_INT_CH_NB); 2718 2719 static const struct stm32_adc_cfg stm32h7_adc_cfg = { 2720 .regs = &stm32h7_adc_regspec, 2721 .adc_info = &stm32h7_adc_info, 2722 .trigs = stm32h7_adc_trigs, 2723 .has_boostmode = true, 2724 .has_linearcal = true, 2725 .has_presel = true, 2726 .has_oversampling = true, 2727 .start_conv = stm32h7_adc_start_conv, 2728 .stop_conv = stm32h7_adc_stop_conv, 2729 .prepare = stm32h7_adc_prepare, 2730 .unprepare = stm32h7_adc_unprepare, 2731 .smp_cycles = stm32h7_adc_smp_cycles, 2732 .irq_clear = stm32h7_adc_irq_clear, 2733 .ts_int_ch = stm32_adc_min_ts_h7, 2734 .set_ovs = stm32h7_adc_set_ovs, 2735 }; 2736 2737 static const unsigned int stm32_adc_min_ts_mp1[] = { 100, 100, 100, 4300, 9800 }; 2738 static_assert(ARRAY_SIZE(stm32_adc_min_ts_mp1) == STM32_ADC_INT_CH_NB); 2739 2740 static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 2741 .regs = &stm32mp1_adc_regspec, 2742 .adc_info = &stm32h7_adc_info, 2743 .trigs = stm32h7_adc_trigs, 2744 .has_vregready = true, 2745 .has_boostmode = true, 2746 .has_linearcal = true, 2747 .has_presel = true, 2748 .has_oversampling = true, 2749 .start_conv = stm32h7_adc_start_conv, 2750 .stop_conv = stm32h7_adc_stop_conv, 2751 .prepare = stm32h7_adc_prepare, 2752 .unprepare = stm32h7_adc_unprepare, 2753 .smp_cycles = stm32h7_adc_smp_cycles, 2754 .irq_clear = stm32h7_adc_irq_clear, 2755 .ts_int_ch = stm32_adc_min_ts_mp1, 2756 .set_ovs = stm32h7_adc_set_ovs, 2757 }; 2758 2759 static const unsigned int stm32_adc_min_ts_mp13[] = { 100, 0, 0, 4300, 9800 }; 2760 static_assert(ARRAY_SIZE(stm32_adc_min_ts_mp13) == STM32_ADC_INT_CH_NB); 2761 2762 static const struct stm32_adc_cfg stm32mp13_adc_cfg = { 2763 .regs = &stm32mp13_adc_regspec, 2764 .adc_info = &stm32mp13_adc_info, 2765 .trigs = stm32h7_adc_trigs, 2766 .has_oversampling = true, 2767 .start_conv = stm32mp13_adc_start_conv, 2768 .stop_conv = stm32h7_adc_stop_conv, 2769 .prepare = stm32h7_adc_prepare, 2770 .unprepare = stm32h7_adc_unprepare, 2771 .smp_cycles = stm32mp13_adc_smp_cycles, 2772 .irq_clear = stm32h7_adc_irq_clear, 2773 .ts_int_ch = stm32_adc_min_ts_mp13, 2774 .set_ovs = stm32mp13_adc_set_ovs, 2775 }; 2776 2777 static const struct of_device_id stm32_adc_of_match[] = { 2778 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2779 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2780 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2781 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg }, 2782 { } 2783 }; 2784 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 2785 2786 static struct platform_driver stm32_adc_driver = { 2787 .probe = stm32_adc_probe, 2788 .remove = stm32_adc_remove, 2789 .driver = { 2790 .name = "stm32-adc", 2791 .of_match_table = stm32_adc_of_match, 2792 .pm = pm_ptr(&stm32_adc_pm_ops), 2793 }, 2794 }; 2795 module_platform_driver(stm32_adc_driver); 2796 2797 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2798 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2799 MODULE_LICENSE("GPL v2"); 2800 MODULE_ALIAS("platform:stm32-adc"); 2801