1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 #include <linux/platform_device.h> 16 17 /* Peripheral id registers (0xFD0-0xFEC) */ 18 #define CORESIGHT_PERIPHIDR4 0xfd0 19 #define CORESIGHT_PERIPHIDR5 0xfd4 20 #define CORESIGHT_PERIPHIDR6 0xfd8 21 #define CORESIGHT_PERIPHIDR7 0xfdC 22 #define CORESIGHT_PERIPHIDR0 0xfe0 23 #define CORESIGHT_PERIPHIDR1 0xfe4 24 #define CORESIGHT_PERIPHIDR2 0xfe8 25 #define CORESIGHT_PERIPHIDR3 0xfeC 26 /* Component id registers (0xFF0-0xFFC) */ 27 #define CORESIGHT_COMPIDR0 0xff0 28 #define CORESIGHT_COMPIDR1 0xff4 29 #define CORESIGHT_COMPIDR2 0xff8 30 #define CORESIGHT_COMPIDR3 0xffC 31 32 #define ETM_ARCH_V3_3 0x23 33 #define ETM_ARCH_V3_5 0x25 34 #define PFT_ARCH_V1_0 0x30 35 #define PFT_ARCH_V1_1 0x31 36 37 #define CORESIGHT_UNLOCK 0xc5acce55 38 39 extern const struct bus_type coresight_bustype; 40 41 enum coresight_dev_type { 42 CORESIGHT_DEV_TYPE_SINK, 43 CORESIGHT_DEV_TYPE_LINK, 44 CORESIGHT_DEV_TYPE_LINKSINK, 45 CORESIGHT_DEV_TYPE_SOURCE, 46 CORESIGHT_DEV_TYPE_HELPER, 47 CORESIGHT_DEV_TYPE_MAX 48 }; 49 50 enum coresight_dev_subtype_sink { 51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 52 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 56 }; 57 58 enum coresight_dev_subtype_link { 59 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 62 }; 63 64 enum coresight_dev_subtype_source { 65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 70 }; 71 72 enum coresight_dev_subtype_helper { 73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, 75 CORESIGHT_DEV_SUBTYPE_HELPER_CTCU, 76 }; 77 78 /** 79 * union coresight_dev_subtype - further characterisation of a type 80 * @sink_subtype: type of sink this component is, as defined 81 * by @coresight_dev_subtype_sink. 82 * @link_subtype: type of link this component is, as defined 83 * by @coresight_dev_subtype_link. 84 * @source_subtype: type of source this component is, as defined 85 * by @coresight_dev_subtype_source. 86 * @helper_subtype: type of helper this component is, as defined 87 * by @coresight_dev_subtype_helper. 88 */ 89 union coresight_dev_subtype { 90 /* We have some devices which acts as LINK and SINK */ 91 struct { 92 enum coresight_dev_subtype_sink sink_subtype; 93 enum coresight_dev_subtype_link link_subtype; 94 }; 95 enum coresight_dev_subtype_source source_subtype; 96 enum coresight_dev_subtype_helper helper_subtype; 97 }; 98 99 /** 100 * struct coresight_platform_data - data harvested from the firmware 101 * specification. 102 * 103 * @nr_inconns: Number of elements for the input connections. 104 * @nr_outconns: Number of elements for the output connections. 105 * @out_conns: Array of nr_outconns pointers to connections from this 106 * component. 107 * @in_conns: Sparse array of pointers to input connections. Sparse 108 * because the source device owns the connection so when it's 109 * unloaded the connection leaves an empty slot. 110 */ 111 struct coresight_platform_data { 112 int nr_inconns; 113 int nr_outconns; 114 struct coresight_connection **out_conns; 115 struct coresight_connection **in_conns; 116 }; 117 118 /** 119 * struct csdev_access - Abstraction of a CoreSight device access. 120 * 121 * @io_mem : True if the device has memory mapped I/O 122 * @base : When io_mem == true, base address of the component 123 * @read : Read from the given "offset" of the given instance. 124 * @write : Write "val" to the given "offset". 125 */ 126 struct csdev_access { 127 bool io_mem; 128 union { 129 void __iomem *base; 130 struct { 131 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 132 void (*write)(u64 val, u32 offset, bool relaxed, 133 bool _64bit); 134 }; 135 }; 136 }; 137 138 #define CSDEV_ACCESS_IOMEM(_addr) \ 139 ((struct csdev_access) { \ 140 .io_mem = true, \ 141 .base = (_addr), \ 142 }) 143 144 #define CORESIGHT_DESC_CPU_BOUND BIT(0) 145 146 /** 147 * struct coresight_desc - description of a component required from drivers 148 * @type: as defined by @coresight_dev_type. 149 * @subtype: as defined by @coresight_dev_subtype. 150 * @ops: generic operations for this component, as defined 151 * by @coresight_ops. 152 * @pdata: platform data collected from DT. 153 * @dev: The device entity associated to this component. 154 * @groups: operations specific to this component. These will end up 155 * in the component's sysfs sub-directory. 156 * @name: name for the coresight device, also shown under sysfs. 157 * @access: Describe access to the device 158 * @flags: The descritpion flags. 159 * @cpu: The CPU this component is affined to. 160 */ 161 struct coresight_desc { 162 enum coresight_dev_type type; 163 union coresight_dev_subtype subtype; 164 const struct coresight_ops *ops; 165 struct coresight_platform_data *pdata; 166 struct device *dev; 167 const struct attribute_group **groups; 168 const char *name; 169 struct csdev_access access; 170 u32 flags; 171 int cpu; 172 }; 173 174 /** 175 * struct coresight_connection - representation of a single connection 176 * @src_port: a connection's output port number. 177 * @dest_port: destination's input port number @src_port is connected to. 178 * @dest_fwnode: destination component's fwnode handle. 179 * @dest_dev: a @coresight_device representation of the component 180 connected to @src_port. NULL until the device is created 181 * @link: Representation of the connection as a sysfs link. 182 * @filter_src_fwnode: filter source component's fwnode handle. 183 * @filter_src_dev: a @coresight_device representation of the component that 184 needs to be filtered. 185 * 186 * The full connection structure looks like this, where in_conns store 187 * references to same connection as the source device's out_conns. 188 * 189 * +-----------------------------+ +-----------------------------+ 190 * |coresight_device | |coresight_connection | 191 * |-----------------------------| |-----------------------------| 192 * | | | | 193 * | | | dest_dev*|<-- 194 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 195 * | | | | | 196 * +-----------------------------+ +-----------------------------+ | 197 * | 198 * +-----------------------------+ | 199 * |coresight_device | | 200 * |------------------------------ | 201 * | | | 202 * | pdata->in_conns[nr_inconns]|<-- 203 * | | 204 * +-----------------------------+ 205 */ 206 struct coresight_connection { 207 int src_port; 208 int dest_port; 209 struct fwnode_handle *dest_fwnode; 210 struct coresight_device *dest_dev; 211 struct coresight_sysfs_link *link; 212 struct coresight_device *src_dev; 213 struct fwnode_handle *filter_src_fwnode; 214 struct coresight_device *filter_src_dev; 215 int src_refcnt; 216 int dest_refcnt; 217 }; 218 219 /** 220 * struct coresight_sysfs_link - representation of a connection in sysfs. 221 * @orig: Originating (master) coresight device for the link. 222 * @orig_name: Name to use for the link orig->target. 223 * @target: Target (slave) coresight device for the link. 224 * @target_name: Name to use for the link target->orig. 225 */ 226 struct coresight_sysfs_link { 227 struct coresight_device *orig; 228 const char *orig_name; 229 struct coresight_device *target; 230 const char *target_name; 231 }; 232 233 /* architecturally we have 128 IDs some of which are reserved */ 234 #define CORESIGHT_TRACE_IDS_MAX 128 235 236 /** 237 * Trace ID map. 238 * 239 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. 240 * Initialised so that the reserved IDs are permanently marked as 241 * in use. 242 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. 243 */ 244 struct coresight_trace_id_map { 245 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); 246 atomic_t __percpu *cpu_map; 247 atomic_t perf_cs_etm_session_active; 248 raw_spinlock_t lock; 249 }; 250 251 /** 252 * struct coresight_device - representation of a device as used by the framework 253 * @pdata: Platform data with device connections associated to this device. 254 * @type: as defined by @coresight_dev_type. 255 * @subtype: as defined by @coresight_dev_subtype. 256 * @ops: generic operations for this component, as defined 257 * by @coresight_ops. 258 * @access: Device i/o access abstraction for this device. 259 * @dev: The device entity associated to this component. 260 * @path: Activated path pointer (only used for source device). 261 * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually 262 * an 'enum cs_mode' but stored in an atomic type. Access is always 263 * through atomic APIs, ensuring SMP-safe synchronisation between 264 * racing from sysFS and Perf mode. A compare-and-exchange 265 * operation is done to atomically claim one mode or the other. 266 * @refcnt: keep track of what is in use. Only access this outside of the 267 * device's spinlock when the coresight_mutex held and mode == 268 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the 269 * spinlock. 270 * @cpu: The CPU this component is affined to (-1 for not CPU bound). 271 * @orphan: true if the component has connections that haven't been linked. 272 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs 273 * by writing a 1 to the 'enable_sink' file. A sink can be 274 * activated but not yet enabled. Enabling for a _sink_ happens 275 * when a source has been selected and a path is enabled from 276 * source to that sink. A sink can also become enabled but not 277 * activated if it's used via Perf. 278 * @ea: Device attribute for sink representation under PMU directory. 279 * @def_sink: cached reference to default sink found for this device. 280 * @nr_links: number of sysfs links created to other components from this 281 * device. These will appear in the "connections" group. 282 * @has_conns_grp: Have added a "connections" group for sysfs links. 283 * @feature_csdev_list: List of complex feature programming added to the device. 284 * @config_csdev_list: List of system configurations added to the device. 285 * @cscfg_csdev_lock: Protect the lists of configurations and features. 286 * @active_cscfg_ctxt: Context information for current active system configuration. 287 */ 288 struct coresight_device { 289 struct coresight_platform_data *pdata; 290 enum coresight_dev_type type; 291 union coresight_dev_subtype subtype; 292 const struct coresight_ops *ops; 293 struct csdev_access access; 294 struct device dev; 295 struct coresight_path *path; 296 atomic_t mode; 297 int refcnt; 298 int cpu; 299 bool orphan; 300 /* sink specific fields */ 301 bool sysfs_sink_activated; 302 struct dev_ext_attribute *ea; 303 struct coresight_device *def_sink; 304 struct coresight_trace_id_map perf_sink_id_map; 305 /* sysfs links between components */ 306 int nr_links; 307 bool has_conns_grp; 308 /* system configuration and feature lists */ 309 struct list_head feature_csdev_list; 310 struct list_head config_csdev_list; 311 raw_spinlock_t cscfg_csdev_lock; 312 void *active_cscfg_ctxt; 313 }; 314 315 /* 316 * coresight_dev_list - Mapping for devices to "name" index for device 317 * names. 318 * 319 * @node: Node on the global device index list. 320 * @nr_idx: Number of entries already allocated. 321 * @pfx: Prefix pattern for device name. 322 * @fwnode_list: Array of fwnode_handles associated with each allocated 323 * index, upto nr_idx entries. 324 */ 325 struct coresight_dev_list { 326 struct list_head node; 327 int nr_idx; 328 char *pfx; 329 struct fwnode_handle **fwnode_list; 330 }; 331 332 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 333 334 /** 335 * struct coresight_path - data needed by enable/disable path 336 * @path_list: path from source to sink. 337 * @trace_id: trace_id of the whole path. 338 * @handle: handle of the aux_event. 339 */ 340 struct coresight_path { 341 struct list_head path_list; 342 u8 trace_id; 343 struct perf_output_handle *handle; 344 }; 345 346 enum cs_mode { 347 CS_MODE_DISABLED = 0, 348 CS_MODE_SYSFS = BIT(0), 349 CS_MODE_PERF = BIT(1), 350 }; 351 352 #define coresight_ops(csdev) csdev->ops 353 #define source_ops(csdev) csdev->ops->source_ops 354 #define sink_ops(csdev) csdev->ops->sink_ops 355 #define link_ops(csdev) csdev->ops->link_ops 356 #define helper_ops(csdev) csdev->ops->helper_ops 357 #define ect_ops(csdev) csdev->ops->ect_ops 358 #define panic_ops(csdev) csdev->ops->panic_ops 359 360 /** 361 * struct coresight_ops_sink - basic operations for a sink 362 * Operations available for sinks 363 * @enable: enables the sink. 364 * @disable: disables the sink. 365 * @alloc_buffer: initialises perf's ring buffer for trace collection. 366 * @free_buffer: release memory allocated in @get_config. 367 * @update_buffer: update buffer pointers after a trace session. 368 */ 369 struct coresight_ops_sink { 370 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 371 struct coresight_path *path); 372 int (*disable)(struct coresight_device *csdev); 373 void *(*alloc_buffer)(struct coresight_device *csdev, 374 struct perf_event *event, void **pages, 375 int nr_pages, bool overwrite); 376 void (*free_buffer)(void *config); 377 unsigned long (*update_buffer)(struct coresight_device *csdev, 378 struct perf_output_handle *handle, 379 void *sink_config); 380 }; 381 382 /** 383 * struct coresight_ops_link - basic operations for a link 384 * Operations available for links. 385 * @enable: enables flow between iport and oport. 386 * @disable: disables flow between iport and oport. 387 */ 388 struct coresight_ops_link { 389 int (*enable)(struct coresight_device *csdev, 390 struct coresight_connection *in, 391 struct coresight_connection *out); 392 void (*disable)(struct coresight_device *csdev, 393 struct coresight_connection *in, 394 struct coresight_connection *out); 395 }; 396 397 /** 398 * struct coresight_ops_source - basic operations for a source 399 * Operations available for sources. 400 * @enable: enables tracing for a source. 401 * @disable: disables tracing for a source. 402 * @resume_perf: resumes tracing for a source in perf session. 403 * @pause_perf: pauses tracing for a source in perf session. 404 */ 405 struct coresight_ops_source { 406 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 407 enum cs_mode mode, struct coresight_path *path); 408 void (*disable)(struct coresight_device *csdev, 409 struct perf_event *event); 410 int (*resume_perf)(struct coresight_device *csdev); 411 void (*pause_perf)(struct coresight_device *csdev); 412 }; 413 414 /** 415 * struct coresight_ops_helper - Operations for a helper device. 416 * 417 * All operations could pass in a device specific data, which could 418 * help the helper device to determine what to do. 419 * 420 * @enable : Enable the device 421 * @disable : Disable the device 422 */ 423 struct coresight_ops_helper { 424 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 425 struct coresight_path *path); 426 int (*disable)(struct coresight_device *csdev, 427 struct coresight_path *path); 428 }; 429 430 431 /** 432 * struct coresight_ops_panic - Generic device ops for panic handing 433 * 434 * @sync : Sync the device register state/trace data 435 */ 436 struct coresight_ops_panic { 437 int (*sync)(struct coresight_device *csdev); 438 }; 439 440 struct coresight_ops { 441 int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, 442 struct coresight_device *sink); 443 int (*pm_save_disable)(struct coresight_device *csdev); 444 void (*pm_restore_enable)(struct coresight_device *csdev); 445 const struct coresight_ops_sink *sink_ops; 446 const struct coresight_ops_link *link_ops; 447 const struct coresight_ops_source *source_ops; 448 const struct coresight_ops_helper *helper_ops; 449 const struct coresight_ops_panic *panic_ops; 450 }; 451 452 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 453 u32 offset) 454 { 455 if (likely(csa->io_mem)) 456 return readl_relaxed(csa->base + offset); 457 458 return csa->read(offset, true, false); 459 } 460 461 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 462 463 static inline u32 coresight_get_cid(void __iomem *base) 464 { 465 u32 i, cid = 0; 466 467 for (i = 0; i < 4; i++) 468 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 469 470 return cid; 471 } 472 473 static inline bool is_coresight_device(void __iomem *base) 474 { 475 u32 cid = coresight_get_cid(base); 476 477 return cid == CORESIGHT_CID; 478 } 479 480 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 481 482 static inline u32 coresight_get_pid(struct csdev_access *csa) 483 { 484 u32 i, pid = 0; 485 486 for (i = 0; i < 4; i++) 487 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 488 489 return pid; 490 } 491 492 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 493 u32 lo_offset, u32 hi_offset) 494 { 495 if (likely(csa->io_mem)) { 496 return readl_relaxed(csa->base + lo_offset) | 497 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 498 } 499 500 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 501 } 502 503 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 504 u32 lo_offset, u32 hi_offset) 505 { 506 if (likely(csa->io_mem)) { 507 writel_relaxed((u32)val, csa->base + lo_offset); 508 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 509 } else { 510 csa->write((u32)val, lo_offset, true, false); 511 csa->write((u32)(val >> 32), hi_offset, true, false); 512 } 513 } 514 515 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 516 { 517 if (likely(csa->io_mem)) 518 return readl(csa->base + offset); 519 520 return csa->read(offset, false, false); 521 } 522 523 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 524 u32 val, u32 offset) 525 { 526 if (likely(csa->io_mem)) 527 writel_relaxed(val, csa->base + offset); 528 else 529 csa->write(val, offset, true, false); 530 } 531 532 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 533 { 534 if (likely(csa->io_mem)) 535 writel(val, csa->base + offset); 536 else 537 csa->write(val, offset, false, false); 538 } 539 540 #ifdef CONFIG_64BIT 541 542 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 543 u32 offset) 544 { 545 if (likely(csa->io_mem)) 546 return readq_relaxed(csa->base + offset); 547 548 return csa->read(offset, true, true); 549 } 550 551 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 552 { 553 if (likely(csa->io_mem)) 554 return readq(csa->base + offset); 555 556 return csa->read(offset, false, true); 557 } 558 559 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 560 u64 val, u32 offset) 561 { 562 if (likely(csa->io_mem)) 563 writeq_relaxed(val, csa->base + offset); 564 else 565 csa->write(val, offset, true, true); 566 } 567 568 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 569 { 570 if (likely(csa->io_mem)) 571 writeq(val, csa->base + offset); 572 else 573 csa->write(val, offset, false, true); 574 } 575 576 #else /* !CONFIG_64BIT */ 577 578 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 579 u32 offset) 580 { 581 WARN_ON(1); 582 return 0; 583 } 584 585 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 586 { 587 WARN_ON(1); 588 return 0; 589 } 590 591 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 592 u64 val, u32 offset) 593 { 594 WARN_ON(1); 595 } 596 597 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 598 { 599 WARN_ON(1); 600 } 601 #endif /* CONFIG_64BIT */ 602 603 static inline bool coresight_is_device_source(struct coresight_device *csdev) 604 { 605 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE); 606 } 607 608 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 609 { 610 return csdev && coresight_is_device_source(csdev) && 611 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 612 } 613 614 static inline bool coresight_is_software_source(struct coresight_device *csdev) 615 { 616 return csdev && coresight_is_device_source(csdev) && 617 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE); 618 } 619 620 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 621 { 622 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 623 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 624 } 625 626 /* 627 * Atomically try to take the device and set a new mode. Returns true on 628 * success, false if the device is already taken by someone else. 629 */ 630 static inline bool coresight_take_mode(struct coresight_device *csdev, 631 enum cs_mode new_mode) 632 { 633 int curr = CS_MODE_DISABLED; 634 635 return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode); 636 } 637 638 static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) 639 { 640 return atomic_read_acquire(&csdev->mode); 641 } 642 643 static inline void coresight_set_mode(struct coresight_device *csdev, 644 enum cs_mode new_mode) 645 { 646 enum cs_mode current_mode = coresight_get_mode(csdev); 647 648 /* 649 * Changing to a new mode must be done from an already disabled state 650 * unless it's synchronized with coresight_take_mode(). Otherwise the 651 * device is already in use and signifies a locking issue. 652 */ 653 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && 654 current_mode != new_mode, "Device already in use\n"); 655 656 atomic_set_release(&csdev->mode, new_mode); 657 } 658 659 struct coresight_device *coresight_register(struct coresight_desc *desc); 660 void coresight_unregister(struct coresight_device *csdev); 661 int coresight_enable_sysfs(struct coresight_device *csdev); 662 void coresight_disable_sysfs(struct coresight_device *csdev); 663 int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value); 664 typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int); 665 int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value, 666 coresight_timeout_cb_t cb); 667 int coresight_claim_device(struct coresight_device *csdev); 668 int coresight_claim_device_unlocked(struct coresight_device *csdev); 669 670 int coresight_claim_device(struct coresight_device *csdev); 671 int coresight_claim_device_unlocked(struct coresight_device *csdev); 672 void coresight_clear_self_claim_tag(struct csdev_access *csa); 673 void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa); 674 void coresight_disclaim_device(struct coresight_device *csdev); 675 void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 676 char *coresight_alloc_device_name(const char *prefix, struct device *dev); 677 678 bool coresight_loses_context_with_cpu(struct device *dev); 679 680 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 681 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 682 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 683 void coresight_relaxed_write32(struct coresight_device *csdev, 684 u32 val, u32 offset); 685 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 686 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 687 void coresight_relaxed_write64(struct coresight_device *csdev, 688 u64 val, u32 offset); 689 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 690 691 int coresight_get_cpu(struct device *dev); 692 int coresight_get_static_trace_id(struct device *dev, u32 *id); 693 694 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 695 struct coresight_connection * 696 coresight_add_out_conn(struct device *dev, 697 struct coresight_platform_data *pdata, 698 const struct coresight_connection *new_conn); 699 int coresight_add_in_conn(struct coresight_connection *conn); 700 struct coresight_device * 701 coresight_find_input_type(struct coresight_platform_data *pdata, 702 enum coresight_dev_type type, 703 union coresight_dev_subtype subtype); 704 struct coresight_device * 705 coresight_find_output_type(struct coresight_platform_data *pdata, 706 enum coresight_dev_type type, 707 union coresight_dev_subtype subtype); 708 709 int coresight_init_driver_with_owner(const char *drv, struct amba_driver *amba_drv, 710 struct platform_driver *pdev_drv, struct module *owner, 711 const char *mod_name); 712 #define coresight_init_driver(drv, amba_drv, pdev_drv) \ 713 coresight_init_driver_with_owner(drv, amba_drv, pdev_drv, THIS_MODULE, KBUILD_MODNAME) 714 715 void coresight_remove_driver(struct amba_driver *amba_drv, 716 struct platform_driver *pdev_drv); 717 int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, 718 struct coresight_device *sink); 719 int coresight_get_enable_clocks(struct device *dev, struct clk **pclk, 720 struct clk **atclk); 721 #endif /* _LINUX_COREISGHT_H */ 722