1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "fw.h"
9 #include "mac.h"
10 #include "phy.h"
11 #include "reg.h"
12 #include "rtw8852c.h"
13 #include "rtw8852c_rfk.h"
14 #include "rtw8852c_table.h"
15 #include "sar.h"
16 #include "util.h"
17
18 #define RTW8852C_FW_FORMAT_MAX 2
19 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw"
20 #define RTW8852C_MODULE_FIRMWARE \
21 RTW89_GEN_MODULE_FWNAME(RTW8852C_FW_BASENAME, RTW8852C_FW_FORMAT_MAX)
22
23 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
24 {13, 1614, grp_0}, /* ACH 0 */
25 {13, 1614, grp_0}, /* ACH 1 */
26 {13, 1614, grp_0}, /* ACH 2 */
27 {13, 1614, grp_0}, /* ACH 3 */
28 {13, 1614, grp_1}, /* ACH 4 */
29 {13, 1614, grp_1}, /* ACH 5 */
30 {13, 1614, grp_1}, /* ACH 6 */
31 {13, 1614, grp_1}, /* ACH 7 */
32 {13, 1614, grp_0}, /* B0MGQ */
33 {13, 1614, grp_0}, /* B0HIQ */
34 {13, 1614, grp_1}, /* B1MGQ */
35 {13, 1614, grp_1}, /* B1HIQ */
36 {40, 0, 0} /* FWCMDQ */
37 };
38
39 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = {
40 1614, /* Group 0 */
41 1614, /* Group 1 */
42 3228, /* Public Max */
43 0 /* WP threshold */
44 };
45
46 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = {
47 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie,
48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 RTW89_HCIFC_POH},
51 [RTW89_QTA_INVALID] = {NULL},
52 };
53
54 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_usb[] = {
55 {18, 344, grp_0}, /* ACH 0 */
56 {0, 0, grp_0}, /* ACH 1 */
57 {18, 344, grp_0}, /* ACH 2 */
58 {0, 0, grp_0}, /* ACH 3 */
59 {18, 344, grp_0}, /* ACH 4 */
60 {0, 0, grp_0}, /* ACH 5 */
61 {18, 344, grp_0}, /* ACH 6 */
62 {0, 0, grp_0}, /* ACH 7 */
63 {18, 344, grp_0}, /* B0MGQ */
64 {0, 0, grp_0}, /* B0HIQ */
65 {18, 344, grp_0}, /* B1MGQ */
66 {0, 0, grp_0}, /* B1HIQ */
67 {0, 0, 0} /* FWCMDQ */
68 };
69
70 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_usb = {
71 344, /* Group 0 */
72 0, /* Group 1 */
73 344, /* Public Max */
74 0 /* WP threshold */
75 };
76
77 static const struct rtw89_hfc_prec_cfg rtw8852c_hfc_preccfg_usb = {
78 9, /* CH 0-11 pre-cost */
79 32, /* H2C pre-cost */
80 146, /* WP CH 0-7 pre-cost */
81 146, /* WP CH 8-11 pre-cost */
82 1, /* CH 0-11 full condition */
83 1, /* H2C full condition */
84 1, /* WP CH 0-7 full condition */
85 1, /* WP CH 8-11 full condition */
86 };
87
88 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_usb[] = {
89 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_usb, &rtw8852c_hfc_pubcfg_usb,
90 &rtw8852c_hfc_preccfg_usb, RTW89_HCIFC_STF},
91 [RTW89_QTA_DLFW] = {NULL, NULL,
92 &rtw8852c_hfc_preccfg_usb, RTW89_HCIFC_STF},
93 [RTW89_QTA_INVALID] = {NULL},
94 };
95
96 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
97 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19,
98 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18,
99 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46,
100 &rtw89_mac_size.ple_qt47},
101 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
102 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
103 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
104 &rtw89_mac_size.ple_qt45},
105 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
106 NULL},
107 };
108
109 static const struct rtw89_dle_mem rtw8852c_dle_mem_usb2[] = {
110 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size31,
111 &rtw89_mac_size.ple_size34, &rtw89_mac_size.wde_qt31,
112 &rtw89_mac_size.wde_qt31, &rtw89_mac_size.ple_qt78,
113 &rtw89_mac_size.ple_qt79},
114 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
115 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
116 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
117 &rtw89_mac_size.ple_qt45},
118 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
119 NULL},
120 };
121
122 static const struct rtw89_dle_mem rtw8852c_dle_mem_usb3[] = {
123 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size17,
124 &rtw89_mac_size.ple_size17, &rtw89_mac_size.wde_qt16,
125 &rtw89_mac_size.wde_qt16, &rtw89_mac_size.ple_qt42,
126 &rtw89_mac_size.ple_qt43},
127 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
128 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
129 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
130 &rtw89_mac_size.ple_qt45},
131 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
132 NULL},
133 };
134
135 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
136 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
137 R_AX_H2CREG_DATA3_V1
138 };
139
140 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
141 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1,
142 R_AX_C2HREG_DATA3_V1
143 };
144
145 static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
146 R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW,
147 };
148
149 static const struct rtw89_page_regs rtw8852c_page_regs = {
150 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
151 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
152 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1,
153 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1,
154 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1,
155 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1,
156 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1,
157 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1,
158 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1,
159 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1,
160 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1,
161 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1,
162 };
163
164 static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
165 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
166 };
167
168 static const struct rtw89_imr_info rtw8852c_imr_info = {
169 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1,
170 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR,
171 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR,
172 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1,
173 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1,
174 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
175 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR,
176 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1,
177 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1,
178 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR,
179 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1,
180 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1,
181 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1,
182 .wde_imr_set = B_AX_WDE_IMR_SET_V1,
183 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1,
184 .ple_imr_set = B_AX_PLE_IMR_SET_V1,
185 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1,
186 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1,
187 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1,
188 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1,
189 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1,
190 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1,
191 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR,
192 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
193 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1,
194 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR,
195 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1,
196 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1,
197 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR,
198 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1,
199 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1,
200 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR,
201 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1,
202 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1,
203 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1,
204 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1,
205 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1,
206 .rmac_imr_reg = R_AX_RX_ERR_IMR,
207 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1,
208 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1,
209 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK,
210 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1,
211 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
212 };
213
214 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = {
215 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
216 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2},
217 };
218
219 static const struct rtw89_rfkill_regs rtw8852c_rfkill_regs = {
220 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
221 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
222 0xf},
223 .mode = {R_AX_GPIO_EXT_CTRL + 2,
224 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
225 0x0},
226 };
227
228 static const struct rtw89_dig_regs rtw8852c_dig_regs = {
229 .seg0_pd_reg = R_SEG0R_PD,
230 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
231 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
232 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
233 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
234 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
235 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
236 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
237 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
238 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
239 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
240 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
241 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
242 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1,
243 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
244 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1,
245 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
246 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1,
247 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
248 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1,
249 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
250 };
251
252 static const struct rtw89_edcca_regs rtw8852c_edcca_regs = {
253 .edcca_level = R_SEG0R_EDCCA_LVL,
254 .edcca_mask = B_EDCCA_LVL_MSK0,
255 .edcca_p_mask = B_EDCCA_LVL_MSK1,
256 .ppdu_level = R_SEG0R_EDCCA_LVL,
257 .ppdu_mask = B_EDCCA_LVL_MSK3,
258 .p = {{
259 .rpt_a = R_EDCCA_RPT_A,
260 .rpt_b = R_EDCCA_RPT_B,
261 .rpt_sel = R_EDCCA_RPT_SEL,
262 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
263 }, {
264 .rpt_a = R_EDCCA_RPT_P1_A,
265 .rpt_b = R_EDCCA_RPT_P1_B,
266 .rpt_sel = R_EDCCA_RPT_SEL,
267 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
268 }},
269 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
270 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
271 };
272
273 static const struct rtw89_pmac_regs rtw8852c_pmac_regs = {
274 .cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
275 .cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
276 .cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
277 .cck_sfd_gg = {R_SFD_GG_CNT_V1, B_SFD_GG_CNT},
278 .cck_sig_gg = {R_SIG_GG_CNT_V1, B_SIG_GG_CNT_V1},
279 .cck_spoofing = {R_SPOOF_CNT_V1, B_SPOOF_CNT_V1},
280 .cck_brk = {R_BRK_CNT, B_BRK_CNT},
281 .brk = {R_CNT_BRK, B_CNT_BRK},
282 .brk_option = {R_BRK_OPT, B_BRK_OPT},
283 .search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
284 .lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
285 .lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
286 .rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
287 .rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
288 .ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
289 .cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
290 .ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
291 .r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_V1, B_R1B_RX_RPT_RST_V1},
292 .r1b_rr_sel = {},
293 .enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
294 .rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
295 .cck_crc32 = R_CNT_CCK_CRC32_P0,
296 .cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
297 .cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
298 .ofdm_txon = R_CNT_OFDMTXON,
299 .ofdm_txon_mask = B_CNT_OFDMTXON,
300 .ofdm_txen_mask = B_CNT_OFDMTXEN,
301 .l_crc = R_CNT_L_CRC,
302 .l_crc_ok_mask = B_CNT_L_CRC_OK,
303 .l_crc_err_mask = B_CNT_L_CRC_ERR,
304 .ht_crc = R_CNT_HT_CRC,
305 .ht_crc_ok_mask = B_CNT_HT_CRC_OK,
306 .ht_crc_err_mask = B_CNT_HT_CRC_ERR,
307 .vht_crc = R_CNT_VHT_CRC,
308 .vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
309 .vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
310 .he_crc = R_CNT_HE_CRC,
311 .he_crc_ok_mask = B_CNT_HE_CRC_OK,
312 .he_crc_err_mask = B_CNT_HE_CRC_ERR,
313 .eht_crc = 0,
314 .eht_crc_ok_mask = 0,
315 .eht_crc_err_mask = 0,
316 .ampdu_crc = R_CNT_AMPDU_RX_CRC32,
317 .ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
318 .ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
319 };
320
321 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
322 enum rtw89_phy_idx phy_idx);
323
324 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
325 enum rtw89_mac_idx mac_idx);
326
rtw8852c_pwr_on_func(struct rtw89_dev * rtwdev)327 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
328 {
329 u32 val32;
330 int ret;
331
332 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
333 if (val32 == MAC_AX_HCI_SEL_PCIE_USB ||
334 rtwdev->hci.type == RTW89_HCI_TYPE_USB)
335 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
336
337 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
338 B_AX_AFSM_PCIE_SUS_EN);
339 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
340 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
341 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
342 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
343
344 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
345 B_AX_OCP_L1_MASK, 0x7);
346
347 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
348 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
349 if (ret)
350 return ret;
351
352 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
353 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
354
355 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
356 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
357 if (ret)
358 return ret;
359
360 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
361 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
362 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
363 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
364
365 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
366
367 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
368 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
369
370 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
371 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
372 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
373 B_AX_R_SYM_WLCMAC1_P3_PC_EN |
374 B_AX_R_SYM_WLCMAC1_P2_PC_EN |
375 B_AX_R_SYM_WLCMAC1_P1_PC_EN |
376 B_AX_R_SYM_WLCMAC1_PC_EN);
377 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
378
379 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
380 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
381 if (ret)
382 return ret;
383
384 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
385
386 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
387 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
388 if (ret)
389 return ret;
390 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
391 XTAL_SI_OFF_WEI);
392 if (ret)
393 return ret;
394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
395 XTAL_SI_OFF_EI);
396 if (ret)
397 return ret;
398 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
399 if (ret)
400 return ret;
401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
402 XTAL_SI_PON_WEI);
403 if (ret)
404 return ret;
405 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
406 XTAL_SI_PON_EI);
407 if (ret)
408 return ret;
409 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
410 if (ret)
411 return ret;
412 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS);
413 if (ret)
414 return ret;
415 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
416 if (ret)
417 return ret;
418
419 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
420 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
421 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
422
423 fsleep(1000);
424
425 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
426 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
427
428 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
429 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
430 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
431 B_AX_LED1_PULL_LOW_EN);
432
433 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
434 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
435 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
436 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
437 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
438 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
439 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN);
440
441 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
442 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
443 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN |
444 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
445 B_AX_TMAC_EN | B_AX_RMAC_EN);
446
447 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
448 PINMUX_EESK_FUNC_SEL_BT_LOG);
449
450 return 0;
451 }
452
rtw8852c_pwr_off_func(struct rtw89_dev * rtwdev)453 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
454 {
455 u32 val32;
456 int ret;
457
458 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
459 XTAL_SI_RFC2RF);
460 if (ret)
461 return ret;
462 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
463 if (ret)
464 return ret;
465 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
466 if (ret)
467 return ret;
468 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
469 if (ret)
470 return ret;
471 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
472 if (ret)
473 return ret;
474 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
475 XTAL_SI_SRAM2RFC);
476 if (ret)
477 return ret;
478 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
479 if (ret)
480 return ret;
481 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
482 if (ret)
483 return ret;
484
485 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
486 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
487 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
488 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
489 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1);
490 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
491
492 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
493 if (ret)
494 return ret;
495
496 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
497
498 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
499 if (ret)
500 return ret;
501
502 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
503
504 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
505 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
506 if (ret)
507 return ret;
508
509 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
510 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
511 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
512 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR);
513
514 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
515 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
516 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
517 B_AX_REG_ZCDC_H_MASK, 0x3);
518
519 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
520 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
521 } else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) {
522 val32 = rtw89_read32(rtwdev, R_AX_SYS_PW_CTRL);
523 val32 &= ~B_AX_AFSM_PCIE_SUS_EN;
524 val32 |= B_AX_AFSM_WLSUS_EN;
525 rtw89_write32(rtwdev, R_AX_SYS_PW_CTRL, val32);
526 }
527
528 return 0;
529 }
530
rtw8852c_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852c_efuse * map)531 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
532 struct rtw8852c_efuse *map)
533 {
534 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
535 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
536 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
537 u8 i, j;
538
539 tssi->thermal[RF_PATH_A] = map->path_a_therm;
540 tssi->thermal[RF_PATH_B] = map->path_b_therm;
541
542 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
543 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
544 sizeof(ofst[i]->cck_tssi));
545
546 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
547 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
548 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
549 i, j, tssi->tssi_cck[i][j]);
550
551 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
552 sizeof(ofst[i]->bw40_tssi));
553 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
554 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
555 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
556 sizeof(tssi->tssi_6g_mcs[i]));
557
558 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
559 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
560 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
561 i, j, tssi->tssi_mcs[i][j]);
562 }
563 }
564
_decode_efuse_gain(u8 data,s8 * high,s8 * low)565 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
566 {
567 if (high)
568 *high = FIELD_GET_SIGNED(GENMASK(7, 4), data);
569 if (low)
570 *low = FIELD_GET_SIGNED(GENMASK(3, 0), data);
571
572 return data != 0xff;
573 }
574
rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8852c_efuse * map)575 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
576 struct rtw8852c_efuse *map)
577 {
578 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
579 bool valid = false;
580
581 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
582 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
583 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
584 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
585 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
586 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
587 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
588 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
589 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
590 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
591 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
592 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
593 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
594 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
595 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
596 valid |= _decode_efuse_gain(map->rx_gain_6g_l0,
597 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0],
598 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]);
599 valid |= _decode_efuse_gain(map->rx_gain_6g_l1,
600 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1],
601 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]);
602 valid |= _decode_efuse_gain(map->rx_gain_6g_m0,
603 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0],
604 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]);
605 valid |= _decode_efuse_gain(map->rx_gain_6g_m1,
606 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1],
607 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]);
608 valid |= _decode_efuse_gain(map->rx_gain_6g_h0,
609 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0],
610 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]);
611 valid |= _decode_efuse_gain(map->rx_gain_6g_h1,
612 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1],
613 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]);
614 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0,
615 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0],
616 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]);
617 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1,
618 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1],
619 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]);
620
621 gain->offset_valid = valid;
622 }
623
rtw8852c_efuse_copy_sn_uuid_usb(struct rtw89_dev * rtwdev,const struct rtw8852c_efuse * map)624 static void rtw8852c_efuse_copy_sn_uuid_usb(struct rtw89_dev *rtwdev,
625 const struct rtw8852c_efuse *map)
626 {
627 struct rtw89_efuse *efuse = &rtwdev->efuse;
628
629 memcpy(efuse->sn, map->u.sn, sizeof(efuse->sn));
630 memcpy(efuse->uuid, map->u.uuid, sizeof(efuse->uuid));
631 }
632
rtw8852c_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)633 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
634 enum rtw89_efuse_block block)
635 {
636 struct rtw89_efuse *efuse = &rtwdev->efuse;
637 struct rtw8852c_efuse *map;
638
639 map = (struct rtw8852c_efuse *)log_map;
640
641 efuse->country_code[0] = map->country_code[0];
642 efuse->country_code[1] = map->country_code[1];
643 rtw8852c_efuse_parsing_tssi(rtwdev, map);
644 rtw8852c_efuse_parsing_gain_offset(rtwdev, map);
645
646 switch (rtwdev->hci.type) {
647 case RTW89_HCI_TYPE_PCIE:
648 ether_addr_copy(efuse->addr, map->e.mac_addr);
649 break;
650 case RTW89_HCI_TYPE_USB:
651 ether_addr_copy(efuse->addr, map->u.mac_addr);
652 rtw8852c_efuse_copy_sn_uuid_usb(rtwdev, map);
653 break;
654 default:
655 return -ENOTSUPP;
656 }
657
658 efuse->rfe_type = map->rfe_type;
659 efuse->xtal_cap = map->xtal_k;
660
661 return 0;
662 }
663
rtw8852c_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)664 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
665 {
666 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
667 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
668 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
669 u32 addr = rtwdev->chip->phycap_addr;
670 bool pg = false;
671 u32 ofst;
672 u8 i, j;
673
674 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
675 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
676 /* addrs are in decreasing order */
677 ofst = tssi_trim_addr[i] - addr - j;
678 tssi->tssi_trim[i][j] = phycap_map[ofst];
679
680 if (phycap_map[ofst] != 0xff)
681 pg = true;
682 }
683
684 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
685 /* addrs are in decreasing order */
686 ofst = tssi_trim_addr_6g[i] - addr - j;
687 tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
688
689 if (phycap_map[ofst] != 0xff)
690 pg = true;
691 }
692 }
693
694 if (!pg) {
695 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
696 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
697 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
698 "[TSSI][TRIM] no PG, set all trim info to 0\n");
699 }
700
701 for (i = 0; i < RF_PATH_NUM_8852C; i++)
702 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
703 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
704 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
705 i, j, tssi->tssi_trim[i][j],
706 tssi_trim_addr[i] - j);
707 }
708
rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)709 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
710 u8 *phycap_map)
711 {
712 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
713 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
714 u32 addr = rtwdev->chip->phycap_addr;
715 u8 i;
716
717 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
718 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
719
720 rtw89_debug(rtwdev, RTW89_DBG_RFK,
721 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
722 i, info->thermal_trim[i]);
723
724 if (info->thermal_trim[i] != 0xff)
725 info->pg_thermal_trim = true;
726 }
727 }
728
729 #define __THM_MASK_SIGN BIT(0)
730 #define __THM_MASK_3BITS GENMASK(3, 1)
731 #define __THM_MASK_VAL8 BIT(4)
732
rtw8852c_thermal_trim(struct rtw89_dev * rtwdev)733 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
734 {
735 #define __thm_setting(raw) \
736 ({ \
737 u8 __v = (raw); \
738 ((__v & __THM_MASK_SIGN) << 3) | ((__v & __THM_MASK_3BITS) >> 1); \
739 })
740 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
741 u8 i, val;
742
743 if (!info->pg_thermal_trim) {
744 rtw89_debug(rtwdev, RTW89_DBG_RFK,
745 "[THERMAL][TRIM] no PG, do nothing\n");
746
747 return;
748 }
749
750 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
751 val = __thm_setting(info->thermal_trim[i]);
752 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
753
754 rtw89_debug(rtwdev, RTW89_DBG_RFK,
755 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
756 i, val);
757 }
758 #undef __thm_setting
759 }
760
rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)761 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
762 u8 *phycap_map)
763 {
764 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
765 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
766 u32 addr = rtwdev->chip->phycap_addr;
767 u8 i;
768
769 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
770 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
771
772 rtw89_debug(rtwdev, RTW89_DBG_RFK,
773 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
774 i, info->pa_bias_trim[i]);
775
776 if (info->pa_bias_trim[i] != 0xff)
777 info->pg_pa_bias_trim = true;
778 }
779 }
780
rtw8852c_pa_bias_trim(struct rtw89_dev * rtwdev)781 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
782 {
783 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
784 u8 pabias_2g, pabias_5g;
785 u8 i;
786
787 if (!info->pg_pa_bias_trim) {
788 rtw89_debug(rtwdev, RTW89_DBG_RFK,
789 "[PA_BIAS][TRIM] no PG, do nothing\n");
790
791 return;
792 }
793
794 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
795 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
796 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
797
798 rtw89_debug(rtwdev, RTW89_DBG_RFK,
799 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
800 i, pabias_2g, pabias_5g);
801
802 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
803 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
804 }
805 }
806
rtw8852c_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)807 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
808 {
809 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
810 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
811 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
812
813 return 0;
814 }
815
rtw8852c_power_trim(struct rtw89_dev * rtwdev)816 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
817 {
818 rtw8852c_thermal_trim(rtwdev);
819 rtw8852c_pa_bias_trim(rtwdev);
820 }
821
rtw8852c_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)822 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev,
823 const struct rtw89_chan *chan,
824 u8 mac_idx)
825 {
826 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
827 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
828 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
829 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0;
830 u8 rf_mod_val = 0, chk_rate_mask = 0;
831 u32 txsc;
832
833 switch (chan->band_width) {
834 case RTW89_CHANNEL_WIDTH_160:
835 txsc80 = rtw89_phy_get_txsc(rtwdev, chan,
836 RTW89_CHANNEL_WIDTH_80);
837 fallthrough;
838 case RTW89_CHANNEL_WIDTH_80:
839 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
840 RTW89_CHANNEL_WIDTH_40);
841 fallthrough;
842 case RTW89_CHANNEL_WIDTH_40:
843 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
844 RTW89_CHANNEL_WIDTH_20);
845 break;
846 default:
847 break;
848 }
849
850 switch (chan->band_width) {
851 case RTW89_CHANNEL_WIDTH_160:
852 rf_mod_val = AX_WMAC_RFMOD_160M;
853 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
854 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) |
855 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80);
856 break;
857 case RTW89_CHANNEL_WIDTH_80:
858 rf_mod_val = AX_WMAC_RFMOD_80M;
859 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
860 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40);
861 break;
862 case RTW89_CHANNEL_WIDTH_40:
863 rf_mod_val = AX_WMAC_RFMOD_40M;
864 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20);
865 break;
866 case RTW89_CHANNEL_WIDTH_20:
867 default:
868 rf_mod_val = AX_WMAC_RFMOD_20M;
869 txsc = 0;
870 break;
871 }
872 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val);
873 rtw89_write32(rtwdev, sub_carr, txsc);
874
875 switch (chan->band_type) {
876 case RTW89_BAND_2G:
877 chk_rate_mask = B_AX_BAND_MODE;
878 break;
879 case RTW89_BAND_5G:
880 case RTW89_BAND_6G:
881 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
882 break;
883 default:
884 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
885 return;
886 }
887 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN |
888 B_AX_RTS_LIMIT_IN_OFDM6);
889 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
890 }
891
892 static const u32 rtw8852c_sco_barker_threshold[14] = {
893 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
894 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
895 };
896
897 static const u32 rtw8852c_sco_cck_threshold[14] = {
898 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
899 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
900 };
901
rtw8852c_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 central_ch,u8 primary_ch,enum rtw89_bandwidth bw)902 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
903 u8 primary_ch, enum rtw89_bandwidth bw)
904 {
905 u8 ch_element;
906
907 if (bw == RTW89_CHANNEL_WIDTH_20) {
908 ch_element = central_ch - 1;
909 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
910 if (primary_ch == 1)
911 ch_element = central_ch - 1 + 2;
912 else
913 ch_element = central_ch - 1 - 2;
914 } else {
915 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
916 return -EINVAL;
917 }
918 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1,
919 rtw8852c_sco_barker_threshold[ch_element]);
920 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1,
921 rtw8852c_sco_cck_threshold[ch_element]);
922
923 return 0;
924 }
925
926 struct rtw8852c_bb_gain {
927 u32 gain_g[BB_PATH_NUM_8852C];
928 u32 gain_a[BB_PATH_NUM_8852C];
929 u32 gain_mask;
930 };
931
932 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
933 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
934 .gain_mask = 0x00ff0000 },
935 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
936 .gain_mask = 0xff000000 },
937 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
938 .gain_mask = 0x000000ff },
939 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
940 .gain_mask = 0x0000ff00 },
941 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
942 .gain_mask = 0x00ff0000 },
943 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
944 .gain_mask = 0xff000000 },
945 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
946 .gain_mask = 0x000000ff },
947 };
948
949 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
950 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
951 .gain_mask = 0x00ff0000 },
952 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
953 .gain_mask = 0xff000000 },
954 };
955
956 struct rtw8852c_bb_gain_bypass {
957 u32 gain_g[BB_PATH_NUM_8852C];
958 u32 gain_a[BB_PATH_NUM_8852C];
959 u32 gain_mask_g;
960 u32 gain_mask_a;
961 };
962
963 static
964 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = {
965 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78},
966 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
967 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
968 .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
969 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
970 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
971 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
972 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000},
973 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C},
974 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
975 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
976 .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
977 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
978 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
979 };
980
981 struct rtw8852c_bb_gain_op1db {
982 struct {
983 u32 lna[BB_PATH_NUM_8852C];
984 u32 tia_lna[BB_PATH_NUM_8852C];
985 u32 mask;
986 } reg[LNA_GAIN_NUM];
987 u32 reg_tia0_lna6[BB_PATH_NUM_8852C];
988 u32 mask_tia0_lna6;
989 };
990
991 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = {
992 .reg = {
993 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
994 .mask = 0xff},
995 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
996 .mask = 0xff00},
997 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
998 .mask = 0xff0000},
999 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
1000 .mask = 0xff000000},
1001 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
1002 .mask = 0xff},
1003 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
1004 .mask = 0xff00},
1005 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
1006 .mask = 0xff0000},
1007 },
1008 .reg_tia0_lna6 = {0x4674, 0x4758},
1009 .mask_tia0_lna6 = 0xff000000,
1010 };
1011
rtw8852c_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)1012 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
1013 enum rtw89_subband subband,
1014 enum rtw89_rf_path path)
1015 {
1016 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1017 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
1018 s32 val;
1019 u32 reg;
1020 u32 mask;
1021 int i;
1022
1023 for (i = 0; i < LNA_GAIN_NUM; i++) {
1024 if (subband == RTW89_CH_2G)
1025 reg = bb_gain_lna[i].gain_g[path];
1026 else
1027 reg = bb_gain_lna[i].gain_a[path];
1028
1029 mask = bb_gain_lna[i].gain_mask;
1030 val = gain->lna_gain[gain_band][path][i];
1031 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1032
1033 if (subband == RTW89_CH_2G) {
1034 reg = bb_gain_bypass_lna[i].gain_g[path];
1035 mask = bb_gain_bypass_lna[i].gain_mask_g;
1036 } else {
1037 reg = bb_gain_bypass_lna[i].gain_a[path];
1038 mask = bb_gain_bypass_lna[i].gain_mask_a;
1039 }
1040
1041 val = gain->lna_gain_bypass[gain_band][path][i];
1042 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1043
1044 if (subband != RTW89_CH_2G) {
1045 reg = bb_gain_op1db_a.reg[i].lna[path];
1046 mask = bb_gain_op1db_a.reg[i].mask;
1047 val = gain->lna_op1db[gain_band][path][i];
1048 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1049
1050 reg = bb_gain_op1db_a.reg[i].tia_lna[path];
1051 mask = bb_gain_op1db_a.reg[i].mask;
1052 val = gain->tia_lna_op1db[gain_band][path][i];
1053 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1054 }
1055 }
1056
1057 if (subband != RTW89_CH_2G) {
1058 reg = bb_gain_op1db_a.reg_tia0_lna6[path];
1059 mask = bb_gain_op1db_a.mask_tia0_lna6;
1060 val = gain->tia_lna_op1db[gain_band][path][7];
1061 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1062 }
1063
1064 for (i = 0; i < TIA_GAIN_NUM; i++) {
1065 if (subband == RTW89_CH_2G)
1066 reg = bb_gain_tia[i].gain_g[path];
1067 else
1068 reg = bb_gain_tia[i].gain_a[path];
1069
1070 mask = bb_gain_tia[i].gain_mask;
1071 val = gain->tia_gain[gain_band][path][i];
1072 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
1073 }
1074 }
1075
rtw8852c_set_gain_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx,enum rtw89_rf_path path)1076 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
1077 const struct rtw89_chan *chan,
1078 enum rtw89_phy_idx phy_idx,
1079 enum rtw89_rf_path path)
1080 {
1081 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1082 R_PATH1_G_TIA0_LNA6_OP1DB_V1};
1083 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK};
1084 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK};
1085 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
1086 enum rtw89_gain_offset gain_band;
1087 s32 offset_q0, offset_base_q4;
1088 s32 tmp = 0;
1089
1090 if (!efuse_gain->offset_valid)
1091 return;
1092
1093 if (rtwdev->dbcc_en && path == RF_PATH_B)
1094 phy_idx = RTW89_PHY_1;
1095
1096 if (chan->band_type == RTW89_BAND_2G) {
1097 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
1098 offset_base_q4 = efuse_gain->offset_base[phy_idx];
1099
1100 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1),
1101 S8_MIN >> 1, S8_MAX >> 1);
1102 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
1103 }
1104
1105 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
1106
1107 offset_q0 = -efuse_gain->offset[path][gain_band];
1108 offset_base_q4 = efuse_gain->offset_base[phy_idx];
1109
1110 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2);
1111 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX);
1112 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
1113
1114 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX);
1115 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
1116 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
1117 }
1118
rtw8852c_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1119 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev,
1120 const struct rtw89_chan *chan,
1121 enum rtw89_phy_idx phy_idx)
1122 {
1123 u8 sco;
1124 u16 central_freq = chan->freq;
1125 u8 central_ch = chan->channel;
1126 u8 band = chan->band_type;
1127 u8 subband = chan->subband_type;
1128 bool is_2g = band == RTW89_BAND_2G;
1129 u8 chan_idx;
1130
1131 if (!central_freq) {
1132 rtw89_warn(rtwdev, "Invalid central_freq\n");
1133 return;
1134 }
1135
1136 if (phy_idx == RTW89_PHY_0) {
1137 /* Path A */
1138 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A);
1139 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A);
1140
1141 if (is_2g)
1142 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1143 B_PATH0_BAND_SEL_MSK_V1, 1,
1144 phy_idx);
1145 else
1146 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1147 B_PATH0_BAND_SEL_MSK_V1, 0,
1148 phy_idx);
1149 /* Path B */
1150 if (!rtwdev->dbcc_en) {
1151 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1152 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1153
1154 if (is_2g)
1155 rtw89_phy_write32_idx(rtwdev,
1156 R_PATH1_BAND_SEL_V1,
1157 B_PATH1_BAND_SEL_MSK_V1,
1158 1, phy_idx);
1159 else
1160 rtw89_phy_write32_idx(rtwdev,
1161 R_PATH1_BAND_SEL_V1,
1162 B_PATH1_BAND_SEL_MSK_V1,
1163 0, phy_idx);
1164 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1165 } else {
1166 if (is_2g)
1167 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1168 else
1169 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1170 }
1171 /* SCO compensate FC setting */
1172 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1173 central_freq, phy_idx);
1174 /* round_up((1/fc0)*pow(2,18)) */
1175 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1176 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1177 phy_idx);
1178 } else {
1179 /* Path B */
1180 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1181 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1182
1183 if (is_2g)
1184 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1185 B_PATH1_BAND_SEL_MSK_V1,
1186 1, phy_idx);
1187 else
1188 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1189 B_PATH1_BAND_SEL_MSK_V1,
1190 0, phy_idx);
1191 /* SCO compensate FC setting */
1192 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1193 central_freq, phy_idx);
1194 /* round_up((1/fc0)*pow(2,18)) */
1195 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1196 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1197 phy_idx);
1198 }
1199 /* CCK parameters */
1200 if (band == RTW89_BAND_2G) {
1201 if (central_ch == 14) {
1202 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1203 B_PCOEFF01_MSK_V1, 0x3b13ff);
1204 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1205 B_PCOEFF23_MSK_V1, 0x1c42de);
1206 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1207 B_PCOEFF45_MSK_V1, 0xfdb0ad);
1208 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1209 B_PCOEFF67_MSK_V1, 0xf60f6e);
1210 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1211 B_PCOEFF89_MSK_V1, 0xfd8f92);
1212 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1213 B_PCOEFFAB_MSK_V1, 0x2d011);
1214 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1215 B_PCOEFFCD_MSK_V1, 0x1c02c);
1216 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1217 B_PCOEFFEF_MSK_V1, 0xfff00a);
1218 } else {
1219 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1220 B_PCOEFF01_MSK_V1, 0x3d23ff);
1221 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1222 B_PCOEFF23_MSK_V1, 0x29b354);
1223 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1224 B_PCOEFF45_MSK_V1, 0xfc1c8);
1225 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1226 B_PCOEFF67_MSK_V1, 0xfdb053);
1227 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1228 B_PCOEFF89_MSK_V1, 0xf86f9a);
1229 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1230 B_PCOEFFAB_MSK_V1, 0xfaef92);
1231 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1232 B_PCOEFFCD_MSK_V1, 0xfe5fcc);
1233 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1234 B_PCOEFFEF_MSK_V1, 0xffdff5);
1235 }
1236 }
1237
1238 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1239 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1240 }
1241
rtw8852c_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)1242 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1243 {
1244 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
1245 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
1246
1247 switch (bw) {
1248 case RTW89_CHANNEL_WIDTH_5:
1249 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1250 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1251 break;
1252 case RTW89_CHANNEL_WIDTH_10:
1253 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1254 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1255 break;
1256 case RTW89_CHANNEL_WIDTH_20:
1257 case RTW89_CHANNEL_WIDTH_40:
1258 case RTW89_CHANNEL_WIDTH_80:
1259 case RTW89_CHANNEL_WIDTH_160:
1260 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1261 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1262 break;
1263 default:
1264 rtw89_warn(rtwdev, "Fail to set ADC\n");
1265 }
1266 }
1267
rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev * rtwdev,u8 bw,enum rtw89_phy_idx phy_idx)1268 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw,
1269 enum rtw89_phy_idx phy_idx)
1270 {
1271 if (bw == RTW89_CHANNEL_WIDTH_20) {
1272 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx);
1273 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1274 } else {
1275 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx);
1276 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1277 }
1278 }
1279
1280 static void
rtw8852c_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1281 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1282 enum rtw89_phy_idx phy_idx)
1283 {
1284 u8 mod_sbw = 0;
1285
1286 switch (bw) {
1287 case RTW89_CHANNEL_WIDTH_5:
1288 case RTW89_CHANNEL_WIDTH_10:
1289 case RTW89_CHANNEL_WIDTH_20:
1290 if (bw == RTW89_CHANNEL_WIDTH_5)
1291 mod_sbw = 0x1;
1292 else if (bw == RTW89_CHANNEL_WIDTH_10)
1293 mod_sbw = 0x2;
1294 else if (bw == RTW89_CHANNEL_WIDTH_20)
1295 mod_sbw = 0x0;
1296 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1297 phy_idx);
1298 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW,
1299 mod_sbw, phy_idx);
1300 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0,
1301 phy_idx);
1302 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1303 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1304 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1305 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1306 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1307 B_PATH0_BW_SEL_MSK_V1, 0xf);
1308 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1309 B_PATH1_BW_SEL_MSK_V1, 0xf);
1310 break;
1311 case RTW89_CHANNEL_WIDTH_40:
1312 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1313 phy_idx);
1314 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1315 phy_idx);
1316 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1317 pri_ch,
1318 phy_idx);
1319 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1320 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1321 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1322 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1323 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1324 B_PATH0_BW_SEL_MSK_V1, 0xf);
1325 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1326 B_PATH1_BW_SEL_MSK_V1, 0xf);
1327 break;
1328 case RTW89_CHANNEL_WIDTH_80:
1329 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1330 phy_idx);
1331 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1332 phy_idx);
1333 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1334 pri_ch,
1335 phy_idx);
1336 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1337 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2);
1338 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1339 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2);
1340 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1341 B_PATH0_BW_SEL_MSK_V1, 0xd);
1342 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1343 B_PATH1_BW_SEL_MSK_V1, 0xd);
1344 break;
1345 case RTW89_CHANNEL_WIDTH_160:
1346 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3,
1347 phy_idx);
1348 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1349 phy_idx);
1350 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1351 pri_ch,
1352 phy_idx);
1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1354 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1);
1355 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1356 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1);
1357 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1358 B_PATH0_BW_SEL_MSK_V1, 0xb);
1359 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1360 B_PATH1_BW_SEL_MSK_V1, 0xb);
1361 break;
1362 default:
1363 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1364 pri_ch);
1365 }
1366
1367 if (bw == RTW89_CHANNEL_WIDTH_40) {
1368 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1369 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx);
1370 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx);
1371 } else {
1372 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1373 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx);
1374 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx);
1375 }
1376
1377 if (phy_idx == RTW89_PHY_0) {
1378 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A);
1379 if (!rtwdev->dbcc_en)
1380 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1381 } else {
1382 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1383 }
1384
1385 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx);
1386 }
1387
rtw8852c_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1388 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev,
1389 const struct rtw89_chan *chan)
1390 {
1391 u8 center_chan = chan->channel;
1392 u8 bw = chan->band_width;
1393
1394 switch (chan->band_type) {
1395 case RTW89_BAND_2G:
1396 if (bw == RTW89_CHANNEL_WIDTH_20) {
1397 if (center_chan >= 5 && center_chan <= 8)
1398 return 2440;
1399 if (center_chan == 13)
1400 return 2480;
1401 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
1402 if (center_chan >= 3 && center_chan <= 10)
1403 return 2440;
1404 }
1405 break;
1406 case RTW89_BAND_5G:
1407 if (center_chan == 151 || center_chan == 153 ||
1408 center_chan == 155 || center_chan == 163)
1409 return 5760;
1410 break;
1411 case RTW89_BAND_6G:
1412 if (center_chan == 195 || center_chan == 197 ||
1413 center_chan == 199 || center_chan == 207)
1414 return 6920;
1415 break;
1416 default:
1417 break;
1418 }
1419
1420 return 0;
1421 }
1422
1423 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1424 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1425 #define MAX_TONE_NUM 2048
1426
rtw8852c_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1427 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1428 const struct rtw89_chan *chan,
1429 enum rtw89_phy_idx phy_idx)
1430 {
1431 u32 spur_freq;
1432 s32 freq_diff, csi_idx, csi_tone_idx;
1433
1434 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1435 if (spur_freq == 0) {
1436 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx);
1437 return;
1438 }
1439
1440 freq_diff = (spur_freq - chan->freq) * 1000000;
1441 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1442 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1443
1444 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx);
1445 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx);
1446 }
1447
1448 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = {
1449 [RF_PATH_A] = {
1450 .notch1_idx = {0x4C14, 0xFF},
1451 .notch1_frac_idx = {0x4C14, 0xC00},
1452 .notch1_en = {0x4C14, 0x1000},
1453 .notch2_idx = {0x4C20, 0xFF},
1454 .notch2_frac_idx = {0x4C20, 0xC00},
1455 .notch2_en = {0x4C20, 0x1000},
1456 },
1457 [RF_PATH_B] = {
1458 .notch1_idx = {0x4CD8, 0xFF},
1459 .notch1_frac_idx = {0x4CD8, 0xC00},
1460 .notch1_en = {0x4CD8, 0x1000},
1461 .notch2_idx = {0x4CE4, 0xFF},
1462 .notch2_frac_idx = {0x4CE4, 0xC00},
1463 .notch2_en = {0x4CE4, 0x1000},
1464 },
1465 };
1466
rtw8852c_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1467 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1468 const struct rtw89_chan *chan,
1469 enum rtw89_rf_path path)
1470 {
1471 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1472 u32 spur_freq, fc;
1473 s32 freq_diff;
1474 s32 nbi_idx, nbi_tone_idx;
1475 s32 nbi_frac_idx, nbi_frac_tone_idx;
1476 bool notch2_chk = false;
1477
1478 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1479 if (spur_freq == 0) {
1480 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1481 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1482 return;
1483 }
1484
1485 fc = chan->freq;
1486 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1487 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1488 if ((fc > spur_freq &&
1489 chan->channel < chan->primary_channel) ||
1490 (fc < spur_freq &&
1491 chan->channel > chan->primary_channel))
1492 notch2_chk = true;
1493 }
1494
1495 freq_diff = (spur_freq - fc) * 1000000;
1496 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx);
1497
1498 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1499 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1500 } else {
1501 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1502 128 : 256;
1503
1504 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1505 }
1506 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1507
1508 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1509 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1510 nbi->notch2_idx.mask, nbi_tone_idx);
1511 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1512 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1513 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1514 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1);
1515 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1516 } else {
1517 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1518 nbi->notch1_idx.mask, nbi_tone_idx);
1519 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1520 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1521 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1522 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1);
1523 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1524 }
1525 }
1526
rtw8852c_spur_notch(struct rtw89_dev * rtwdev,u32 val,enum rtw89_phy_idx phy_idx)1527 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
1528 enum rtw89_phy_idx phy_idx)
1529 {
1530 u32 notch;
1531 u32 notch2;
1532
1533 if (phy_idx == RTW89_PHY_0) {
1534 notch = R_PATH0_NOTCH;
1535 notch2 = R_PATH0_NOTCH2;
1536 } else {
1537 notch = R_PATH1_NOTCH;
1538 notch2 = R_PATH1_NOTCH2;
1539 }
1540
1541 rtw89_phy_write32_mask(rtwdev, notch,
1542 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val);
1543 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
1544 rtw89_phy_write32_mask(rtwdev, notch2,
1545 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val);
1546 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
1547 }
1548
rtw8852c_spur_elimination(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 pri_ch_idx,enum rtw89_phy_idx phy_idx)1549 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
1550 const struct rtw89_chan *chan,
1551 u8 pri_ch_idx,
1552 enum rtw89_phy_idx phy_idx)
1553 {
1554 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx);
1555
1556 if (phy_idx == RTW89_PHY_0) {
1557 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1558 (pri_ch_idx == RTW89_SC_20_LOWER ||
1559 pri_ch_idx == RTW89_SC_20_UP3X)) {
1560 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
1561 if (!rtwdev->dbcc_en)
1562 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1563 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1564 (pri_ch_idx == RTW89_SC_20_UPPER ||
1565 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1566 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
1567 if (!rtwdev->dbcc_en)
1568 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1569 } else {
1570 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A);
1571 if (!rtwdev->dbcc_en)
1572 rtw8852c_set_nbi_tone_idx(rtwdev, chan,
1573 RF_PATH_B);
1574 }
1575 } else {
1576 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1577 (pri_ch_idx == RTW89_SC_20_LOWER ||
1578 pri_ch_idx == RTW89_SC_20_UP3X)) {
1579 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1580 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1581 (pri_ch_idx == RTW89_SC_20_UPPER ||
1582 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1583 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1584 } else {
1585 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B);
1586 }
1587 }
1588
1589 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X)
1590 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
1591 else
1592 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
1593 }
1594
rtw8852c_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1595 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
1596 const struct rtw89_chan *chan,
1597 enum rtw89_phy_idx phy_idx)
1598 {
1599 u8 pri_ch = chan->pri_ch_idx;
1600 bool mask_5m_low;
1601 bool mask_5m_en;
1602
1603 switch (chan->band_width) {
1604 case RTW89_CHANNEL_WIDTH_40:
1605 mask_5m_en = true;
1606 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1607 break;
1608 case RTW89_CHANNEL_WIDTH_80:
1609 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1610 pri_ch == RTW89_SC_20_LOWEST;
1611 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1612 break;
1613 default:
1614 mask_5m_en = false;
1615 mask_5m_low = false;
1616 break;
1617 }
1618
1619 if (!mask_5m_en) {
1620 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0);
1621 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0);
1622 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT,
1623 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx);
1624 } else {
1625 if (mask_5m_low) {
1626 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1627 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1628 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0);
1629 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1);
1630 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1631 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1632 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0);
1633 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1);
1634 } else {
1635 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1636 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1637 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1);
1638 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0);
1639 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1640 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1641 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1);
1642 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0);
1643 }
1644 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx);
1645 }
1646 }
1647
rtw8852c_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1648 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
1649 enum rtw89_phy_idx phy_idx)
1650 {
1651 /*HW SI reset*/
1652 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1653 0x7);
1654 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1655 0x7);
1656
1657 udelay(1);
1658
1659 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1660 phy_idx);
1661 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1662 phy_idx);
1663 /*HW SI reset*/
1664 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1665 0x0);
1666 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1667 0x0);
1668
1669 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1670 phy_idx);
1671 }
1672
rtw8852c_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)1673 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1674 enum rtw89_phy_idx phy_idx, bool en)
1675 {
1676 if (en) {
1677 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1678 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1679 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1680 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1681 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1682 phy_idx);
1683 if (band == RTW89_BAND_2G)
1684 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
1685 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1686 } else {
1687 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
1688 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1689 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1690 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1691 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1692 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1693 fsleep(1);
1694 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1695 phy_idx);
1696 }
1697 }
1698
rtw8852c_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1699 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
1700 enum rtw89_phy_idx phy_idx)
1701 {
1702 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1703 }
1704
1705 static
rtw8852c_bb_gpio_trsw(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 tx_path_en,u8 trsw_tx,u8 trsw_rx,u8 trsw,u8 trsw_b)1706 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1707 u8 tx_path_en, u8 trsw_tx,
1708 u8 trsw_rx, u8 trsw, u8 trsw_b)
1709 {
1710 static const u32 path_cr_bases[] = {0x5868, 0x7868};
1711 u32 mask_ofst = 16;
1712 u32 cr;
1713 u32 val;
1714
1715 if (path >= ARRAY_SIZE(path_cr_bases))
1716 return;
1717
1718 cr = path_cr_bases[path];
1719
1720 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1721 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b);
1722
1723 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1724 }
1725
1726 enum rtw8852c_rfe_src {
1727 PAPE_RFM,
1728 TRSW_RFM,
1729 LNAON_RFM,
1730 };
1731
1732 static
rtw8852c_bb_gpio_rfm(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,enum rtw8852c_rfe_src src,u8 dis_tx_gnt_wl,u8 active_tx_opt,u8 act_bt_en,u8 rfm_output_val)1733 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1734 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl,
1735 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val)
1736 {
1737 static const u32 path_cr_bases[] = {0x5894, 0x7894};
1738 static const u32 masks[] = {0, 8, 16};
1739 u32 mask, mask_ofst;
1740 u32 cr;
1741 u32 val;
1742
1743 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1744 return;
1745
1746 mask_ofst = masks[src];
1747 cr = path_cr_bases[path];
1748
1749 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) |
1750 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) |
1751 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) |
1752 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val);
1753 mask = 0xff << mask_ofst;
1754
1755 rtw89_phy_write32_mask(rtwdev, cr, mask, val);
1756 }
1757
rtw8852c_bb_gpio_init(struct rtw89_dev * rtwdev)1758 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
1759 {
1760 static const u32 cr_bases[] = {0x5800, 0x7800};
1761 u32 addr;
1762 u8 i;
1763
1764 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) {
1765 addr = cr_bases[i];
1766 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
1767 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
1768 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
1769 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
1770 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
1771 }
1772
1773 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1774 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1775 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1776 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1777
1778 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1779 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1780 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1781 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1782 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1783 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1784 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1785 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1786
1787 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
1788 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
1789 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
1790 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
1791 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
1792 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
1793 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
1794 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
1795
1796 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
1797 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
1798 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
1799
1800 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
1801 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
1802 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
1803 }
1804
rtw8852c_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1805 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1806 enum rtw89_phy_idx phy_idx)
1807 {
1808 u32 addr;
1809
1810 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1811 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1812 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1813 }
1814
rtw8852c_bb_sethw(struct rtw89_dev * rtwdev)1815 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
1816 {
1817 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1818
1819 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
1820 B_DBCC_80P80_SEL_EVM_RPT_EN);
1821 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
1822 B_DBCC_80P80_SEL_EVM_RPT2_EN);
1823
1824 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1825 rtw8852c_bb_gpio_init(rtwdev);
1826
1827 /* read these registers after loading BB parameters */
1828 gain->offset_base[RTW89_PHY_0] =
1829 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK);
1830 gain->offset_base[RTW89_PHY_1] =
1831 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK);
1832 }
1833
rtw8852c_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1834 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
1835 const struct rtw89_chan *chan,
1836 enum rtw89_phy_idx phy_idx)
1837 {
1838 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
1839 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
1840 struct rtw89_hal *hal = &rtwdev->hal;
1841 bool cck_en = chan->band_type == RTW89_BAND_2G;
1842 u8 pri_ch_idx = chan->pri_ch_idx;
1843 u32 mask, reg;
1844 u8 ntx_path;
1845
1846 if (chan->band_type == RTW89_BAND_2G)
1847 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel,
1848 chan->primary_channel,
1849 chan->band_width);
1850
1851 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx);
1852 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1853 if (cck_en) {
1854 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1855 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0);
1856 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1857 B_PD_ARBITER_OFF, 0x0, phy_idx);
1858 } else {
1859 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1860 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1);
1861 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1862 B_PD_ARBITER_OFF, 0x1, phy_idx);
1863 }
1864
1865 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx);
1866 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G,
1867 RTW89_PHY_0);
1868 rtw8852c_5m_mask(rtwdev, chan, phy_idx);
1869
1870 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1871 rtwdev->hal.cv != CHIP_CAV) {
1872 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ,
1873 B_P80_AT_HIGH_FREQ, 0x0, phy_idx);
1874 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx);
1875 if (chan->primary_channel > chan->channel) {
1876 rtw89_phy_write32_mask(rtwdev,
1877 R_P80_AT_HIGH_FREQ_RU_ALLOC,
1878 ru_alloc_msk[phy_idx], 1);
1879 rtw89_write32_mask(rtwdev, reg,
1880 B_P80_AT_HIGH_FREQ_BB_WRP, 1);
1881 } else {
1882 rtw89_phy_write32_mask(rtwdev,
1883 R_P80_AT_HIGH_FREQ_RU_ALLOC,
1884 ru_alloc_msk[phy_idx], 0);
1885 rtw89_write32_mask(rtwdev, reg,
1886 B_P80_AT_HIGH_FREQ_BB_WRP, 0);
1887 }
1888 }
1889
1890 if (chan->band_type == RTW89_BAND_6G &&
1891 chan->band_width == RTW89_CHANNEL_WIDTH_160)
1892 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1893 B_CDD_EVM_CHK_EN, 0, phy_idx);
1894 else
1895 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1896 B_CDD_EVM_CHK_EN, 1, phy_idx);
1897
1898 if (!rtwdev->dbcc_en) {
1899 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1900 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1901 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1902 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1903 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1904 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1905 } else {
1906 if (phy_idx == RTW89_PHY_0) {
1907 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1908 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1909 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1910 } else {
1911 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1912 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1913 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1914 }
1915 }
1916
1917 if (chan->band_type == RTW89_BAND_6G)
1918 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN);
1919 else
1920 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN);
1921
1922 if (hal->antenna_tx)
1923 ntx_path = hal->antenna_tx;
1924 else
1925 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB;
1926
1927 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx);
1928
1929 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1930 }
1931
rtw8852c_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1932 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev,
1933 const struct rtw89_chan *chan,
1934 enum rtw89_mac_idx mac_idx,
1935 enum rtw89_phy_idx phy_idx)
1936 {
1937 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx);
1938 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx);
1939 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx);
1940 }
1941
rtw8852c_dfs_en(struct rtw89_dev * rtwdev,bool en)1942 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en)
1943 {
1944 if (en)
1945 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1946 else
1947 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1948 }
1949
rtw8852c_adc_en(struct rtw89_dev * rtwdev,bool en)1950 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en)
1951 {
1952 if (en)
1953 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1954 0x0);
1955 else
1956 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1957 0xf);
1958 }
1959
rtw8852c_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1960 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1961 struct rtw89_channel_help_params *p,
1962 const struct rtw89_chan *chan,
1963 enum rtw89_mac_idx mac_idx,
1964 enum rtw89_phy_idx phy_idx)
1965 {
1966 if (enter) {
1967 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1968 RTW89_SCH_TX_SEL_ALL);
1969 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1970 rtw8852c_dfs_en(rtwdev, false);
1971 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx, chan);
1972 rtw8852c_adc_en(rtwdev, false);
1973 fsleep(40);
1974 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1975 } else {
1976 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1977 rtw8852c_adc_en(rtwdev, true);
1978 rtw8852c_dfs_en(rtwdev, true);
1979 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx, chan);
1980 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1981 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1982 }
1983 }
1984
rtw8852c_rfk_init(struct rtw89_dev * rtwdev)1985 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
1986 {
1987 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1988
1989 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1990 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1991 memset(rfk_mcc, 0, sizeof(*rfk_mcc));
1992 rtw8852c_lck_init(rtwdev);
1993 rtw8852c_dpk_init(rtwdev);
1994
1995 rtw8852c_rck(rtwdev);
1996 rtw8852c_dack(rtwdev, RTW89_CHANCTX_0);
1997 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);
1998 }
1999
rtw8852c_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2000 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev,
2001 struct rtw89_vif_link *rtwvif_link)
2002 {
2003 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
2004 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
2005
2006 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx);
2007 rtw89_btc_ntfy_conn_rfk(rtwdev, true);
2008
2009 rtw8852c_rx_dck(rtwdev, phy_idx, false);
2010 rtw8852c_iqk(rtwdev, phy_idx, chanctx_idx);
2011 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
2012 rtw8852c_tssi(rtwdev, phy_idx, chanctx_idx);
2013 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
2014 rtw8852c_dpk(rtwdev, phy_idx, chanctx_idx);
2015
2016 rtw89_btc_ntfy_conn_rfk(rtwdev, false);
2017 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);
2018 }
2019
rtw8852c_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2020 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev,
2021 enum rtw89_phy_idx phy_idx,
2022 const struct rtw89_chan *chan)
2023 {
2024 rtw8852c_tssi_scan(rtwdev, phy_idx, chan);
2025 }
2026
rtw8852c_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)2027 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev,
2028 struct rtw89_vif_link *rtwvif_link,
2029 bool start)
2030 {
2031 rtw8852c_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx);
2032 }
2033
rtw8852c_rfk_track(struct rtw89_dev * rtwdev)2034 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev)
2035 {
2036 rtw8852c_dpk_track(rtwdev);
2037 rtw8852c_lck_track(rtwdev);
2038 rtw8852c_rx_dck_track(rtwdev);
2039 }
2040
rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref,u16 pwr_ofst_decrease)2041 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
2042 enum rtw89_phy_idx phy_idx,
2043 s16 ref, u16 pwr_ofst_decrease)
2044 {
2045 u8 base_cw_0db = 0x27;
2046 u16 tssi_16dbm_cw = 0x12c;
2047 s16 pwr_s10_3 = 0;
2048 s16 rf_pwr_cw = 0;
2049 u16 bb_pwr_cw = 0;
2050 u32 pwr_cw = 0;
2051 u32 tssi_ofst_cw = 0;
2052
2053 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease;
2054 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
2055 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
2056 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
2057 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
2058
2059 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) -
2060 pwr_ofst_decrease;
2061 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2062 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
2063 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
2064
2065 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
2066 }
2067
2068 static
rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)2069 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
2070 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
2071 {
2072 s8 pw_ofst_2tx;
2073 s8 val_1t;
2074 s8 val_2t;
2075 u32 reg;
2076 u8 i;
2077
2078 if (pw_ofst < -32 || pw_ofst > 31) {
2079 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
2080 return;
2081 }
2082 val_1t = pw_ofst << 2;
2083 pw_ofst_2tx = max(pw_ofst - 3, -32);
2084 val_2t = pw_ofst_2tx << 2;
2085
2086 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
2087 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
2088
2089 for (i = 0; i < 4; i++) {
2090 /* 1TX */
2091 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
2092 rtw89_write32_mask(rtwdev, reg,
2093 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i),
2094 val_1t);
2095 /* 2TX */
2096 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
2097 rtw89_write32_mask(rtwdev, reg,
2098 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i),
2099 val_2t);
2100 }
2101 }
2102
rtw8852c_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 pwr_ofst)2103 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
2104 enum rtw89_phy_idx phy_idx, s16 pwr_ofst)
2105 {
2106 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800};
2107 u16 ofst_dec[RF_PATH_NUM_8852C];
2108 const u32 mask = 0x7FFFFFF;
2109 const u8 ofst_ofdm = 0x4;
2110 const u8 ofst_cck = 0x8;
2111 s16 ref_ofdm = 0;
2112 s16 ref_cck = 0;
2113 u32 val;
2114 u8 i;
2115
2116 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
2117
2118 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
2119 GENMASK(27, 10), 0x0);
2120
2121 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst);
2122 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0;
2123
2124 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
2125 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
2126 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]);
2127 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx);
2128 }
2129
2130 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
2131 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
2132 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]);
2133 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx);
2134 }
2135 }
2136
rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)2137 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
2138 const struct rtw89_chan *chan,
2139 u8 tx_shape_idx,
2140 enum rtw89_phy_idx phy_idx)
2141 {
2142 #define __DFIR_CFG_MASK 0xffffff
2143 #define __DFIR_CFG_NR 8
2144 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \
2145 static const u32 _prefix ## _ ## _name[] = {_val}; \
2146 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR)
2147 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val)
2148 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val)
2149
2150 __DECL_DFIR_PARAM(flat,
2151 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
2152 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5);
2153 __DECL_DFIR_PARAM(sharp,
2154 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090,
2155 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5);
2156 __DECL_DFIR_PARAM(sharp_14,
2157 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
2158 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A);
2159 __DECL_DFIR_ADDR(filter,
2160 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0,
2161 0x45C4, 0x45C8);
2162 u8 ch = chan->channel;
2163 const u32 *param;
2164 int i;
2165
2166 if (ch > 14) {
2167 rtw89_warn(rtwdev,
2168 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
2169 return;
2170 }
2171
2172 if (ch == 14)
2173 param = param_sharp_14;
2174 else
2175 param = tx_shape_idx == 0 ? param_flat : param_sharp;
2176
2177 for (i = 0; i < __DFIR_CFG_NR; i++) {
2178 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2179 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i],
2180 param[i]);
2181 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK,
2182 param[i], phy_idx);
2183 }
2184
2185 #undef __DECL_DFIR_ADDR
2186 #undef __DECL_DFIR_PARAM
2187 #undef __DECL_DFIR_VAR
2188 #undef __DFIR_CFG_NR
2189 #undef __DFIR_CFG_MASK
2190 }
2191
rtw8852c_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2192 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
2193 const struct rtw89_chan *chan,
2194 enum rtw89_phy_idx phy_idx)
2195 {
2196 u8 band = chan->band_type;
2197 u8 tx_shape_cck = rtw89_get_tx_shape_idx(rtwdev, band, RTW89_RS_CCK);
2198 u8 tx_shape_ofdm = rtw89_get_tx_shape_idx(rtwdev, band, RTW89_RS_OFDM);
2199
2200 if (band == RTW89_BAND_2G)
2201 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
2202
2203 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2204 (enum rtw89_mac_idx)phy_idx,
2205 tx_shape_ofdm);
2206
2207 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN,
2208 B_P0_DAC_COMP_POST_DPD_EN);
2209 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN,
2210 B_P1_DAC_COMP_POST_DPD_EN);
2211 }
2212
rtw8852c_set_txpwr_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2213 static void rtw8852c_set_txpwr_diff(struct rtw89_dev *rtwdev,
2214 const struct rtw89_chan *chan,
2215 enum rtw89_phy_idx phy_idx)
2216 {
2217 s16 pwr_ofst;
2218
2219 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
2220 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst);
2221 }
2222
rtw8852c_set_txpwr_sar_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2223 static void rtw8852c_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
2224 const struct rtw89_chan *chan,
2225 enum rtw89_phy_idx phy_idx)
2226 {
2227 struct rtw89_sar_parm sar_parm = {
2228 .center_freq = chan->freq,
2229 .force_path = true,
2230 };
2231 s16 sar_rf;
2232 s8 sar_mac;
2233
2234 if (phy_idx != RTW89_PHY_0)
2235 return;
2236
2237 sar_parm.path = RF_PATH_A;
2238 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2239 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2240 rtw89_phy_write32_mask(rtwdev, R_TXPWRB, B_TXPWRB_MAX, sar_rf);
2241
2242 sar_parm.path = RF_PATH_B;
2243 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2244 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2245 rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB, B_TXPWRB_MAX, sar_rf);
2246 }
2247
rtw8852c_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2248 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
2249 const struct rtw89_chan *chan,
2250 enum rtw89_phy_idx phy_idx)
2251 {
2252 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2253 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2254 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
2255 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2256 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2257 rtw8852c_set_txpwr_diff(rtwdev, chan, phy_idx);
2258 rtw8852c_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
2259 }
2260
rtw8852c_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2261 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2262 enum rtw89_phy_idx phy_idx)
2263 {
2264 rtw8852c_set_txpwr_ref(rtwdev, phy_idx, 0);
2265 }
2266
2267 static void
rtw8852c_init_tssi_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2268 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2269 {
2270 static const struct rtw89_reg2_def ctrl_ini[] = {
2271 {0xD938, 0x00010100},
2272 {0xD93C, 0x0500D500},
2273 {0xD940, 0x00000500},
2274 {0xD944, 0x00000005},
2275 {0xD94C, 0x00220000},
2276 {0xD950, 0x00030000},
2277 };
2278 u32 addr;
2279 int i;
2280
2281 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4)
2282 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
2283
2284 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++)
2285 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr,
2286 ctrl_ini[i].data);
2287
2288 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2289 (enum rtw89_mac_idx)phy_idx,
2290 RTW89_TSSI_BANDEDGE_FLAT);
2291 }
2292
2293 static int
rtw8852c_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2294 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2295 {
2296 int ret;
2297
2298 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
2299 if (ret)
2300 return ret;
2301
2302 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
2303 if (ret)
2304 return ret;
2305
2306 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
2307 if (ret)
2308 return ret;
2309
2310 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
2311 RTW89_MAC_1 :
2312 RTW89_MAC_0);
2313 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx);
2314
2315 return 0;
2316 }
2317
rtw8852c_bb_cfg_rx_path(struct rtw89_dev * rtwdev,u8 rx_path)2318 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path)
2319 {
2320 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2321 u8 band = chan->band_type;
2322 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
2323 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
2324
2325 if (rtwdev->dbcc_en) {
2326 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1);
2327 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2,
2328 RTW89_PHY_1);
2329
2330 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0,
2331 1);
2332 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1,
2333 1);
2334 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2,
2335 RTW89_PHY_1);
2336 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2,
2337 RTW89_PHY_1);
2338
2339 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2340 B_RXHT_MCS_LIMIT, 0);
2341 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2342 B_RXVHT_MCS_LIMIT, 0);
2343 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2344 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2345 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2346
2347 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT,
2348 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1);
2349 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT,
2350 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1);
2351 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1,
2352 RTW89_PHY_1);
2353 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0,
2354 RTW89_PHY_1);
2355 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0,
2356 RTW89_PHY_1);
2357 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2358 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2359 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2360 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2361 } else {
2362 if (rx_path == RF_PATH_A) {
2363 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2364 B_ANT_RX_SEG0, 1);
2365 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2366 B_ANT_RX_1RCCA_SEG0, 1);
2367 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2368 B_ANT_RX_1RCCA_SEG1, 1);
2369 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2370 B_RXHT_MCS_LIMIT, 0);
2371 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2372 B_RXVHT_MCS_LIMIT, 0);
2373 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2374 0);
2375 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2376 0);
2377 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2378 rst_mask0, 1);
2379 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2380 rst_mask0, 3);
2381 } else if (rx_path == RF_PATH_B) {
2382 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2383 B_ANT_RX_SEG0, 2);
2384 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2385 B_ANT_RX_1RCCA_SEG0, 2);
2386 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2387 B_ANT_RX_1RCCA_SEG1, 2);
2388 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2389 B_RXHT_MCS_LIMIT, 0);
2390 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2391 B_RXVHT_MCS_LIMIT, 0);
2392 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2393 0);
2394 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2395 0);
2396 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2397 rst_mask1, 1);
2398 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2399 rst_mask1, 3);
2400 } else {
2401 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2402 B_ANT_RX_SEG0, 3);
2403 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2404 B_ANT_RX_1RCCA_SEG0, 3);
2405 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2406 B_ANT_RX_1RCCA_SEG1, 3);
2407 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2408 B_RXHT_MCS_LIMIT, 1);
2409 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2410 B_RXVHT_MCS_LIMIT, 1);
2411 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2412 1);
2413 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2414 1);
2415 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G,
2416 RTW89_PHY_0);
2417 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2418 rst_mask0, 1);
2419 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2420 rst_mask0, 3);
2421 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2422 rst_mask1, 1);
2423 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2424 rst_mask1, 3);
2425 }
2426 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2427 }
2428 }
2429
rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev * rtwdev,u8 tx_path,enum rtw89_mac_idx mac_idx)2430 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
2431 enum rtw89_mac_idx mac_idx)
2432 {
2433 struct rtw89_reg2_def path_com[] = {
2434 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL},
2435 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL},
2436 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL},
2437 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL},
2438 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL},
2439 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL},
2440 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL},
2441 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL},
2442 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL},
2443 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL},
2444 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL},
2445 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL},
2446 };
2447 u32 addr;
2448 u32 reg;
2449 u8 cr_size = ARRAY_SIZE(path_com);
2450 u8 i = 0;
2451
2452 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0);
2453 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1);
2454
2455 for (addr = R_AX_MACID_ANT_TABLE;
2456 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) {
2457 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
2458 rtw89_write32(rtwdev, reg, 0);
2459 }
2460
2461 if (tx_path == RF_A) {
2462 path_com[0].data = AX_PATH_COM0_PATHA;
2463 path_com[1].data = AX_PATH_COM1_PATHA;
2464 path_com[2].data = AX_PATH_COM2_PATHA;
2465 path_com[7].data = AX_PATH_COM7_PATHA;
2466 path_com[8].data = AX_PATH_COM8_PATHA;
2467 } else if (tx_path == RF_B) {
2468 path_com[0].data = AX_PATH_COM0_PATHB;
2469 path_com[1].data = AX_PATH_COM1_PATHB;
2470 path_com[2].data = AX_PATH_COM2_PATHB;
2471 path_com[7].data = AX_PATH_COM7_PATHB;
2472 path_com[8].data = AX_PATH_COM8_PATHB;
2473 } else if (tx_path == RF_AB) {
2474 path_com[0].data = AX_PATH_COM0_PATHAB;
2475 path_com[1].data = AX_PATH_COM1_PATHAB;
2476 path_com[2].data = AX_PATH_COM2_PATHAB;
2477 path_com[7].data = AX_PATH_COM7_PATHAB;
2478 path_com[8].data = AX_PATH_COM8_PATHAB;
2479 } else {
2480 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path);
2481 return;
2482 }
2483
2484 for (i = 0; i < cr_size; i++) {
2485 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n",
2486 path_com[i].addr, path_com[i].data);
2487 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx);
2488 rtw89_write32(rtwdev, reg, path_com[i].data);
2489 }
2490 }
2491
rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2492 static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
2493 enum rtw89_phy_idx phy_idx)
2494 {
2495 if (en) {
2496 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2497 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3);
2498 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2499 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3);
2500 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2501 B_PATH0_RXBB_MSK_V1, 0xf);
2502 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2503 B_PATH1_RXBB_MSK_V1, 0xf);
2504 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2505 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
2506 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2507 B_PATH1_G_LNA6_OP1DB_V1, 0x80);
2508 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2509 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
2510 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2511 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80);
2512 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2513 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80);
2514 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2515 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80);
2516 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2517 B_PATH0_BT_BACKOFF_V1, 0x780D1E);
2518 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2519 B_PATH1_BT_BACKOFF_V1, 0x780D1E);
2520 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2521 B_P0_BACKOFF_IBADC_V1, 0x34);
2522 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2523 B_P1_BACKOFF_IBADC_V1, 0x34);
2524 } else {
2525 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2526 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0);
2527 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2528 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0);
2529 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2530 B_PATH0_RXBB_MSK_V1, 0x60);
2531 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2532 B_PATH1_RXBB_MSK_V1, 0x60);
2533 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2534 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
2535 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2536 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2537 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2538 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2539 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2540 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2541 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2542 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2543 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2544 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2545 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2546 B_PATH0_BT_BACKOFF_V1, 0x79E99E);
2547 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2548 B_PATH1_BT_BACKOFF_V1, 0x79E99E);
2549 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2550 B_P0_BACKOFF_IBADC_V1, 0x26);
2551 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2552 B_P1_BACKOFF_IBADC_V1, 0x26);
2553 }
2554 }
2555
rtw8852c_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)2556 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2557 {
2558 struct rtw89_hal *hal = &rtwdev->hal;
2559 u8 nrx_path = RF_PATH_AB;
2560 u8 rx_nss = hal->rx_nss;
2561
2562 if (hal->antenna_rx == RF_A)
2563 nrx_path = RF_PATH_A;
2564 else if (hal->antenna_rx == RF_B)
2565 nrx_path = RF_PATH_B;
2566
2567 if (nrx_path != RF_PATH_AB)
2568 rx_nss = 1;
2569
2570 rtw8852c_bb_cfg_rx_path(rtwdev, nrx_path);
2571
2572 if (rx_nss == 1) {
2573 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2574 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2575 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2576 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2577 } else {
2578 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2579 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2580 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2581 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2582 }
2583 }
2584
rtw8852c_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)2585 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2586 {
2587 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
2588 s8 comp = 0;
2589 u8 val;
2590
2591 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2592 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2593 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2594
2595 fsleep(200);
2596
2597 val = rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2598
2599 if (info->pg_thermal_trim) {
2600 u8 trim = info->thermal_trim[rf_path];
2601
2602 if (trim & __THM_MASK_VAL8)
2603 comp = 8 * (trim & __THM_MASK_SIGN ? -1 : 1);
2604 }
2605
2606 return val + comp;
2607 }
2608
rtw8852c_btc_set_rfe(struct rtw89_dev * rtwdev)2609 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2610 {
2611 struct rtw89_btc_module *md = &rtwdev->btc.mdinfo;
2612
2613 md->rfe_type = rtwdev->efuse.rfe_type;
2614 md->kt_ver = rtwdev->hal.cv;
2615 md->bt_solo = 0;
2616 md->bt0_sw_type = BTC_SWITCH_INTERNAL;
2617
2618 if (md->rfe_type > 0)
2619 md->ant.num = (md->rfe_type % 2 ? 2 : 3);
2620 else
2621 md->ant.num = 2;
2622
2623 md->ant.diversity = 0;
2624 md->ant.isolation = 10;
2625
2626 if (md->ant.num == 3) {
2627 md->ant.type = BTC_ANT_DEDICATED;
2628 md->bt0_pos = BTC_BT_ALONE;
2629 } else {
2630 md->ant.type = BTC_ANT_SHARED;
2631 md->bt0_pos = BTC_BT_BTG;
2632 }
2633 rtwdev->btc.btg_pos = md->ant.btg_pos;
2634 rtwdev->btc.ant_type = md->ant.type;
2635 }
2636
rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2637 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
2638 enum rtw89_phy_idx phy_idx)
2639 {
2640 if (en) {
2641 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2642 B_PATH0_BT_SHARE_V1, 0x1);
2643 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2644 B_PATH0_BTG_PATH_V1, 0x0);
2645 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2646 B_PATH1_G_LNA6_OP1DB_V1, 0x20);
2647 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2648 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
2649 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2650 B_PATH1_BT_SHARE_V1, 0x1);
2651 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2652 B_PATH1_BTG_PATH_V1, 0x1);
2653 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
2654 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1);
2655 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2);
2656 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2657 B_BT_DYN_DC_EST_EN_MSK, 0x1);
2658 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2659 0x1);
2660 } else {
2661 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2662 B_PATH0_BT_SHARE_V1, 0x0);
2663 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2664 B_PATH0_BTG_PATH_V1, 0x0);
2665 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2666 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2667 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2668 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2669 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2670 B_PATH1_BT_SHARE_V1, 0x0);
2671 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2672 B_PATH1_BTG_PATH_V1, 0x0);
2673 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
2674 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
2675 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0);
2676 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0);
2677 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2678 B_BT_DYN_DC_EST_EN_MSK, 0x0);
2679 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2680 0x0);
2681 }
2682 }
2683
2684 static
rtw8852c_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)2685 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2686 {
2687 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2688 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2689 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2690 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2691 }
2692
rtw8852c_btc_init_cfg(struct rtw89_dev * rtwdev)2693 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
2694 {
2695 struct rtw89_btc *btc = &rtwdev->btc;
2696 const struct rtw89_chip_info *chip = rtwdev->chip;
2697 const struct rtw89_mac_ax_coex coex_params = {
2698 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2699 .direction = RTW89_MAC_AX_COEX_INNER,
2700 };
2701
2702 /* PTA init */
2703 rtw89_mac_coex_init_v1(rtwdev, &coex_params);
2704
2705 /* set WL Tx response = Hi-Pri */
2706 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2707 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2708
2709 /* set rf gnt debug off */
2710 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2711 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2712
2713 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
2714 if (btc->ant_type == BTC_ANT_SHARED) {
2715 rtw8852c_set_trx_mask(rtwdev,
2716 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
2717 rtw8852c_set_trx_mask(rtwdev,
2718 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
2719 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2720 rtw8852c_set_trx_mask(rtwdev,
2721 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2722 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
2723 rtw8852c_set_trx_mask(rtwdev,
2724 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
2725 rtw8852c_set_trx_mask(rtwdev,
2726 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
2727 }
2728
2729 /* set PTA break table */
2730 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2731
2732 /* enable BT counter 0xda10[1:0] = 2b'11 */
2733 rtw89_write32_set(rtwdev,
2734 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN |
2735 B_AX_BT_CNT_RST_V1);
2736 }
2737
2738 static
rtw8852c_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)2739 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2740 {
2741 u32 bitmap = 0;
2742 u32 reg = 0;
2743
2744 switch (map) {
2745 case BTC_PRI_MASK_TX_RESP:
2746 reg = R_BTC_COEX_WL_REQ;
2747 bitmap = B_BTC_RSP_ACK_HI;
2748 break;
2749 case BTC_PRI_MASK_BEACON:
2750 reg = R_BTC_COEX_WL_REQ;
2751 bitmap = B_BTC_TX_BCN_HI;
2752 break;
2753 default:
2754 return;
2755 }
2756
2757 if (state)
2758 rtw89_write32_set(rtwdev, reg, bitmap);
2759 else
2760 rtw89_write32_clr(rtwdev, reg, bitmap);
2761 }
2762
2763 union rtw8852c_btc_wl_txpwr_ctrl {
2764 u32 txpwr_val;
2765 struct {
2766 union {
2767 u16 ctrl_all_time;
2768 struct {
2769 s16 data:9;
2770 u16 rsvd:6;
2771 u16 flag:1;
2772 } all_time;
2773 };
2774 union {
2775 u16 ctrl_gnt_bt;
2776 struct {
2777 s16 data:9;
2778 u16 rsvd:7;
2779 } gnt_bt;
2780 };
2781 };
2782 } __packed;
2783
2784 static void
rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2785 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2786 {
2787 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2788 s32 val;
2789
2790 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2791 do { \
2792 u32 _wrt = FIELD_PREP(_msk, _val); \
2793 BUILD_BUG_ON((_msk & _en) != 0); \
2794 if (_cond) \
2795 _wrt |= _en; \
2796 else \
2797 _wrt &= ~_en; \
2798 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2799 _msk | _en, _wrt); \
2800 } while (0)
2801
2802 switch (arg.ctrl_all_time) {
2803 case 0xffff:
2804 val = 0;
2805 break;
2806 default:
2807 val = arg.all_time.data;
2808 break;
2809 }
2810
2811 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2812 val, B_AX_FORCE_PWR_BY_RATE_EN,
2813 arg.ctrl_all_time != 0xffff);
2814
2815 switch (arg.ctrl_gnt_bt) {
2816 case 0xffff:
2817 val = 0;
2818 break;
2819 default:
2820 val = arg.gnt_bt.data;
2821 break;
2822 }
2823
2824 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2825 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2826
2827 #undef __write_ctrl
2828 }
2829
2830 static
rtw8852c_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2831 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2832 {
2833 /* +6 for compensate offset */
2834 return clamp_t(s8, val + 6, -100, 0) + 100;
2835 }
2836
2837 static const struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8852c_rf_ul_v0[] = {
2838 {255, 0, 0, 7}, /* 0 -> original */
2839 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2840 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2841 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2842 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2843 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2844 {6, 1, 0, 7},
2845 {13, 1, 0, 7},
2846 {13, 1, 0, 7}
2847 };
2848
2849 static const struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8852c_rf_dl_v0[] = {
2850 {255, 0, 0, 7}, /* 0 -> original */
2851 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2852 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2853 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2854 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2855 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2856 {255, 1, 0, 7},
2857 {255, 1, 0, 7},
2858 {255, 1, 0, 7}
2859 };
2860
2861 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2862 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
2863
2864 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {
2865 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00),
2866 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04),
2867 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
2868 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
2869 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
2870 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38),
2871 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44),
2872 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48),
2873 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
2874 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
2875 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
2876 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2877 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4),
2878 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778),
2879 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c),
2880 };
2881
2882 static
rtw8852c_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2883 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2884 {
2885 /* Feature move to firmware */
2886 }
2887
2888 static
rtw8852c_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2889 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2890 {
2891 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2892 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2893 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2894
2895 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2896 if (state)
2897 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2898 RFREG_MASK, 0x179c);
2899 else
2900 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2901 RFREG_MASK, 0x208);
2902
2903 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2904 }
2905
rtw8852c_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)2906 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2907 {
2908 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2909 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2910 * To improve BT ACI in co-rx
2911 */
2912
2913 switch (level) {
2914 case 0: /* default */
2915 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2916 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2918 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2919 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2920 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2922 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2923 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2925 break;
2926 case 1: /* Fix LNA2=5 */
2927 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2928 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2929 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2930 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2931 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2932 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2933 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2934 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2935 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2936 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2937 break;
2938 }
2939 }
2940
rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2941 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2942 {
2943 struct rtw89_btc *btc = &rtwdev->btc;
2944
2945 switch (level) {
2946 case 0: /* original */
2947 default:
2948 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2949 btc->dm.wl_lna2 = 0;
2950 break;
2951 case 1: /* for FDD free-run */
2952 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
2953 btc->dm.wl_lna2 = 0;
2954 break;
2955 case 2: /* for BTG Co-Rx*/
2956 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2957 btc->dm.wl_lna2 = 1;
2958 break;
2959 }
2960
2961 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2962 }
2963
rtw8852c_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2964 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2965 struct rtw89_rx_phy_ppdu *phy_ppdu,
2966 struct ieee80211_rx_status *status)
2967 {
2968 u8 chan_idx = phy_ppdu->chan_idx;
2969 enum nl80211_band band;
2970 u8 ch;
2971
2972 if (chan_idx == 0)
2973 return;
2974
2975 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2976 status->freq = ieee80211_channel_to_frequency(ch, band);
2977 status->band = band;
2978 }
2979
rtw8852c_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2980 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev,
2981 struct rtw89_rx_phy_ppdu *phy_ppdu,
2982 struct ieee80211_rx_status *status)
2983 {
2984 u8 path;
2985 u8 *rx_power = phy_ppdu->rssi;
2986
2987 if (!status->signal)
2988 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
2989 rx_power[RF_PATH_B]));
2990
2991 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2992 status->chains |= BIT(path);
2993 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2994 }
2995 if (phy_ppdu->valid)
2996 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2997 }
2998
rtw8852c_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2999 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3000 {
3001 int ret;
3002
3003 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3004 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3005
3006 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
3007 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
3008 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
3009
3010 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
3011 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
3012
3013 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
3014 if (ret)
3015 return ret;
3016
3017 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
3018 if (ret)
3019 return ret;
3020
3021 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
3022 if (ret)
3023 return ret;
3024
3025 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
3026 if (ret)
3027 return ret;
3028
3029 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
3030 if (ret)
3031 return ret;
3032
3033 return 0;
3034 }
3035
rtw8852c_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3036 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3037 {
3038 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
3039 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3040 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3041
3042 return 0;
3043 }
3044
3045 static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = {
3046 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb,
3047 .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb,
3048 };
3049
3050 #ifdef CONFIG_PM
3051 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = {
3052 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
3053 WIPHY_WOWLAN_NET_DETECT,
3054 .n_patterns = RTW89_MAX_PATTERN_NUM,
3055 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
3056 .pattern_min_len = 1,
3057 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
3058 };
3059 #endif
3060
3061 static const struct rtw89_chip_ops rtw8852c_chip_ops = {
3062 .enable_bb_rf = rtw8852c_mac_enable_bb_rf,
3063 .disable_bb_rf = rtw8852c_mac_disable_bb_rf,
3064 .bb_preinit = NULL,
3065 .bb_postinit = NULL,
3066 .bb_reset = rtw8852c_bb_reset,
3067 .bb_sethw = rtw8852c_bb_sethw,
3068 .read_rf = rtw89_phy_read_rf_v1,
3069 .write_rf = rtw89_phy_write_rf_v1,
3070 .set_channel = rtw8852c_set_channel,
3071 .set_channel_help = rtw8852c_set_channel_help,
3072 .read_efuse = rtw8852c_read_efuse,
3073 .read_phycap = rtw8852c_read_phycap,
3074 .fem_setup = NULL,
3075 .data_setup = NULL,
3076 .rfe_gpio = NULL,
3077 .rfk_hw_init = NULL,
3078 .rfk_init = rtw8852c_rfk_init,
3079 .rfk_init_late = NULL,
3080 .rfk_channel = rtw8852c_rfk_channel,
3081 .rfk_band_changed = rtw8852c_rfk_band_changed,
3082 .rfk_scan = rtw8852c_rfk_scan,
3083 .rfk_track = rtw8852c_rfk_track,
3084 .power_trim = rtw8852c_power_trim,
3085 .set_txpwr = rtw8852c_set_txpwr,
3086 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl,
3087 .init_txpwr_unit = rtw8852c_init_txpwr_unit,
3088 .get_thermal = rtw8852c_get_thermal,
3089 .chan_to_rf18_val = NULL,
3090 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx,
3091 .query_ppdu = rtw8852c_query_ppdu,
3092 .convert_rpl_to_rssi = NULL,
3093 .phy_rpt_to_rssi = NULL,
3094 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx,
3095 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path,
3096 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset,
3097 .digital_pwr_comp = NULL,
3098 .calc_rx_gain_normal = NULL,
3099 .path_diff_update = NULL,
3100 .pwr_on_func = rtw8852c_pwr_on_func,
3101 .pwr_off_func = rtw8852c_pwr_off_func,
3102 .query_rxdesc = rtw89_core_query_rxdesc,
3103 .fill_txdesc = rtw89_core_fill_txdesc_v1,
3104 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1,
3105 .get_ch_dma = {rtw89_core_get_ch_dma,
3106 rtw89_core_get_ch_dma_v2,
3107 NULL,},
3108 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1,
3109 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1,
3110 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1,
3111 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
3112 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1,
3113 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
3114 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
3115 .h2c_ampdu_cmac_tbl = NULL,
3116 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
3117 .h2c_punctured_cmac_tbl = NULL,
3118 .h2c_default_dmac_tbl = NULL,
3119 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
3120 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
3121 .h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
3122
3123 .btc_set_rfe = rtw8852c_btc_set_rfe,
3124 .btc_init_cfg = rtw8852c_btc_init_cfg,
3125 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
3126 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
3127 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
3128 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
3129 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
3130 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain,
3131 .btc_set_policy = rtw89_btc_set_policy_v1,
3132 };
3133
3134 const struct rtw89_chip_info rtw8852c_chip_info = {
3135 .chip_id = RTL8852C,
3136 .chip_gen = RTW89_CHIP_AX,
3137 .ops = &rtw8852c_chip_ops,
3138 .mac_def = &rtw89_mac_gen_ax,
3139 .phy_def = &rtw89_phy_gen_ax,
3140 .fw_def = {
3141 .fw_basename = RTW8852C_FW_BASENAME,
3142 .fw_format_max = RTW8852C_FW_FORMAT_MAX,
3143 .fw_b_aid = 0,
3144 },
3145 .try_ce_fw = false,
3146 .bbmcu_nr = 0,
3147 .needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS |
3148 BIT(__RTW89_FW_ELEMENT_ID_INTL_TRANSITION),
3149 .fw_blacklist = &rtw89_fw_blacklist_default,
3150 .fifo_size = 458752,
3151 .small_fifo_size = false,
3152 .dle_scc_rsvd_size = 0,
3153 .max_amsdu_limit = 8000,
3154 .max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
3155 .max_eht_mpdu_cap = 0,
3156 .max_tx_agg_num = 128,
3157 .max_rx_agg_num = 64,
3158 .dis_2g_40m_ul_ofdma = false,
3159 .rsvd_ple_ofst = 0x6f800,
3160 .qta_def = {
3161 .hfc_param_ini = {rtw8852c_hfc_param_ini_pcie,
3162 rtw8852c_hfc_param_ini_usb,
3163 rtw8852c_hfc_param_ini_usb,
3164 NULL},
3165 .dle_mem = {rtw8852c_dle_mem_pcie,
3166 rtw8852c_dle_mem_usb2,
3167 rtw8852c_dle_mem_usb3,
3168 NULL},
3169 },
3170 .wde_qempty_acq_grpnum = 16,
3171 .wde_qempty_mgq_grpsel = 16,
3172 .rf_base_addr = {0xe000, 0xf000},
3173 .thermal_th = {0x32, 0x35},
3174 .pwr_on_seq = NULL,
3175 .pwr_off_seq = NULL,
3176 .bb_table = &rtw89_8852c_phy_bb_table,
3177 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table,
3178 .rf_table = {&rtw89_8852c_phy_radiob_table,
3179 &rtw89_8852c_phy_radioa_table,},
3180 .nctl_table = &rtw89_8852c_phy_nctl_table,
3181 .nctl_post_table = NULL,
3182 .dflt_parms = &rtw89_8852c_dflt_parms,
3183 .rfe_parms_conf = NULL,
3184 .chanctx_listener = &rtw8852c_chanctx_listener,
3185 .txpwr_factor_bb = 3,
3186 .txpwr_factor_rf = 2,
3187 .txpwr_factor_mac = 1,
3188 .dig_table = NULL,
3189 .dig_regs = &rtw8852c_dig_regs,
3190 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table,
3191 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
3192 .support_link_num = 0,
3193 .support_chanctx_num = 2,
3194 .support_rnr = false,
3195 .support_bands = BIT(NL80211_BAND_2GHZ) |
3196 BIT(NL80211_BAND_5GHZ) |
3197 BIT(NL80211_BAND_6GHZ),
3198 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
3199 BIT(NL80211_CHAN_WIDTH_40) |
3200 BIT(NL80211_CHAN_WIDTH_80) |
3201 BIT(NL80211_CHAN_WIDTH_160),
3202 .support_unii4 = true,
3203 .support_ant_gain = true,
3204 .support_tas = true,
3205 .support_sar_by_ant = true,
3206 .support_noise = false,
3207 .support_fw_cmd_ofld = true,
3208 .ul_tb_waveform_ctrl = false,
3209 .ul_tb_pwr_diff = true,
3210 .rx_freq_from_ie = false,
3211 .hw_sec_hdr = true,
3212 .hw_mgmt_tx_encrypt = true,
3213 .hw_tkip_crypto = true,
3214 .hw_mlo_bmc_crypto = false,
3215 .rf_path_num = 2,
3216 .tx_nss = 2,
3217 .rx_nss = 2,
3218 .acam_num = 128,
3219 .bcam_num = 20,
3220 .scam_num = 128,
3221 .bacam_num = 8,
3222 .bacam_dynamic_num = 8,
3223 .bacam_ver = RTW89_BACAM_V0_EXT,
3224 .addrcam_ver = 0,
3225 .ppdu_max_usr = 8,
3226 .sec_ctrl_efuse_size = 4,
3227 .physical_efuse_size = 1216,
3228 .logical_efuse_size = 2048,
3229 .limit_efuse_size = 1280,
3230 .dav_phy_efuse_size = 96,
3231 .dav_log_efuse_size = 16,
3232 .efuse_blocks = NULL,
3233 .phycap_addr = 0x590,
3234 .phycap_size = 0x60,
3235 .para_ver = 0x1,
3236 .wlcx_desired = 0x06000000,
3237 .scbd = 0x1,
3238 .mailbox = 0x1,
3239
3240 .afh_guard_ch = 6,
3241 .fdd_iso_freq = 1000,
3242 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres,
3243 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres,
3244 .rssi_tol = 2,
3245 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg),
3246 .mon_reg = rtw89_btc_8852c_mon_reg,
3247 .rf_para_ulink_v0 = rtw89_btc_8852c_rf_ul_v0,
3248 .rf_para_dlink_v0 = rtw89_btc_8852c_rf_dl_v0,
3249 .rf_para_ulink_num_v0 = ARRAY_SIZE(rtw89_btc_8852c_rf_ul_v0),
3250 .rf_para_dlink_num_v0 = ARRAY_SIZE(rtw89_btc_8852c_rf_dl_v0),
3251 .rf_para_ulink_v9 = NULL,
3252 .rf_para_dlink_v9 = NULL,
3253 .rf_para_ulink_num_v9 = 0,
3254 .rf_para_dlink_num_v9 = 0,
3255 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3256 BIT(RTW89_PS_MODE_CLK_GATED) |
3257 BIT(RTW89_PS_MODE_PWR_GATED),
3258 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) |
3259 BIT(RTW89_PS_MODE_PWR_GATED),
3260 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1,
3261 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1,
3262 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short),
3263 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1),
3264 .txwd_info_size = sizeof(struct rtw89_txwd_info),
3265 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1,
3266 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3267 .h2c_regs = rtw8852c_h2c_regs,
3268 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
3269 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3270 .c2h_regs = rtw8852c_c2h_regs,
3271 .page_regs = &rtw8852c_page_regs,
3272 .wow_reason_reg = rtw8852c_wow_wakeup_regs,
3273 .cfo_src_fd = false,
3274 .cfo_hw_comp = false,
3275 .dcfo_comp = &rtw8852c_dcfo_comp,
3276 .dcfo_comp_sft = 12,
3277 .nhm_report = NULL,
3278 .nhm_th = NULL,
3279 .imr_info = &rtw8852c_imr_info,
3280 .imr_dmac_table = NULL,
3281 .imr_cmac_table = NULL,
3282 .rrsr_cfgs = &rtw8852c_rrsr_cfgs,
3283 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
3284 .bss_clr_map_reg = R_BSS_CLR_MAP,
3285 .rfkill_init = &rtw8852c_rfkill_regs,
3286 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
3287 .btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
3288 .dma_ch_mask = 0,
3289 .edcca_regs = &rtw8852c_edcca_regs,
3290 .pmac_regs = &rtw8852c_pmac_regs,
3291 #ifdef CONFIG_PM
3292 .wowlan_stub = &rtw_wowlan_stub_8852c,
3293 #endif
3294 .xtal_info = NULL,
3295 .default_quirks = 0,
3296 .txtime_limit_2ghz = 0,
3297 };
3298 EXPORT_SYMBOL(rtw8852c_chip_info);
3299
3300 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE);
3301 MODULE_AUTHOR("Realtek Corporation");
3302 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver");
3303 MODULE_LICENSE("Dual BSD/GPL");
3304