1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Support Intel uncore PerfMon discovery mechanism. 4 * Copyright(c) 2021 Intel Corporation. 5 */ 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <asm/msr.h> 9 #include "uncore.h" 10 #include "uncore_discovery.h" 11 12 static struct rb_root discovery_tables = RB_ROOT; 13 static int num_discovered_types[UNCORE_ACCESS_MAX]; 14 15 static int logical_die_id; 16 17 static int get_device_die_id(struct pci_dev *dev) 18 { 19 int node = pcibus_to_node(dev->bus); 20 21 /* 22 * If the NUMA info is not available, assume that the logical die id is 23 * continuous in the order in which the discovery table devices are 24 * detected. 25 */ 26 if (node < 0) 27 return logical_die_id++; 28 29 return uncore_device_to_die(dev); 30 } 31 32 #define __node_2_type(cur) \ 33 rb_entry((cur), struct intel_uncore_discovery_type, node) 34 35 static inline int __type_cmp(const void *key, const struct rb_node *b) 36 { 37 const struct intel_uncore_discovery_type *type_b = __node_2_type(b); 38 const u16 *type_id = key; 39 40 if (type_b->type > *type_id) 41 return -1; 42 else if (type_b->type < *type_id) 43 return 1; 44 45 return 0; 46 } 47 48 static inline struct intel_uncore_discovery_type * 49 search_uncore_discovery_type(u16 type_id) 50 { 51 struct rb_node *node = rb_find(&type_id, &discovery_tables, __type_cmp); 52 53 return (node) ? __node_2_type(node) : NULL; 54 } 55 56 static inline bool __type_less(struct rb_node *a, const struct rb_node *b) 57 { 58 return (__node_2_type(a)->type < __node_2_type(b)->type); 59 } 60 61 static struct intel_uncore_discovery_type * 62 add_uncore_discovery_type(struct uncore_unit_discovery *unit) 63 { 64 struct intel_uncore_discovery_type *type; 65 66 if (unit->access_type >= UNCORE_ACCESS_MAX) { 67 pr_warn("Unsupported access type %d\n", unit->access_type); 68 return NULL; 69 } 70 71 type = kzalloc_obj(struct intel_uncore_discovery_type); 72 if (!type) 73 return NULL; 74 75 type->units = RB_ROOT; 76 77 type->access_type = unit->access_type; 78 num_discovered_types[type->access_type]++; 79 type->type = unit->box_type; 80 81 rb_add(&type->node, &discovery_tables, __type_less); 82 83 return type; 84 } 85 86 static struct intel_uncore_discovery_type * 87 get_uncore_discovery_type(struct uncore_unit_discovery *unit) 88 { 89 struct intel_uncore_discovery_type *type; 90 91 type = search_uncore_discovery_type(unit->box_type); 92 if (type) 93 return type; 94 95 return add_uncore_discovery_type(unit); 96 } 97 98 static inline int pmu_idx_cmp(const void *key, const struct rb_node *b) 99 { 100 const struct intel_uncore_discovery_unit *unit; 101 const unsigned int *id = key; 102 103 unit = rb_entry(b, struct intel_uncore_discovery_unit, node); 104 105 if (unit->pmu_idx > *id) 106 return -1; 107 else if (unit->pmu_idx < *id) 108 return 1; 109 110 return 0; 111 } 112 113 static struct intel_uncore_discovery_unit * 114 intel_uncore_find_discovery_unit(struct rb_root *units, int die, 115 unsigned int pmu_idx) 116 { 117 struct intel_uncore_discovery_unit *unit; 118 struct rb_node *pos; 119 120 if (!units) 121 return NULL; 122 123 pos = rb_find_first(&pmu_idx, units, pmu_idx_cmp); 124 if (!pos) 125 return NULL; 126 unit = rb_entry(pos, struct intel_uncore_discovery_unit, node); 127 128 if (die < 0) 129 return unit; 130 131 for (; pos; pos = rb_next(pos)) { 132 unit = rb_entry(pos, struct intel_uncore_discovery_unit, node); 133 134 if (unit->pmu_idx != pmu_idx) 135 break; 136 137 if (unit->die == die) 138 return unit; 139 } 140 141 return NULL; 142 } 143 144 int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die, 145 unsigned int pmu_idx) 146 { 147 struct intel_uncore_discovery_unit *unit; 148 149 unit = intel_uncore_find_discovery_unit(units, die, pmu_idx); 150 if (unit) 151 return unit->id; 152 153 return -1; 154 } 155 156 static inline bool unit_less(struct rb_node *a, const struct rb_node *b) 157 { 158 const struct intel_uncore_discovery_unit *a_node, *b_node; 159 160 a_node = rb_entry(a, struct intel_uncore_discovery_unit, node); 161 b_node = rb_entry(b, struct intel_uncore_discovery_unit, node); 162 163 if (a_node->pmu_idx < b_node->pmu_idx) 164 return true; 165 if (a_node->pmu_idx > b_node->pmu_idx) 166 return false; 167 168 if (a_node->die < b_node->die) 169 return true; 170 if (a_node->die > b_node->die) 171 return false; 172 173 return 0; 174 } 175 176 static inline struct intel_uncore_discovery_unit * 177 uncore_find_unit(struct rb_root *root, unsigned int id) 178 { 179 struct intel_uncore_discovery_unit *unit; 180 struct rb_node *node; 181 182 for (node = rb_first(root); node; node = rb_next(node)) { 183 unit = rb_entry(node, struct intel_uncore_discovery_unit, node); 184 if (unit->id == id) 185 return unit; 186 } 187 188 return NULL; 189 } 190 191 void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, 192 struct rb_root *root, u16 *num_units) 193 { 194 struct intel_uncore_discovery_unit *unit = uncore_find_unit(root, node->id); 195 196 if (unit) 197 node->pmu_idx = unit->pmu_idx; 198 else if (num_units) 199 node->pmu_idx = (*num_units)++; 200 201 rb_add(&node->node, root, unit_less); 202 } 203 204 static void 205 uncore_insert_box_info(struct uncore_unit_discovery *unit, 206 int die) 207 { 208 struct intel_uncore_discovery_unit *node; 209 struct intel_uncore_discovery_type *type; 210 211 if (!unit->ctl || !unit->ctl_offset || !unit->ctr_offset) { 212 pr_info("Invalid address is detected for uncore type %d box %d, " 213 "Disable the uncore unit.\n", 214 unit->box_type, unit->box_id); 215 return; 216 } 217 218 node = kzalloc_obj(*node); 219 if (!node) 220 return; 221 222 node->die = die; 223 node->id = unit->box_id; 224 node->addr = unit->ctl; 225 226 type = get_uncore_discovery_type(unit); 227 if (!type) { 228 kfree(node); 229 return; 230 } 231 232 uncore_find_add_unit(node, &type->units, &type->num_units); 233 234 /* Store generic information for the first box */ 235 if (type->num_units == 1) { 236 type->num_counters = unit->num_regs; 237 type->counter_width = unit->bit_width; 238 type->ctl_offset = unit->ctl_offset; 239 type->ctr_offset = unit->ctr_offset; 240 } 241 } 242 243 static bool 244 uncore_ignore_unit(struct uncore_unit_discovery *unit, 245 struct uncore_discovery_domain *domain) 246 { 247 int i; 248 249 if (!domain || !domain->units_ignore) 250 return false; 251 252 for (i = 0; domain->units_ignore[i] != UNCORE_IGNORE_END ; i++) { 253 if (unit->box_type == domain->units_ignore[i]) 254 return true; 255 } 256 257 return false; 258 } 259 260 static int __parse_discovery_table(struct uncore_discovery_domain *domain, 261 resource_size_t addr, int die, bool *parsed) 262 { 263 struct uncore_global_discovery global; 264 struct uncore_unit_discovery unit; 265 void __iomem *io_addr; 266 unsigned long size; 267 int ret = 0; 268 int i; 269 270 size = UNCORE_DISCOVERY_GLOBAL_MAP_SIZE; 271 io_addr = ioremap(addr, size); 272 if (!io_addr) 273 return -ENOMEM; 274 275 /* Read Global Discovery State */ 276 memcpy_fromio(&global, io_addr, sizeof(struct uncore_global_discovery)); 277 iounmap(io_addr); 278 279 if (uncore_discovery_invalid_unit(global)) { 280 pr_info("Invalid Global Discovery State: 0x%llx 0x%llx 0x%llx\n", 281 global.table1, global.ctl, global.table3); 282 return -EINVAL; 283 } 284 285 size = (1 + global.max_units) * global.stride * 8; 286 io_addr = ioremap(addr, size); 287 if (!io_addr) 288 return -ENOMEM; 289 290 if (domain->global_init && domain->global_init(die, global.ctl)) { 291 ret = -ENODEV; 292 goto out; 293 } 294 295 /* Parsing Unit Discovery State */ 296 for (i = 0; i < global.max_units; i++) { 297 memcpy_fromio(&unit, io_addr + (i + 1) * (global.stride * 8), 298 sizeof(struct uncore_unit_discovery)); 299 300 if (uncore_discovery_invalid_unit(unit)) 301 continue; 302 303 if (unit.access_type >= UNCORE_ACCESS_MAX) 304 continue; 305 306 if (uncore_ignore_unit(&unit, domain)) 307 continue; 308 309 uncore_insert_box_info(&unit, die); 310 } 311 312 *parsed = true; 313 314 out: 315 iounmap(io_addr); 316 return ret; 317 } 318 319 static int parse_discovery_table(struct uncore_discovery_domain *domain, 320 struct pci_dev *dev, int die, 321 u32 bar_offset, bool *parsed) 322 { 323 resource_size_t addr; 324 u32 val; 325 326 pci_read_config_dword(dev, bar_offset, &val); 327 328 if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64) 329 return -EINVAL; 330 331 addr = (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK); 332 #ifdef CONFIG_PHYS_ADDR_T_64BIT 333 if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) { 334 u32 val2; 335 336 pci_read_config_dword(dev, bar_offset + 4, &val2); 337 addr |= ((resource_size_t)val2) << 32; 338 } 339 #endif 340 341 return __parse_discovery_table(domain, addr, die, parsed); 342 } 343 344 static bool uncore_discovery_pci(struct uncore_discovery_domain *domain) 345 { 346 u32 device, val, entry_id, bar_offset; 347 int die, dvsec = 0, ret = true; 348 struct pci_dev *dev = NULL; 349 bool parsed = false; 350 351 device = domain->discovery_base; 352 353 /* 354 * Start a new search and iterates through the list of 355 * the discovery table devices. 356 */ 357 while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) { 358 while ((dvsec = pci_find_next_ext_capability(dev, dvsec, UNCORE_EXT_CAP_ID_DISCOVERY))) { 359 pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC_OFFSET, &val); 360 entry_id = val & UNCORE_DISCOVERY_DVSEC_ID_MASK; 361 if (entry_id != UNCORE_DISCOVERY_DVSEC_ID_PMON) 362 continue; 363 364 pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC2_OFFSET, &val); 365 366 if (val & ~UNCORE_DISCOVERY_DVSEC2_BIR_MASK) { 367 ret = false; 368 goto err; 369 } 370 bar_offset = UNCORE_DISCOVERY_BIR_BASE + 371 (val & UNCORE_DISCOVERY_DVSEC2_BIR_MASK) * UNCORE_DISCOVERY_BIR_STEP; 372 373 die = get_device_die_id(dev); 374 if ((die < 0) || (die >= uncore_max_dies())) 375 continue; 376 377 parse_discovery_table(domain, dev, die, bar_offset, &parsed); 378 } 379 } 380 381 /* None of the discovery tables are available */ 382 if (!parsed) 383 ret = false; 384 err: 385 pci_dev_put(dev); 386 387 return ret; 388 } 389 390 static bool uncore_discovery_msr(struct uncore_discovery_domain *domain) 391 { 392 unsigned long *die_mask; 393 bool parsed = false; 394 int cpu, die; 395 u64 base; 396 397 die_mask = kcalloc(BITS_TO_LONGS(uncore_max_dies()), 398 sizeof(unsigned long), GFP_KERNEL); 399 if (!die_mask) 400 return false; 401 402 for_each_online_cpu(cpu) { 403 die = topology_logical_die_id(cpu); 404 if (__test_and_set_bit(die, die_mask)) 405 continue; 406 407 if (rdmsrq_safe_on_cpu(cpu, domain->discovery_base, &base)) 408 continue; 409 410 if (!base) 411 continue; 412 413 __parse_discovery_table(domain, base, die, &parsed); 414 } 415 416 kfree(die_mask); 417 return parsed; 418 } 419 420 bool uncore_discovery(struct uncore_plat_init *init) 421 { 422 struct uncore_discovery_domain *domain; 423 bool ret = false; 424 int i; 425 426 for (i = 0; i < UNCORE_DISCOVERY_DOMAINS; i++) { 427 domain = &init->domain[i]; 428 if (domain->discovery_base) { 429 cpus_read_lock(); 430 431 if (!domain->base_is_pci) 432 ret |= uncore_discovery_msr(domain); 433 else 434 ret |= uncore_discovery_pci(domain); 435 436 cpus_read_unlock(); 437 } 438 } 439 440 return ret; 441 } 442 443 void intel_uncore_clear_discovery_tables(void) 444 { 445 struct intel_uncore_discovery_type *type, *next; 446 struct intel_uncore_discovery_unit *pos; 447 struct rb_node *node; 448 449 rbtree_postorder_for_each_entry_safe(type, next, &discovery_tables, node) { 450 while (!RB_EMPTY_ROOT(&type->units)) { 451 node = rb_first(&type->units); 452 pos = rb_entry(node, struct intel_uncore_discovery_unit, node); 453 rb_erase(node, &type->units); 454 kfree(pos); 455 } 456 kfree(type); 457 } 458 } 459 460 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 461 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 462 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 463 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 464 DEFINE_UNCORE_FORMAT_ATTR(thresh, thresh, "config:24-31"); 465 466 static struct attribute *generic_uncore_formats_attr[] = { 467 &format_attr_event.attr, 468 &format_attr_umask.attr, 469 &format_attr_edge.attr, 470 &format_attr_inv.attr, 471 &format_attr_thresh.attr, 472 NULL, 473 }; 474 475 static const struct attribute_group generic_uncore_format_group = { 476 .name = "format", 477 .attrs = generic_uncore_formats_attr, 478 }; 479 480 static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box) 481 { 482 struct intel_uncore_discovery_unit *unit; 483 484 unit = intel_uncore_find_discovery_unit(box->pmu->type->boxes, 485 box->dieid, box->pmu->pmu_idx); 486 if (!unit) 487 return 0; 488 489 return unit->addr; 490 } 491 492 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) 493 { 494 u64 box_ctl = intel_generic_uncore_box_ctl(box); 495 496 if (!box_ctl) 497 return; 498 499 wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT); 500 } 501 502 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) 503 { 504 u64 box_ctl = intel_generic_uncore_box_ctl(box); 505 506 if (box_ctl) 507 wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_FRZ); 508 } 509 510 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) 511 { 512 u64 box_ctl = intel_generic_uncore_box_ctl(box); 513 514 if (box_ctl) 515 wrmsrq(box_ctl, 0); 516 } 517 518 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box, 519 struct perf_event *event) 520 { 521 struct hw_perf_event *hwc = &event->hw; 522 523 wrmsrq(hwc->config_base, hwc->config); 524 } 525 526 static void intel_generic_uncore_msr_disable_event(struct intel_uncore_box *box, 527 struct perf_event *event) 528 { 529 struct hw_perf_event *hwc = &event->hw; 530 531 wrmsrq(hwc->config_base, 0); 532 } 533 534 static struct intel_uncore_ops generic_uncore_msr_ops = { 535 .init_box = intel_generic_uncore_msr_init_box, 536 .disable_box = intel_generic_uncore_msr_disable_box, 537 .enable_box = intel_generic_uncore_msr_enable_box, 538 .disable_event = intel_generic_uncore_msr_disable_event, 539 .enable_event = intel_generic_uncore_msr_enable_event, 540 .read_counter = uncore_msr_read_counter, 541 }; 542 543 bool intel_generic_uncore_assign_hw_event(struct perf_event *event, 544 struct intel_uncore_box *box) 545 { 546 struct hw_perf_event *hwc = &event->hw; 547 u64 box_ctl; 548 549 if (!box->pmu->type->boxes) 550 return false; 551 552 if (box->io_addr) { 553 hwc->config_base = uncore_pci_event_ctl(box, hwc->idx); 554 hwc->event_base = uncore_pci_perf_ctr(box, hwc->idx); 555 return true; 556 } 557 558 box_ctl = intel_generic_uncore_box_ctl(box); 559 if (!box_ctl) 560 return false; 561 562 if (box->pci_dev) { 563 box_ctl = UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl); 564 565 hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx); 566 hwc->event_base = box_ctl + uncore_pci_perf_ctr(box, hwc->idx); 567 return true; 568 } 569 570 hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx; 571 hwc->event_base = box_ctl + box->pmu->type->perf_ctr + hwc->idx; 572 573 return true; 574 } 575 576 static inline int intel_pci_uncore_box_ctl(struct intel_uncore_box *box) 577 { 578 return UNCORE_DISCOVERY_PCI_BOX_CTRL(intel_generic_uncore_box_ctl(box)); 579 } 580 581 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) 582 { 583 int box_ctl = intel_pci_uncore_box_ctl(box); 584 585 if (!box_ctl) 586 return; 587 588 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 589 pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT); 590 } 591 592 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box) 593 { 594 int box_ctl = intel_pci_uncore_box_ctl(box); 595 596 if (box_ctl) 597 pci_write_config_dword(box->pci_dev, box_ctl, 598 GENERIC_PMON_BOX_CTL_FRZ); 599 } 600 601 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box) 602 { 603 int box_ctl = intel_pci_uncore_box_ctl(box); 604 605 if (box_ctl) 606 pci_write_config_dword(box->pci_dev, box_ctl, 0); 607 } 608 609 static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box, 610 struct perf_event *event) 611 { 612 struct pci_dev *pdev = box->pci_dev; 613 struct hw_perf_event *hwc = &event->hw; 614 615 pci_write_config_dword(pdev, hwc->config_base, hwc->config); 616 } 617 618 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box, 619 struct perf_event *event) 620 { 621 struct pci_dev *pdev = box->pci_dev; 622 struct hw_perf_event *hwc = &event->hw; 623 624 pci_write_config_dword(pdev, hwc->config_base, 0); 625 } 626 627 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box, 628 struct perf_event *event) 629 { 630 struct pci_dev *pdev = box->pci_dev; 631 struct hw_perf_event *hwc = &event->hw; 632 u64 count = 0; 633 634 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 635 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); 636 637 return count; 638 } 639 640 static struct intel_uncore_ops generic_uncore_pci_ops = { 641 .init_box = intel_generic_uncore_pci_init_box, 642 .disable_box = intel_generic_uncore_pci_disable_box, 643 .enable_box = intel_generic_uncore_pci_enable_box, 644 .disable_event = intel_generic_uncore_pci_disable_event, 645 .enable_event = intel_generic_uncore_pci_enable_event, 646 .read_counter = intel_generic_uncore_pci_read_counter, 647 }; 648 649 #define UNCORE_GENERIC_MMIO_SIZE 0x4000 650 651 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box) 652 { 653 static struct intel_uncore_discovery_unit *unit; 654 struct intel_uncore_type *type = box->pmu->type; 655 resource_size_t addr; 656 657 unit = intel_uncore_find_discovery_unit(type->boxes, box->dieid, box->pmu->pmu_idx); 658 if (!unit) { 659 pr_warn("Uncore type %d id %d: Cannot find box control address.\n", 660 type->type_id, box->pmu->pmu_idx); 661 return; 662 } 663 664 if (!unit->addr) { 665 pr_warn("Uncore type %d box %d: Invalid box control address.\n", 666 type->type_id, unit->id); 667 return; 668 } 669 670 addr = unit->addr; 671 box->io_addr = ioremap(addr, type->mmio_map_size); 672 if (!box->io_addr) { 673 pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n", 674 type->type_id, unit->id, (unsigned long long)addr); 675 return; 676 } 677 678 writel(GENERIC_PMON_BOX_CTL_INT, box->io_addr); 679 } 680 681 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box) 682 { 683 if (!box->io_addr) 684 return; 685 686 writel(GENERIC_PMON_BOX_CTL_FRZ, box->io_addr); 687 } 688 689 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box) 690 { 691 if (!box->io_addr) 692 return; 693 694 writel(0, box->io_addr); 695 } 696 697 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box, 698 struct perf_event *event) 699 { 700 struct hw_perf_event *hwc = &event->hw; 701 702 if (!box->io_addr) 703 return; 704 705 writel(hwc->config, box->io_addr + hwc->config_base); 706 } 707 708 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box, 709 struct perf_event *event) 710 { 711 struct hw_perf_event *hwc = &event->hw; 712 713 if (!box->io_addr) 714 return; 715 716 writel(0, box->io_addr + hwc->config_base); 717 } 718 719 static struct intel_uncore_ops generic_uncore_mmio_ops = { 720 .init_box = intel_generic_uncore_mmio_init_box, 721 .exit_box = uncore_mmio_exit_box, 722 .disable_box = intel_generic_uncore_mmio_disable_box, 723 .enable_box = intel_generic_uncore_mmio_enable_box, 724 .disable_event = intel_generic_uncore_mmio_disable_event, 725 .enable_event = intel_generic_uncore_mmio_enable_event, 726 .read_counter = uncore_mmio_read_counter, 727 }; 728 729 static bool uncore_update_uncore_type(enum uncore_access_type type_id, 730 struct intel_uncore_type *uncore, 731 struct intel_uncore_discovery_type *type) 732 { 733 uncore->type_id = type->type; 734 uncore->num_counters = type->num_counters; 735 uncore->perf_ctr_bits = type->counter_width; 736 uncore->perf_ctr = (unsigned int)type->ctr_offset; 737 uncore->event_ctl = (unsigned int)type->ctl_offset; 738 uncore->boxes = &type->units; 739 uncore->num_boxes = type->num_units; 740 741 switch (type_id) { 742 case UNCORE_ACCESS_MSR: 743 uncore->ops = &generic_uncore_msr_ops; 744 break; 745 case UNCORE_ACCESS_PCI: 746 uncore->ops = &generic_uncore_pci_ops; 747 break; 748 case UNCORE_ACCESS_MMIO: 749 uncore->ops = &generic_uncore_mmio_ops; 750 uncore->mmio_map_size = UNCORE_GENERIC_MMIO_SIZE; 751 break; 752 default: 753 return false; 754 } 755 756 return true; 757 } 758 759 struct intel_uncore_type ** 760 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra) 761 { 762 struct intel_uncore_discovery_type *type; 763 struct intel_uncore_type **uncores; 764 struct intel_uncore_type *uncore; 765 struct rb_node *node; 766 int i = 0; 767 768 uncores = kzalloc_objs(struct intel_uncore_type *, 769 num_discovered_types[type_id] + num_extra + 1); 770 if (!uncores) 771 return empty_uncore; 772 773 for (node = rb_first(&discovery_tables); node; node = rb_next(node)) { 774 type = rb_entry(node, struct intel_uncore_discovery_type, node); 775 if (type->access_type != type_id) 776 continue; 777 778 uncore = kzalloc_obj(struct intel_uncore_type); 779 if (!uncore) 780 break; 781 782 uncore->event_mask = GENERIC_PMON_RAW_EVENT_MASK; 783 uncore->format_group = &generic_uncore_format_group; 784 785 if (!uncore_update_uncore_type(type_id, uncore, type)) { 786 kfree(uncore); 787 continue; 788 } 789 uncores[i++] = uncore; 790 } 791 792 return uncores; 793 } 794 795 void intel_uncore_generic_uncore_cpu_init(void) 796 { 797 uncore_msr_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_MSR, 0); 798 } 799 800 int intel_uncore_generic_uncore_pci_init(void) 801 { 802 uncore_pci_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_PCI, 0); 803 804 return 0; 805 } 806 807 void intel_uncore_generic_uncore_mmio_init(void) 808 { 809 uncore_mmio_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_MMIO, 0); 810 } 811