1 /*
2 * P2WI (Push-Pull Two Wire Interface) bus driver.
3 *
4 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 *
10 * The P2WI controller looks like an SMBus controller which only supports byte
11 * data transfers. But, it differs from standard SMBus protocol on several
12 * aspects:
13 * - it supports only one target device, and thus drop the address field
14 * - it adds a parity bit every 8bits of data
15 * - only one read access is required to read a byte (instead of a write
16 * followed by a read access in standard SMBus protocol)
17 * - there's no Ack bit after each byte transfer
18 *
19 * This means this bus cannot be used to interface with standard SMBus
20 * devices (the only known device to support this interface is the AXP221
21 * PMIC).
22 *
23 */
24 #include <linux/clk.h>
25 #include <linux/i2c.h>
26 #include <linux/io.h>
27 #include <linux/interrupt.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
32
33
34 /* P2WI registers */
35 #define P2WI_CTRL 0x0
36 #define P2WI_CCR 0x4
37 #define P2WI_INTE 0x8
38 #define P2WI_INTS 0xc
39 #define P2WI_DADDR0 0x10
40 #define P2WI_DADDR1 0x14
41 #define P2WI_DLEN 0x18
42 #define P2WI_DATA0 0x1c
43 #define P2WI_DATA1 0x20
44 #define P2WI_LCR 0x24
45 #define P2WI_PMCR 0x28
46
47 /* CTRL fields */
48 #define P2WI_CTRL_START_TRANS BIT(7)
49 #define P2WI_CTRL_ABORT_TRANS BIT(6)
50 #define P2WI_CTRL_GLOBAL_INT_ENB BIT(1)
51 #define P2WI_CTRL_SOFT_RST BIT(0)
52
53 /* CLK CTRL fields */
54 #define P2WI_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
55 #define P2WI_CCR_MAX_CLK_DIV 0xff
56 #define P2WI_CCR_CLK_DIV(v) ((v) & P2WI_CCR_MAX_CLK_DIV)
57
58 /* STATUS fields */
59 #define P2WI_INTS_TRANS_ERR_ID(v) (((v) >> 8) & 0xff)
60 #define P2WI_INTS_LOAD_BSY BIT(2)
61 #define P2WI_INTS_TRANS_ERR BIT(1)
62 #define P2WI_INTS_TRANS_OVER BIT(0)
63
64 /* DATA LENGTH fields*/
65 #define P2WI_DLEN_READ BIT(4)
66 #define P2WI_DLEN_DATA_LENGTH(v) ((v - 1) & 0x7)
67
68 /* LINE CTRL fields*/
69 #define P2WI_LCR_SCL_STATE BIT(5)
70 #define P2WI_LCR_SDA_STATE BIT(4)
71 #define P2WI_LCR_SCL_CTL BIT(3)
72 #define P2WI_LCR_SCL_CTL_EN BIT(2)
73 #define P2WI_LCR_SDA_CTL BIT(1)
74 #define P2WI_LCR_SDA_CTL_EN BIT(0)
75
76 /* PMU MODE CTRL fields */
77 #define P2WI_PMCR_PMU_INIT_SEND BIT(31)
78 #define P2WI_PMCR_PMU_INIT_DATA(v) (((v) & 0xff) << 16)
79 #define P2WI_PMCR_PMU_MODE_REG(v) (((v) & 0xff) << 8)
80 #define P2WI_PMCR_PMU_DEV_ADDR(v) ((v) & 0xff)
81
82 #define P2WI_MAX_FREQ 6000000
83
84 struct p2wi {
85 struct i2c_adapter adapter;
86 struct completion complete;
87 unsigned int status;
88 void __iomem *regs;
89 struct clk *clk;
90 struct reset_control *rstc;
91 int target_addr;
92 };
93
p2wi_interrupt(int irq,void * dev_id)94 static irqreturn_t p2wi_interrupt(int irq, void *dev_id)
95 {
96 struct p2wi *p2wi = dev_id;
97 unsigned long status;
98
99 status = readl(p2wi->regs + P2WI_INTS);
100 p2wi->status = status;
101
102 /* Clear interrupts */
103 status &= (P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR |
104 P2WI_INTS_TRANS_OVER);
105 writel(status, p2wi->regs + P2WI_INTS);
106
107 complete(&p2wi->complete);
108
109 return IRQ_HANDLED;
110 }
111
p2wi_functionality(struct i2c_adapter * adap)112 static u32 p2wi_functionality(struct i2c_adapter *adap)
113 {
114 return I2C_FUNC_SMBUS_BYTE_DATA;
115 }
116
p2wi_smbus_xfer(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)117 static int p2wi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
118 unsigned short flags, char read_write,
119 u8 command, int size, union i2c_smbus_data *data)
120 {
121 struct p2wi *p2wi = i2c_get_adapdata(adap);
122 unsigned long dlen = P2WI_DLEN_DATA_LENGTH(1);
123
124 if (p2wi->target_addr >= 0 && addr != p2wi->target_addr) {
125 dev_err(&adap->dev, "invalid P2WI address\n");
126 return -EINVAL;
127 }
128
129 if (!data)
130 return -EINVAL;
131
132 writel(command, p2wi->regs + P2WI_DADDR0);
133
134 if (read_write == I2C_SMBUS_READ)
135 dlen |= P2WI_DLEN_READ;
136 else
137 writel(data->byte, p2wi->regs + P2WI_DATA0);
138
139 writel(dlen, p2wi->regs + P2WI_DLEN);
140
141 if (readl(p2wi->regs + P2WI_CTRL) & P2WI_CTRL_START_TRANS) {
142 dev_err(&adap->dev, "P2WI bus busy\n");
143 return -EBUSY;
144 }
145
146 reinit_completion(&p2wi->complete);
147
148 writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER,
149 p2wi->regs + P2WI_INTE);
150
151 writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB,
152 p2wi->regs + P2WI_CTRL);
153
154 wait_for_completion(&p2wi->complete);
155
156 if (p2wi->status & P2WI_INTS_LOAD_BSY) {
157 dev_err(&adap->dev, "P2WI bus busy\n");
158 return -EBUSY;
159 }
160
161 if (p2wi->status & P2WI_INTS_TRANS_ERR) {
162 dev_err(&adap->dev, "P2WI bus xfer error\n");
163 return -ENXIO;
164 }
165
166 if (read_write == I2C_SMBUS_READ)
167 data->byte = readl(p2wi->regs + P2WI_DATA0);
168
169 return 0;
170 }
171
172 static const struct i2c_algorithm p2wi_algo = {
173 .smbus_xfer = p2wi_smbus_xfer,
174 .functionality = p2wi_functionality,
175 };
176
177 static const struct of_device_id p2wi_of_match_table[] = {
178 { .compatible = "allwinner,sun6i-a31-p2wi" },
179 {}
180 };
181 MODULE_DEVICE_TABLE(of, p2wi_of_match_table);
182
p2wi_probe(struct platform_device * pdev)183 static int p2wi_probe(struct platform_device *pdev)
184 {
185 struct device *dev = &pdev->dev;
186 struct device_node *np = dev->of_node;
187 struct device_node *childnp;
188 unsigned long parent_clk_freq;
189 u32 clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
190 struct p2wi *p2wi;
191 u32 target_addr;
192 int clk_div;
193 int irq;
194 int ret;
195
196 of_property_read_u32(np, "clock-frequency", &clk_freq);
197 if (clk_freq > P2WI_MAX_FREQ)
198 return dev_err_probe(dev, -EINVAL,
199 "required clock-frequency (%u Hz) is too high (max = 6MHz)",
200 clk_freq);
201
202 if (clk_freq == 0)
203 return dev_err_probe(dev, -EINVAL, "clock-frequency is set to 0 in DT\n");
204
205 if (of_get_child_count(np) > 1)
206 return dev_err_probe(dev, -EINVAL, "P2WI only supports one target device\n");
207
208 p2wi = devm_kzalloc(dev, sizeof(struct p2wi), GFP_KERNEL);
209 if (!p2wi)
210 return -ENOMEM;
211
212 p2wi->target_addr = -1;
213
214 /*
215 * Authorize a p2wi node without any children to be able to use an
216 * i2c-dev from userpace.
217 * In this case the target_addr is set to -1 and won't be checked when
218 * launching a P2WI transfer.
219 */
220 childnp = of_get_next_available_child(np, NULL);
221 if (childnp) {
222 ret = of_property_read_u32(childnp, "reg", &target_addr);
223 if (ret)
224 return dev_err_probe(dev, -EINVAL,
225 "invalid target address on node %pOF\n", childnp);
226
227 p2wi->target_addr = target_addr;
228 }
229
230 p2wi->regs = devm_platform_ioremap_resource(pdev, 0);
231 if (IS_ERR(p2wi->regs))
232 return PTR_ERR(p2wi->regs);
233
234 strscpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name));
235 irq = platform_get_irq(pdev, 0);
236 if (irq < 0)
237 return irq;
238
239 p2wi->clk = devm_clk_get_enabled(dev, NULL);
240 if (IS_ERR(p2wi->clk))
241 return dev_err_probe(dev, PTR_ERR(p2wi->clk),
242 "failed to enable clk\n");
243
244 parent_clk_freq = clk_get_rate(p2wi->clk);
245
246 p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL);
247 if (IS_ERR(p2wi->rstc))
248 return dev_err_probe(dev, PTR_ERR(p2wi->rstc),
249 "failed to retrieve reset controller\n");
250
251 ret = reset_control_deassert(p2wi->rstc);
252 if (ret)
253 return dev_err_probe(dev, ret, "failed to deassert reset line\n");
254
255 init_completion(&p2wi->complete);
256 p2wi->adapter.dev.parent = dev;
257 p2wi->adapter.algo = &p2wi_algo;
258 p2wi->adapter.owner = THIS_MODULE;
259 p2wi->adapter.dev.of_node = pdev->dev.of_node;
260 platform_set_drvdata(pdev, p2wi);
261 i2c_set_adapdata(&p2wi->adapter, p2wi);
262
263 ret = devm_request_irq(dev, irq, p2wi_interrupt, 0, pdev->name, p2wi);
264 if (ret)
265 goto err_reset_assert;
266
267 writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL);
268
269 clk_div = parent_clk_freq / clk_freq;
270 if (!clk_div) {
271 dev_warn(dev,
272 "clock-frequency is too high, setting it to %lu Hz\n",
273 parent_clk_freq);
274 clk_div = 1;
275 } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) {
276 dev_warn(dev,
277 "clock-frequency is too low, setting it to %lu Hz\n",
278 parent_clk_freq / P2WI_CCR_MAX_CLK_DIV);
279 clk_div = P2WI_CCR_MAX_CLK_DIV;
280 }
281
282 writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
283 p2wi->regs + P2WI_CCR);
284
285 ret = i2c_add_adapter(&p2wi->adapter);
286 if (!ret)
287 return 0;
288
289 err_reset_assert:
290 reset_control_assert(p2wi->rstc);
291
292 return ret;
293 }
294
p2wi_remove(struct platform_device * dev)295 static void p2wi_remove(struct platform_device *dev)
296 {
297 struct p2wi *p2wi = platform_get_drvdata(dev);
298
299 reset_control_assert(p2wi->rstc);
300 i2c_del_adapter(&p2wi->adapter);
301 }
302
303 static struct platform_driver p2wi_driver = {
304 .probe = p2wi_probe,
305 .remove = p2wi_remove,
306 .driver = {
307 .name = "i2c-sunxi-p2wi",
308 .of_match_table = p2wi_of_match_table,
309 },
310 };
311 module_platform_driver(p2wi_driver);
312
313 MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
314 MODULE_DESCRIPTION("Allwinner P2WI driver");
315 MODULE_LICENSE("GPL v2");
316