1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-cci.h>
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-fwnode.h>
16
17 #define OV02C10_LINK_FREQ_400MHZ 400000000ULL
18 #define OV02C10_MCLK 19200000
19 #define OV02C10_RGB_DEPTH 10
20
21 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a)
22 #define OV02C10_CHIP_ID 0x5602
23
24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)
25
26 #define OV02C10_REG_HTS CCI_REG16(0x380c)
27
28 /* vertical-timings from sensor */
29 #define OV02C10_REG_VTS CCI_REG16(0x380e)
30 #define OV02C10_VTS_MAX 0xffff
31
32 /* Exposure controls from sensor */
33 #define OV02C10_REG_EXPOSURE CCI_REG16(0x3501)
34 #define OV02C10_EXPOSURE_MIN 4
35 #define OV02C10_EXPOSURE_MAX_MARGIN 8
36 #define OV02C10_EXPOSURE_STEP 1
37
38 /* Analog gain controls from sensor */
39 #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508)
40 #define OV02C10_ANAL_GAIN_MIN 0x10
41 #define OV02C10_ANAL_GAIN_MAX 0xf8
42 #define OV02C10_ANAL_GAIN_STEP 1
43 #define OV02C10_ANAL_GAIN_DEFAULT 0x10
44
45 /* Digital gain controls from sensor */
46 #define OV02C10_REG_DIGITAL_GAIN CCI_REG24(0x350a)
47 #define OV02C10_DGTL_GAIN_MIN 0x0400
48 #define OV02C10_DGTL_GAIN_MAX 0x3fff
49 #define OV02C10_DGTL_GAIN_STEP 1
50 #define OV02C10_DGTL_GAIN_DEFAULT 0x0400
51
52 /* Rotate */
53 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820)
54 #define OV02C10_ISP_X_WIN_CONTROL CCI_REG16(0x3810)
55 #define OV02C10_ISP_Y_WIN_CONTROL CCI_REG16(0x3812)
56 #define OV02C10_CONFIG_ROTATE 0x18
57
58 /* Test Pattern Control */
59 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503)
60 #define OV02C10_TEST_PATTERN_ENABLE BIT(7)
61
62 struct ov02c10_mode {
63 /* Frame width in pixels */
64 u32 width;
65
66 /* Frame height in pixels */
67 u32 height;
68
69 /* Horizontal timining size */
70 u32 hts;
71
72 /* Min vertical timining size */
73 u32 vts_min;
74
75 /* Sensor register settings for this resolution */
76 const struct reg_sequence *reg_sequence;
77 const int sequence_length;
78 /* Sensor register settings for 1 or 2 lane config */
79 const struct reg_sequence *lane_settings[2];
80 const int lane_settings_length[2];
81 };
82
83 static const struct reg_sequence sensor_1928x1092_30fps_setting[] = {
84 {0x0301, 0x08},
85 {0x0303, 0x06},
86 {0x0304, 0x01},
87 {0x0305, 0xe0},
88 {0x0313, 0x40},
89 {0x031c, 0x4f},
90 {0x3020, 0x97},
91 {0x3022, 0x01},
92 {0x3026, 0xb4},
93 {0x303b, 0x00},
94 {0x303c, 0x4f},
95 {0x303d, 0xe6},
96 {0x303e, 0x00},
97 {0x303f, 0x03},
98 {0x3021, 0x23},
99 {0x3501, 0x04},
100 {0x3502, 0x6c},
101 {0x3504, 0x0c},
102 {0x3507, 0x00},
103 {0x3508, 0x08},
104 {0x3509, 0x00},
105 {0x350a, 0x01},
106 {0x350b, 0x00},
107 {0x350c, 0x41},
108 {0x3600, 0x84},
109 {0x3603, 0x08},
110 {0x3610, 0x57},
111 {0x3611, 0x1b},
112 {0x3613, 0x78},
113 {0x3623, 0x00},
114 {0x3632, 0xa0},
115 {0x3642, 0xe8},
116 {0x364c, 0x70},
117 {0x365f, 0x0f},
118 {0x3708, 0x30},
119 {0x3714, 0x24},
120 {0x3725, 0x02},
121 {0x3737, 0x08},
122 {0x3739, 0x28},
123 {0x3749, 0x32},
124 {0x374a, 0x32},
125 {0x374b, 0x32},
126 {0x374c, 0x32},
127 {0x374d, 0x81},
128 {0x374e, 0x81},
129 {0x374f, 0x81},
130 {0x3752, 0x36},
131 {0x3753, 0x36},
132 {0x3754, 0x36},
133 {0x3761, 0x00},
134 {0x376c, 0x81},
135 {0x3774, 0x18},
136 {0x3776, 0x08},
137 {0x377c, 0x81},
138 {0x377d, 0x81},
139 {0x377e, 0x81},
140 {0x37a0, 0x44},
141 {0x37a6, 0x44},
142 {0x37aa, 0x0d},
143 {0x37ae, 0x00},
144 {0x37cb, 0x03},
145 {0x37cc, 0x01},
146 {0x37d8, 0x02},
147 {0x37d9, 0x10},
148 {0x37e1, 0x10},
149 {0x37e2, 0x18},
150 {0x37e3, 0x08},
151 {0x37e4, 0x08},
152 {0x37e5, 0x02},
153 {0x37e6, 0x08},
154
155 /* 1928x1092 */
156 {0x3800, 0x00},
157 {0x3801, 0x00},
158 {0x3802, 0x00},
159 {0x3803, 0x00},
160 {0x3804, 0x07},
161 {0x3805, 0x8f},
162 {0x3806, 0x04},
163 {0x3807, 0x47},
164 {0x3808, 0x07},
165 {0x3809, 0x88},
166 {0x380a, 0x04},
167 {0x380b, 0x44},
168 {0x3814, 0x01},
169 {0x3815, 0x01},
170 {0x3816, 0x01},
171 {0x3817, 0x01},
172
173 {0x3820, 0xa8},
174 {0x3821, 0x00},
175 {0x3822, 0x80},
176 {0x3823, 0x08},
177 {0x3824, 0x00},
178 {0x3825, 0x20},
179 {0x3826, 0x00},
180 {0x3827, 0x08},
181 {0x382a, 0x00},
182 {0x382b, 0x08},
183 {0x382d, 0x00},
184 {0x382e, 0x00},
185 {0x382f, 0x23},
186 {0x3834, 0x00},
187 {0x3839, 0x00},
188 {0x383a, 0xd1},
189 {0x383e, 0x03},
190 {0x393d, 0x29},
191 {0x393f, 0x6e},
192 {0x394b, 0x06},
193 {0x394c, 0x06},
194 {0x394d, 0x08},
195 {0x394f, 0x01},
196 {0x3950, 0x01},
197 {0x3951, 0x01},
198 {0x3952, 0x01},
199 {0x3953, 0x01},
200 {0x3954, 0x01},
201 {0x3955, 0x01},
202 {0x3956, 0x01},
203 {0x3957, 0x0e},
204 {0x3958, 0x08},
205 {0x3959, 0x08},
206 {0x395a, 0x08},
207 {0x395b, 0x13},
208 {0x395c, 0x09},
209 {0x395d, 0x05},
210 {0x395e, 0x02},
211 {0x395f, 0x00},
212 {0x395f, 0x00},
213 {0x3960, 0x00},
214 {0x3961, 0x00},
215 {0x3962, 0x00},
216 {0x3963, 0x00},
217 {0x3964, 0x00},
218 {0x3965, 0x00},
219 {0x3966, 0x00},
220 {0x3967, 0x00},
221 {0x3968, 0x01},
222 {0x3969, 0x01},
223 {0x396a, 0x01},
224 {0x396b, 0x01},
225 {0x396c, 0x10},
226 {0x396d, 0xf0},
227 {0x396e, 0x11},
228 {0x396f, 0x00},
229 {0x3970, 0x37},
230 {0x3971, 0x37},
231 {0x3972, 0x37},
232 {0x3973, 0x37},
233 {0x3974, 0x00},
234 {0x3975, 0x3c},
235 {0x3976, 0x3c},
236 {0x3977, 0x3c},
237 {0x3978, 0x3c},
238 {0x3c00, 0x0f},
239 {0x3c20, 0x01},
240 {0x3c21, 0x08},
241 {0x3f00, 0x8b},
242 {0x3f02, 0x0f},
243 {0x4000, 0xc3},
244 {0x4001, 0xe0},
245 {0x4002, 0x00},
246 {0x4003, 0x40},
247 {0x4008, 0x04},
248 {0x4009, 0x23},
249 {0x400a, 0x04},
250 {0x400b, 0x01},
251 {0x4077, 0x06},
252 {0x4078, 0x00},
253 {0x4079, 0x1a},
254 {0x407a, 0x7f},
255 {0x407b, 0x01},
256 {0x4080, 0x03},
257 {0x4081, 0x84},
258 {0x4308, 0x03},
259 {0x4309, 0xff},
260 {0x430d, 0x00},
261 {0x4806, 0x00},
262 {0x4813, 0x00},
263 {0x4837, 0x10},
264 {0x4857, 0x05},
265 {0x4500, 0x07},
266 {0x4501, 0x00},
267 {0x4503, 0x00},
268 {0x450a, 0x04},
269 {0x450e, 0x00},
270 {0x450f, 0x00},
271 {0x4900, 0x00},
272 {0x4901, 0x00},
273 {0x4902, 0x01},
274 {0x5001, 0x50},
275 {0x5006, 0x00},
276 {0x5080, 0x40},
277 {0x5181, 0x2b},
278 {0x5202, 0xa3},
279 {0x5206, 0x01},
280 {0x5207, 0x00},
281 {0x520a, 0x01},
282 {0x520b, 0x00},
283 {0x365d, 0x00},
284 {0x4815, 0x40},
285 {0x4816, 0x12},
286 {0x4f00, 0x01},
287 };
288
289 static const struct reg_sequence sensor_1928x1092_30fps_1lane_setting[] = {
290 {0x301b, 0xd2},
291 {0x3027, 0xe1},
292 {0x380c, 0x08},
293 {0x380d, 0xe8},
294 {0x380e, 0x04},
295 {0x380f, 0x8c},
296 {0x394e, 0x0b},
297 {0x4800, 0x24},
298 {0x5000, 0xf5},
299 /* plls */
300 {0x0303, 0x05},
301 {0x0305, 0x90},
302 {0x0316, 0x90},
303 {0x3016, 0x12},
304 };
305
306 static const struct reg_sequence sensor_1928x1092_30fps_2lane_setting[] = {
307 {0x301b, 0xf0},
308 {0x3027, 0xf1},
309 {0x380c, 0x04},
310 {0x380d, 0x74},
311 {0x380e, 0x09},
312 {0x380f, 0x18},
313 {0x394e, 0x0a},
314 {0x4041, 0x20},
315 {0x4884, 0x04},
316 {0x4800, 0x64},
317 {0x4d00, 0x03},
318 {0x4d01, 0xd8},
319 {0x4d02, 0xba},
320 {0x4d03, 0xa0},
321 {0x4d04, 0xb7},
322 {0x4d05, 0x34},
323 {0x4d0d, 0x00},
324 {0x5000, 0xfd},
325 {0x481f, 0x30},
326 /* plls */
327 {0x0303, 0x05},
328 {0x0305, 0x90},
329 {0x0316, 0x90},
330 {0x3016, 0x32},
331 };
332
333 static const char * const ov02c10_test_pattern_menu[] = {
334 "Disabled",
335 "Color Bar",
336 "Top-Bottom Darker Color Bar",
337 "Right-Left Darker Color Bar",
338 "Color Bar type 4",
339 };
340
341 static const s64 link_freq_menu_items[] = {
342 OV02C10_LINK_FREQ_400MHZ,
343 };
344
345 static const struct ov02c10_mode supported_modes[] = {
346 {
347 .width = 1928,
348 .height = 1092,
349 .hts = 2280,
350 .vts_min = 1164,
351 .reg_sequence = sensor_1928x1092_30fps_setting,
352 .sequence_length = ARRAY_SIZE(sensor_1928x1092_30fps_setting),
353 .lane_settings = {
354 sensor_1928x1092_30fps_1lane_setting,
355 sensor_1928x1092_30fps_2lane_setting
356 },
357 .lane_settings_length = {
358 ARRAY_SIZE(sensor_1928x1092_30fps_1lane_setting),
359 ARRAY_SIZE(sensor_1928x1092_30fps_2lane_setting),
360 },
361 },
362 };
363
364 static const char * const ov02c10_supply_names[] = {
365 "dovdd", /* Digital I/O power */
366 "avdd", /* Analog power */
367 "dvdd", /* Digital core power */
368 };
369
370 struct ov02c10 {
371 struct device *dev;
372
373 struct v4l2_subdev sd;
374 struct media_pad pad;
375 struct v4l2_ctrl_handler ctrl_handler;
376 struct regmap *regmap;
377
378 /* V4L2 Controls */
379 struct v4l2_ctrl *link_freq;
380 struct v4l2_ctrl *pixel_rate;
381 struct v4l2_ctrl *vblank;
382 struct v4l2_ctrl *hblank;
383 struct v4l2_ctrl *exposure;
384
385 struct clk *img_clk;
386 struct gpio_desc *reset;
387 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02c10_supply_names)];
388
389 /* MIPI lane info */
390 u32 link_freq_index;
391 u8 mipi_lanes;
392 };
393
to_ov02c10(struct v4l2_subdev * subdev)394 static inline struct ov02c10 *to_ov02c10(struct v4l2_subdev *subdev)
395 {
396 return container_of(subdev, struct ov02c10, sd);
397 }
398
ov02c10_test_pattern(struct ov02c10 * ov02c10,int pattern)399 static int ov02c10_test_pattern(struct ov02c10 *ov02c10, int pattern)
400 {
401 int ret = 0;
402
403 if (!pattern)
404 return cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
405 BIT(7), 0, NULL);
406
407 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
408 0x03, pattern - 1, &ret);
409 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
410 BIT(7), OV02C10_TEST_PATTERN_ENABLE, &ret);
411 return ret;
412 }
413
ov02c10_set_ctrl(struct v4l2_ctrl * ctrl)414 static int ov02c10_set_ctrl(struct v4l2_ctrl *ctrl)
415 {
416 struct ov02c10 *ov02c10 = container_of(ctrl->handler,
417 struct ov02c10, ctrl_handler);
418 const u32 height = supported_modes[0].height;
419 s64 exposure_max;
420 int ret = 0;
421
422 /* Propagate change of current control to all related controls */
423 if (ctrl->id == V4L2_CID_VBLANK) {
424 /* Update max exposure while meeting expected vblanking */
425 exposure_max = height + ctrl->val - OV02C10_EXPOSURE_MAX_MARGIN;
426 __v4l2_ctrl_modify_range(ov02c10->exposure,
427 ov02c10->exposure->minimum,
428 exposure_max, ov02c10->exposure->step,
429 exposure_max);
430 }
431
432 /* V4L2 controls values will be applied only when power is already up */
433 if (!pm_runtime_get_if_in_use(ov02c10->dev))
434 return 0;
435
436 switch (ctrl->id) {
437 case V4L2_CID_ANALOGUE_GAIN:
438 cci_write(ov02c10->regmap, OV02C10_REG_ANALOG_GAIN,
439 ctrl->val << 4, &ret);
440 break;
441
442 case V4L2_CID_DIGITAL_GAIN:
443 cci_write(ov02c10->regmap, OV02C10_REG_DIGITAL_GAIN,
444 ctrl->val << 6, &ret);
445 break;
446
447 case V4L2_CID_EXPOSURE:
448 cci_write(ov02c10->regmap, OV02C10_REG_EXPOSURE,
449 ctrl->val, &ret);
450 break;
451
452 case V4L2_CID_VBLANK:
453 cci_write(ov02c10->regmap, OV02C10_REG_VTS, height + ctrl->val,
454 &ret);
455 break;
456
457 case V4L2_CID_TEST_PATTERN:
458 ret = ov02c10_test_pattern(ov02c10, ctrl->val);
459 break;
460
461 case V4L2_CID_HFLIP:
462 cci_write(ov02c10->regmap, OV02C10_ISP_X_WIN_CONTROL,
463 ctrl->val ? 2 : 1, &ret);
464 cci_update_bits(ov02c10->regmap, OV02C10_ROTATE_CONTROL,
465 BIT(3), ctrl->val ? 0 : BIT(3), &ret);
466 break;
467
468 case V4L2_CID_VFLIP:
469 cci_write(ov02c10->regmap, OV02C10_ISP_Y_WIN_CONTROL,
470 ctrl->val ? 2 : 1, &ret);
471 cci_update_bits(ov02c10->regmap, OV02C10_ROTATE_CONTROL,
472 BIT(4), ctrl->val << 4, &ret);
473 break;
474
475 default:
476 ret = -EINVAL;
477 break;
478 }
479
480 pm_runtime_put(ov02c10->dev);
481
482 return ret;
483 }
484
485 static const struct v4l2_ctrl_ops ov02c10_ctrl_ops = {
486 .s_ctrl = ov02c10_set_ctrl,
487 };
488
ov02c10_init_controls(struct ov02c10 * ov02c10)489 static int ov02c10_init_controls(struct ov02c10 *ov02c10)
490 {
491 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02c10->ctrl_handler;
492 const struct ov02c10_mode *mode = &supported_modes[0];
493 u32 vblank_min, vblank_max, vblank_default, vts_def;
494 struct v4l2_fwnode_device_properties props;
495 s64 exposure_max, h_blank, pixel_rate;
496 int ret;
497
498 v4l2_ctrl_handler_init(ctrl_hdlr, 12);
499
500 ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
501 &ov02c10_ctrl_ops,
502 V4L2_CID_LINK_FREQ,
503 ov02c10->link_freq_index, 0,
504 link_freq_menu_items);
505 if (ov02c10->link_freq)
506 ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
507
508 /* MIPI lanes are DDR -> use link-freq * 2 */
509 pixel_rate = div_u64(link_freq_menu_items[ov02c10->link_freq_index] *
510 2 * ov02c10->mipi_lanes, OV02C10_RGB_DEPTH);
511
512 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
513 V4L2_CID_PIXEL_RATE, 0,
514 pixel_rate, 1, pixel_rate);
515
516 /*
517 * For default multiple min by number of lanes to keep the default
518 * FPS the same indepenedent of the lane count.
519 */
520 vts_def = mode->vts_min * ov02c10->mipi_lanes;
521
522 vblank_min = mode->vts_min - mode->height;
523 vblank_max = OV02C10_VTS_MAX - mode->height;
524 vblank_default = vts_def - mode->height;
525 ov02c10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
526 V4L2_CID_VBLANK, vblank_min,
527 vblank_max, 1, vblank_default);
528
529 h_blank = mode->hts - mode->width;
530 ov02c10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
531 V4L2_CID_HBLANK, h_blank, h_blank,
532 1, h_blank);
533 if (ov02c10->hblank)
534 ov02c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
535
536 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
537 OV02C10_ANAL_GAIN_MIN, OV02C10_ANAL_GAIN_MAX,
538 OV02C10_ANAL_GAIN_STEP, OV02C10_ANAL_GAIN_DEFAULT);
539 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
540 OV02C10_DGTL_GAIN_MIN, OV02C10_DGTL_GAIN_MAX,
541 OV02C10_DGTL_GAIN_STEP, OV02C10_DGTL_GAIN_DEFAULT);
542 exposure_max = vts_def - OV02C10_EXPOSURE_MAX_MARGIN;
543 ov02c10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
544 V4L2_CID_EXPOSURE,
545 OV02C10_EXPOSURE_MIN,
546 exposure_max,
547 OV02C10_EXPOSURE_STEP,
548 exposure_max);
549
550 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_HFLIP,
551 0, 1, 1, 0);
552
553 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_VFLIP,
554 0, 1, 1, 0);
555
556 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02c10_ctrl_ops,
557 V4L2_CID_TEST_PATTERN,
558 ARRAY_SIZE(ov02c10_test_pattern_menu) - 1,
559 0, 0, ov02c10_test_pattern_menu);
560
561 ret = v4l2_fwnode_device_parse(ov02c10->dev, &props);
562 if (ret)
563 return ret;
564
565 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02c10_ctrl_ops, &props);
566
567 if (ctrl_hdlr->error)
568 return ctrl_hdlr->error;
569
570 ov02c10->sd.ctrl_handler = ctrl_hdlr;
571
572 return 0;
573 }
574
ov02c10_update_pad_format(const struct ov02c10_mode * mode,struct v4l2_mbus_framefmt * fmt)575 static void ov02c10_update_pad_format(const struct ov02c10_mode *mode,
576 struct v4l2_mbus_framefmt *fmt)
577 {
578 fmt->width = mode->width;
579 fmt->height = mode->height;
580 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
581 fmt->field = V4L2_FIELD_NONE;
582 }
583
ov02c10_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)584 static int ov02c10_enable_streams(struct v4l2_subdev *sd,
585 struct v4l2_subdev_state *state,
586 u32 pad, u64 streams_mask)
587 {
588 const struct ov02c10_mode *mode = &supported_modes[0];
589 struct ov02c10 *ov02c10 = to_ov02c10(sd);
590 const struct reg_sequence *reg_sequence;
591 int ret, sequence_length;
592
593 ret = pm_runtime_resume_and_get(ov02c10->dev);
594 if (ret)
595 return ret;
596
597 reg_sequence = mode->reg_sequence;
598 sequence_length = mode->sequence_length;
599 ret = regmap_multi_reg_write(ov02c10->regmap,
600 reg_sequence, sequence_length);
601 if (ret) {
602 dev_err(ov02c10->dev, "failed to set mode\n");
603 goto out;
604 }
605
606 reg_sequence = mode->lane_settings[ov02c10->mipi_lanes - 1];
607 sequence_length = mode->lane_settings_length[ov02c10->mipi_lanes - 1];
608 ret = regmap_multi_reg_write(ov02c10->regmap,
609 reg_sequence, sequence_length);
610 if (ret) {
611 dev_err(ov02c10->dev, "failed to write lane settings\n");
612 goto out;
613 }
614
615 ret = __v4l2_ctrl_handler_setup(ov02c10->sd.ctrl_handler);
616 if (ret)
617 goto out;
618
619 ret = cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 1, NULL);
620 out:
621 if (ret)
622 pm_runtime_put(ov02c10->dev);
623
624 return ret;
625 }
626
ov02c10_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)627 static int ov02c10_disable_streams(struct v4l2_subdev *sd,
628 struct v4l2_subdev_state *state,
629 u32 pad, u64 streams_mask)
630 {
631 struct ov02c10 *ov02c10 = to_ov02c10(sd);
632
633 cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 0, NULL);
634 pm_runtime_put(ov02c10->dev);
635
636 return 0;
637 }
638
639 /* This function tries to get power control resources */
ov02c10_get_pm_resources(struct device * dev)640 static int ov02c10_get_pm_resources(struct device *dev)
641 {
642 struct v4l2_subdev *sd = dev_get_drvdata(dev);
643 struct ov02c10 *ov02c10 = to_ov02c10(sd);
644 int i;
645
646 ov02c10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
647 if (IS_ERR(ov02c10->reset))
648 return dev_err_probe(dev, PTR_ERR(ov02c10->reset),
649 "failed to get reset gpio\n");
650
651 for (i = 0; i < ARRAY_SIZE(ov02c10_supply_names); i++)
652 ov02c10->supplies[i].supply = ov02c10_supply_names[i];
653
654 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02c10_supply_names),
655 ov02c10->supplies);
656 }
657
ov02c10_power_off(struct device * dev)658 static int ov02c10_power_off(struct device *dev)
659 {
660 struct v4l2_subdev *sd = dev_get_drvdata(dev);
661 struct ov02c10 *ov02c10 = to_ov02c10(sd);
662
663 gpiod_set_value_cansleep(ov02c10->reset, 1);
664
665 regulator_bulk_disable(ARRAY_SIZE(ov02c10_supply_names),
666 ov02c10->supplies);
667
668 clk_disable_unprepare(ov02c10->img_clk);
669
670 return 0;
671 }
672
ov02c10_power_on(struct device * dev)673 static int ov02c10_power_on(struct device *dev)
674 {
675 struct v4l2_subdev *sd = dev_get_drvdata(dev);
676 struct ov02c10 *ov02c10 = to_ov02c10(sd);
677 int ret;
678
679 ret = clk_prepare_enable(ov02c10->img_clk);
680 if (ret < 0) {
681 dev_err(dev, "failed to enable imaging clock: %d", ret);
682 return ret;
683 }
684
685 ret = regulator_bulk_enable(ARRAY_SIZE(ov02c10_supply_names),
686 ov02c10->supplies);
687 if (ret < 0) {
688 dev_err(dev, "failed to enable regulators: %d", ret);
689 clk_disable_unprepare(ov02c10->img_clk);
690 return ret;
691 }
692
693 if (ov02c10->reset) {
694 /* Assert reset for at least 2ms on back to back off-on */
695 usleep_range(2000, 2200);
696 gpiod_set_value_cansleep(ov02c10->reset, 0);
697 usleep_range(5000, 5100);
698 }
699
700 return 0;
701 }
702
ov02c10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)703 static int ov02c10_set_format(struct v4l2_subdev *sd,
704 struct v4l2_subdev_state *sd_state,
705 struct v4l2_subdev_format *fmt)
706 {
707 const struct ov02c10_mode *mode = &supported_modes[0];
708 struct ov02c10 *ov02c10 = to_ov02c10(sd);
709 s32 vblank_def, h_blank;
710
711 ov02c10_update_pad_format(mode, &fmt->format);
712 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
713
714 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
715 return 0;
716
717 /* Update limits and set FPS to default */
718 vblank_def = mode->vts_min * ov02c10->mipi_lanes - mode->height;
719 __v4l2_ctrl_modify_range(ov02c10->vblank, mode->vts_min - mode->height,
720 OV02C10_VTS_MAX - mode->height, 1, vblank_def);
721 __v4l2_ctrl_s_ctrl(ov02c10->vblank, vblank_def);
722 h_blank = mode->hts - mode->width;
723 __v4l2_ctrl_modify_range(ov02c10->hblank, h_blank, h_blank, 1, h_blank);
724
725 return 0;
726 }
727
ov02c10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)728 static int ov02c10_enum_mbus_code(struct v4l2_subdev *sd,
729 struct v4l2_subdev_state *sd_state,
730 struct v4l2_subdev_mbus_code_enum *code)
731 {
732 if (code->index > 0)
733 return -EINVAL;
734
735 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
736
737 return 0;
738 }
739
ov02c10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)740 static int ov02c10_enum_frame_size(struct v4l2_subdev *sd,
741 struct v4l2_subdev_state *sd_state,
742 struct v4l2_subdev_frame_size_enum *fse)
743 {
744 if (fse->index >= ARRAY_SIZE(supported_modes))
745 return -EINVAL;
746
747 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
748 return -EINVAL;
749
750 fse->min_width = supported_modes[fse->index].width;
751 fse->max_width = fse->min_width;
752 fse->min_height = supported_modes[fse->index].height;
753 fse->max_height = fse->min_height;
754
755 return 0;
756 }
757
ov02c10_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)758 static int ov02c10_init_state(struct v4l2_subdev *sd,
759 struct v4l2_subdev_state *sd_state)
760 {
761 ov02c10_update_pad_format(&supported_modes[0],
762 v4l2_subdev_state_get_format(sd_state, 0));
763
764 return 0;
765 }
766
767 static const struct v4l2_subdev_video_ops ov02c10_video_ops = {
768 .s_stream = v4l2_subdev_s_stream_helper,
769 };
770
771 static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = {
772 .set_fmt = ov02c10_set_format,
773 .get_fmt = v4l2_subdev_get_fmt,
774 .enum_mbus_code = ov02c10_enum_mbus_code,
775 .enum_frame_size = ov02c10_enum_frame_size,
776 .enable_streams = ov02c10_enable_streams,
777 .disable_streams = ov02c10_disable_streams,
778 };
779
780 static const struct v4l2_subdev_ops ov02c10_subdev_ops = {
781 .video = &ov02c10_video_ops,
782 .pad = &ov02c10_pad_ops,
783 };
784
785 static const struct media_entity_operations ov02c10_subdev_entity_ops = {
786 .link_validate = v4l2_subdev_link_validate,
787 };
788
789 static const struct v4l2_subdev_internal_ops ov02c10_internal_ops = {
790 .init_state = ov02c10_init_state,
791 };
792
ov02c10_identify_module(struct ov02c10 * ov02c10)793 static int ov02c10_identify_module(struct ov02c10 *ov02c10)
794 {
795 u64 chip_id;
796 int ret;
797
798 ret = cci_read(ov02c10->regmap, OV02C10_REG_CHIP_ID, &chip_id, NULL);
799 if (ret)
800 return ret;
801
802 if (chip_id != OV02C10_CHIP_ID) {
803 dev_err(ov02c10->dev, "chip id mismatch: %x!=%llx",
804 OV02C10_CHIP_ID, chip_id);
805 return -ENXIO;
806 }
807
808 return 0;
809 }
810
ov02c10_check_hwcfg(struct ov02c10 * ov02c10)811 static int ov02c10_check_hwcfg(struct ov02c10 *ov02c10)
812 {
813 struct v4l2_fwnode_endpoint bus_cfg = {
814 .bus_type = V4L2_MBUS_CSI2_DPHY
815 };
816 struct device *dev = ov02c10->dev;
817 struct fwnode_handle *ep, *fwnode = dev_fwnode(dev);
818 unsigned long link_freq_bitmap;
819 int ret;
820
821 /*
822 * Sometimes the fwnode graph is initialized by the bridge driver,
823 * wait for this.
824 */
825 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0);
826 if (!ep)
827 return dev_err_probe(dev, -EPROBE_DEFER,
828 "waiting for fwnode graph endpoint\n");
829
830 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
831 fwnode_handle_put(ep);
832 if (ret)
833 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
834
835 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
836 bus_cfg.nr_of_link_frequencies,
837 link_freq_menu_items,
838 ARRAY_SIZE(link_freq_menu_items),
839 &link_freq_bitmap);
840 if (ret)
841 goto check_hwcfg_error;
842
843 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */
844 ov02c10->link_freq_index = ffs(link_freq_bitmap) - 1;
845
846 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 1 &&
847 bus_cfg.bus.mipi_csi2.num_data_lanes != 2) {
848 ret = dev_err_probe(dev, -EINVAL,
849 "number of CSI2 data lanes %u is not supported\n",
850 bus_cfg.bus.mipi_csi2.num_data_lanes);
851 goto check_hwcfg_error;
852 }
853
854 ov02c10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
855
856 check_hwcfg_error:
857 v4l2_fwnode_endpoint_free(&bus_cfg);
858 return ret;
859 }
860
ov02c10_remove(struct i2c_client * client)861 static void ov02c10_remove(struct i2c_client *client)
862 {
863 struct v4l2_subdev *sd = i2c_get_clientdata(client);
864 struct ov02c10 *ov02c10 = to_ov02c10(sd);
865
866 v4l2_async_unregister_subdev(sd);
867 v4l2_subdev_cleanup(sd);
868 media_entity_cleanup(&sd->entity);
869 v4l2_ctrl_handler_free(sd->ctrl_handler);
870 pm_runtime_disable(ov02c10->dev);
871 if (!pm_runtime_status_suspended(ov02c10->dev)) {
872 ov02c10_power_off(ov02c10->dev);
873 pm_runtime_set_suspended(ov02c10->dev);
874 }
875 }
876
ov02c10_probe(struct i2c_client * client)877 static int ov02c10_probe(struct i2c_client *client)
878 {
879 struct ov02c10 *ov02c10;
880 unsigned long freq;
881 int ret;
882
883 ov02c10 = devm_kzalloc(&client->dev, sizeof(*ov02c10), GFP_KERNEL);
884 if (!ov02c10)
885 return -ENOMEM;
886
887 ov02c10->dev = &client->dev;
888
889 ov02c10->img_clk = devm_v4l2_sensor_clk_get(ov02c10->dev, NULL);
890 if (IS_ERR(ov02c10->img_clk))
891 return dev_err_probe(ov02c10->dev, PTR_ERR(ov02c10->img_clk),
892 "failed to get imaging clock\n");
893
894 freq = clk_get_rate(ov02c10->img_clk);
895 if (freq != OV02C10_MCLK)
896 return dev_err_probe(ov02c10->dev, -EINVAL,
897 "external clock %lu is not supported",
898 freq);
899
900 v4l2_i2c_subdev_init(&ov02c10->sd, client, &ov02c10_subdev_ops);
901
902 /* Check HW config */
903 ret = ov02c10_check_hwcfg(ov02c10);
904 if (ret)
905 return ret;
906
907 ret = ov02c10_get_pm_resources(ov02c10->dev);
908 if (ret)
909 return ret;
910
911 ov02c10->regmap = devm_cci_regmap_init_i2c(client, 16);
912 if (IS_ERR(ov02c10->regmap))
913 return PTR_ERR(ov02c10->regmap);
914
915 ret = ov02c10_power_on(ov02c10->dev);
916 if (ret) {
917 dev_err_probe(ov02c10->dev, ret, "failed to power on\n");
918 return ret;
919 }
920
921 ret = ov02c10_identify_module(ov02c10);
922 if (ret) {
923 dev_err(ov02c10->dev, "failed to find sensor: %d", ret);
924 goto probe_error_power_off;
925 }
926
927 ret = ov02c10_init_controls(ov02c10);
928 if (ret) {
929 dev_err(ov02c10->dev, "failed to init controls: %d", ret);
930 goto probe_error_v4l2_ctrl_handler_free;
931 }
932
933 ov02c10->sd.internal_ops = &ov02c10_internal_ops;
934 ov02c10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
935 ov02c10->sd.entity.ops = &ov02c10_subdev_entity_ops;
936 ov02c10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
937 ov02c10->pad.flags = MEDIA_PAD_FL_SOURCE;
938 ret = media_entity_pads_init(&ov02c10->sd.entity, 1, &ov02c10->pad);
939 if (ret) {
940 dev_err(ov02c10->dev, "failed to init entity pads: %d", ret);
941 goto probe_error_v4l2_ctrl_handler_free;
942 }
943
944 ov02c10->sd.state_lock = ov02c10->ctrl_handler.lock;
945 ret = v4l2_subdev_init_finalize(&ov02c10->sd);
946 if (ret < 0) {
947 dev_err(ov02c10->dev, "failed to init subdev: %d", ret);
948 goto probe_error_media_entity_cleanup;
949 }
950
951 pm_runtime_set_active(ov02c10->dev);
952 pm_runtime_enable(ov02c10->dev);
953
954 ret = v4l2_async_register_subdev_sensor(&ov02c10->sd);
955 if (ret < 0) {
956 dev_err(ov02c10->dev, "failed to register V4L2 subdev: %d",
957 ret);
958 goto probe_error_v4l2_subdev_cleanup;
959 }
960
961 pm_runtime_idle(ov02c10->dev);
962 return 0;
963
964 probe_error_v4l2_subdev_cleanup:
965 pm_runtime_disable(ov02c10->dev);
966 pm_runtime_set_suspended(ov02c10->dev);
967 v4l2_subdev_cleanup(&ov02c10->sd);
968
969 probe_error_media_entity_cleanup:
970 media_entity_cleanup(&ov02c10->sd.entity);
971
972 probe_error_v4l2_ctrl_handler_free:
973 v4l2_ctrl_handler_free(ov02c10->sd.ctrl_handler);
974
975 probe_error_power_off:
976 ov02c10_power_off(ov02c10->dev);
977
978 return ret;
979 }
980
981 static DEFINE_RUNTIME_DEV_PM_OPS(ov02c10_pm_ops, ov02c10_power_off,
982 ov02c10_power_on, NULL);
983
984 #ifdef CONFIG_ACPI
985 static const struct acpi_device_id ov02c10_acpi_ids[] = {
986 { "OVTI02C1" },
987 { /* sentinel */ }
988 };
989
990 MODULE_DEVICE_TABLE(acpi, ov02c10_acpi_ids);
991 #endif
992
993 static const struct of_device_id ov02c10_of_match[] = {
994 { .compatible = "ovti,ov02c10" },
995 { /* sentinel */ }
996 };
997 MODULE_DEVICE_TABLE(of, ov02c10_of_match);
998
999 static struct i2c_driver ov02c10_i2c_driver = {
1000 .driver = {
1001 .name = "ov02c10",
1002 .pm = pm_sleep_ptr(&ov02c10_pm_ops),
1003 .acpi_match_table = ACPI_PTR(ov02c10_acpi_ids),
1004 .of_match_table = ov02c10_of_match,
1005 },
1006 .probe = ov02c10_probe,
1007 .remove = ov02c10_remove,
1008 };
1009
1010 module_i2c_driver(ov02c10_i2c_driver);
1011
1012 MODULE_AUTHOR("Hao Yao <hao.yao@intel.com>");
1013 MODULE_AUTHOR("Heimir Thor Sverrisson <heimir.sverrisson@gmail.com>");
1014 MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>");
1015 MODULE_DESCRIPTION("OmniVision OV02C10 sensor driver");
1016 MODULE_LICENSE("GPL");
1017