1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Qualcomm Peripheral Authentication Service remoteproc driver
4 *
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/iommu.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_reserved_mem.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/firmware/qcom/qcom_pas.h>
25 #include <linux/firmware/qcom/qcom_scm.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/remoteproc.h>
28 #include <linux/soc/qcom/mdt_loader.h>
29 #include <linux/soc/qcom/smem.h>
30 #include <linux/soc/qcom/smem_state.h>
31
32 #include "qcom_common.h"
33 #include "qcom_pil_info.h"
34 #include "qcom_q6v5.h"
35 #include "remoteproc_internal.h"
36
37 #define QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS 100
38
39 #define MAX_ASSIGN_COUNT 3
40
41 struct qcom_pas_data {
42 int crash_reason_smem;
43 const char *firmware_name;
44 const char *dtb_firmware_name;
45 int pas_id;
46 int dtb_pas_id;
47 int lite_pas_id;
48 int lite_dtb_pas_id;
49 unsigned int minidump_id;
50 bool auto_boot;
51 bool decrypt_shutdown;
52
53 char **proxy_pd_names;
54
55 const char *load_state;
56 const char *ssr_name;
57 const char *sysmon_name;
58 int ssctl_id;
59 unsigned int smem_host_id;
60
61 int region_assign_idx;
62 int region_assign_count;
63 bool region_assign_shared;
64 int region_assign_vmid;
65 bool early_boot;
66 bool needs_tzmem;
67 };
68
69 struct qcom_pas {
70 struct device *dev;
71 struct rproc *rproc;
72
73 struct qcom_q6v5 q6v5;
74
75 struct clk *xo;
76 struct clk *aggre2_clk;
77
78 struct regulator *cx_supply;
79 struct regulator *px_supply;
80
81 struct device *proxy_pds[3];
82
83 int proxy_pd_count;
84
85 const char *dtb_firmware_name;
86 int pas_id;
87 int dtb_pas_id;
88 int lite_pas_id;
89 int lite_dtb_pas_id;
90 unsigned int minidump_id;
91 int crash_reason_smem;
92 unsigned int smem_host_id;
93 bool decrypt_shutdown;
94 const char *info_name;
95
96 const struct firmware *firmware;
97 const struct firmware *dtb_firmware;
98
99 phys_addr_t mem_phys;
100 phys_addr_t dtb_mem_phys;
101 phys_addr_t mem_reloc;
102 phys_addr_t dtb_mem_reloc;
103 phys_addr_t region_assign_phys[MAX_ASSIGN_COUNT];
104
105 void __iomem *mem_region;
106
107 size_t mem_size;
108 size_t dtb_mem_size;
109 size_t region_assign_size[MAX_ASSIGN_COUNT];
110
111 int region_assign_idx;
112 int region_assign_count;
113 bool region_assign_shared;
114 int region_assign_vmid;
115 u64 region_assign_owners[MAX_ASSIGN_COUNT];
116
117 struct qcom_rproc_glink glink_subdev;
118 struct qcom_rproc_subdev smd_subdev;
119 struct qcom_rproc_pdm pdm_subdev;
120 struct qcom_rproc_ssr ssr_subdev;
121 struct qcom_sysmon *sysmon;
122 struct platform_device *bam_dmux;
123
124 struct qcom_pas_context *pas_ctx;
125 struct qcom_pas_context *dtb_pas_ctx;
126 };
127
qcom_pas_segment_dump(struct rproc * rproc,struct rproc_dump_segment * segment,void * dest,size_t offset,size_t size)128 static void qcom_pas_segment_dump(struct rproc *rproc,
129 struct rproc_dump_segment *segment,
130 void *dest, size_t offset, size_t size)
131 {
132 struct qcom_pas *pas = rproc->priv;
133 int total_offset;
134
135 total_offset = segment->da + segment->offset + offset - pas->mem_phys;
136 if (total_offset < 0 || total_offset + size > pas->mem_size) {
137 dev_err(pas->dev,
138 "invalid copy request for segment %pad with offset %zu and size %zu)\n",
139 &segment->da, offset, size);
140 memset(dest, 0xff, size);
141 return;
142 }
143
144 memcpy_fromio(dest, pas->mem_region + total_offset, size);
145 }
146
qcom_pas_minidump(struct rproc * rproc)147 static void qcom_pas_minidump(struct rproc *rproc)
148 {
149 struct qcom_pas *pas = rproc->priv;
150
151 if (rproc->dump_conf == RPROC_COREDUMP_DISABLED)
152 return;
153
154 pas->mem_region = qcom_pas_ctx_map(pas->pas_ctx);
155 if (!pas->mem_region)
156 return;
157
158 qcom_minidump(rproc, pas->minidump_id, qcom_pas_segment_dump);
159 iounmap(pas->mem_region);
160 pas->mem_region = NULL;
161 }
162
qcom_pas_pds_enable(struct qcom_pas * pas,struct device ** pds,size_t pd_count)163 static int qcom_pas_pds_enable(struct qcom_pas *pas, struct device **pds,
164 size_t pd_count)
165 {
166 int ret;
167 int i;
168
169 for (i = 0; i < pd_count; i++) {
170 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
171 ret = pm_runtime_get_sync(pds[i]);
172 if (ret < 0) {
173 pm_runtime_put_noidle(pds[i]);
174 dev_pm_genpd_set_performance_state(pds[i], 0);
175 goto unroll_pd_votes;
176 }
177 }
178
179 return 0;
180
181 unroll_pd_votes:
182 for (i--; i >= 0; i--) {
183 dev_pm_genpd_set_performance_state(pds[i], 0);
184 pm_runtime_put(pds[i]);
185 }
186
187 return ret;
188 };
189
qcom_pas_pds_disable(struct qcom_pas * pas,struct device ** pds,size_t pd_count)190 static void qcom_pas_pds_disable(struct qcom_pas *pas, struct device **pds,
191 size_t pd_count)
192 {
193 int i;
194
195 for (i = 0; i < pd_count; i++) {
196 dev_pm_genpd_set_performance_state(pds[i], 0);
197 pm_runtime_put(pds[i]);
198 }
199 }
200
qcom_pas_shutdown_poll_decrypt(struct qcom_pas * pas)201 static int qcom_pas_shutdown_poll_decrypt(struct qcom_pas *pas)
202 {
203 unsigned int retry_num = 50;
204 int ret;
205
206 do {
207 msleep(QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS);
208 ret = qcom_pas_shutdown(pas->pas_id);
209 } while (ret == -EINVAL && --retry_num);
210
211 return ret;
212 }
213
qcom_pas_unprepare(struct rproc * rproc)214 static int qcom_pas_unprepare(struct rproc *rproc)
215 {
216 struct qcom_pas *pas = rproc->priv;
217
218 /*
219 * qcom_pas_load() did pass pas_metadata to the SCM driver for storing
220 * metadata context. It might have been released already if
221 * auth_and_reset() was successful, but in other cases clean it up
222 * here.
223 */
224 qcom_pas_metadata_release(pas->pas_ctx);
225 if (pas->dtb_pas_id)
226 qcom_pas_metadata_release(pas->dtb_pas_ctx);
227
228 return 0;
229 }
230
qcom_pas_load(struct rproc * rproc,const struct firmware * fw)231 static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
232 {
233 struct qcom_pas *pas = rproc->priv;
234 int ret;
235
236 /* Store firmware handle to be used in qcom_pas_start() */
237 pas->firmware = fw;
238
239 if (pas->lite_pas_id)
240 qcom_pas_shutdown(pas->lite_pas_id);
241 if (pas->lite_dtb_pas_id)
242 qcom_pas_shutdown(pas->lite_dtb_pas_id);
243
244 if (pas->dtb_pas_id) {
245 ret = request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas->dev);
246 if (ret) {
247 dev_err(pas->dev, "request_firmware failed for %s: %d\n",
248 pas->dtb_firmware_name, ret);
249 return ret;
250 }
251
252 ret = qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware,
253 pas->dtb_firmware_name, &pas->dtb_mem_reloc);
254 if (ret) {
255 qcom_pas_metadata_release(pas->dtb_pas_ctx);
256 release_firmware(pas->dtb_firmware);
257 return ret;
258 }
259 }
260
261 return 0;
262 }
263
qcom_pas_unmap_carveout(struct rproc * rproc,phys_addr_t mem_phys,size_t size)264 static void qcom_pas_unmap_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t size)
265 {
266 if (rproc->has_iommu)
267 iommu_unmap(rproc->domain, mem_phys, size);
268 }
269
qcom_pas_map_carveout(struct rproc * rproc,phys_addr_t mem_phys,size_t size)270 static int qcom_pas_map_carveout(struct rproc *rproc, phys_addr_t mem_phys, size_t size)
271 {
272 int ret = 0;
273
274 if (rproc->has_iommu)
275 ret = iommu_map(rproc->domain, mem_phys, mem_phys, size,
276 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
277 return ret;
278 }
279
qcom_pas_start(struct rproc * rproc)280 static int qcom_pas_start(struct rproc *rproc)
281 {
282 struct qcom_pas *pas = rproc->priv;
283 int ret;
284
285 ret = qcom_q6v5_prepare(&pas->q6v5);
286 if (ret)
287 return ret;
288
289 ret = qcom_pas_pds_enable(pas, pas->proxy_pds, pas->proxy_pd_count);
290 if (ret < 0)
291 goto disable_irqs;
292
293 ret = clk_prepare_enable(pas->xo);
294 if (ret)
295 goto disable_proxy_pds;
296
297 ret = clk_prepare_enable(pas->aggre2_clk);
298 if (ret)
299 goto disable_xo_clk;
300
301 if (pas->cx_supply) {
302 ret = regulator_enable(pas->cx_supply);
303 if (ret)
304 goto disable_aggre2_clk;
305 }
306
307 if (pas->px_supply) {
308 ret = regulator_enable(pas->px_supply);
309 if (ret)
310 goto disable_cx_supply;
311 }
312
313 if (pas->dtb_pas_id) {
314 ret = qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
315 if (ret)
316 goto disable_px_supply;
317
318 ret = qcom_pas_prepare_and_auth_reset(pas->dtb_pas_ctx);
319 if (ret) {
320 dev_err(pas->dev,
321 "failed to authenticate dtb image and release reset\n");
322 goto unmap_dtb_carveout;
323 }
324 }
325
326 ret = qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware,
327 &pas->mem_reloc);
328 if (ret)
329 goto release_pas_metadata;
330
331 qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size);
332
333 ret = qcom_pas_map_carveout(rproc, pas->mem_phys, pas->mem_size);
334 if (ret)
335 goto release_pas_metadata;
336
337 ret = qcom_pas_prepare_and_auth_reset(pas->pas_ctx);
338 if (ret) {
339 dev_err(pas->dev,
340 "failed to authenticate image and release reset\n");
341 goto unmap_carveout;
342 }
343
344 ret = qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000));
345 if (ret == -ETIMEDOUT) {
346 dev_err(pas->dev, "start timed out\n");
347 qcom_pas_shutdown(pas->pas_id);
348 goto unmap_carveout;
349 }
350
351 qcom_pas_metadata_release(pas->pas_ctx);
352 if (pas->dtb_pas_id)
353 qcom_pas_metadata_release(pas->dtb_pas_ctx);
354
355 /* firmware is used to pass reference from qcom_pas_start(), drop it now */
356 pas->firmware = NULL;
357
358 return 0;
359
360 unmap_carveout:
361 qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
362 release_pas_metadata:
363 qcom_pas_metadata_release(pas->pas_ctx);
364 if (pas->dtb_pas_id)
365 qcom_pas_metadata_release(pas->dtb_pas_ctx);
366
367 unmap_dtb_carveout:
368 if (pas->dtb_pas_id)
369 qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
370 disable_px_supply:
371 if (pas->px_supply)
372 regulator_disable(pas->px_supply);
373 disable_cx_supply:
374 if (pas->cx_supply)
375 regulator_disable(pas->cx_supply);
376 disable_aggre2_clk:
377 clk_disable_unprepare(pas->aggre2_clk);
378 disable_xo_clk:
379 clk_disable_unprepare(pas->xo);
380 disable_proxy_pds:
381 qcom_pas_pds_disable(pas, pas->proxy_pds, pas->proxy_pd_count);
382 disable_irqs:
383 qcom_q6v5_unprepare(&pas->q6v5);
384
385 /* firmware is used to pass reference from qcom_pas_start(), drop it now */
386 pas->firmware = NULL;
387
388 return ret;
389 }
390
qcom_pas_handover(struct qcom_q6v5 * q6v5)391 static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
392 {
393 struct qcom_pas *pas = container_of(q6v5, struct qcom_pas, q6v5);
394
395 if (pas->px_supply)
396 regulator_disable(pas->px_supply);
397 if (pas->cx_supply)
398 regulator_disable(pas->cx_supply);
399 clk_disable_unprepare(pas->aggre2_clk);
400 clk_disable_unprepare(pas->xo);
401 qcom_pas_pds_disable(pas, pas->proxy_pds, pas->proxy_pd_count);
402 }
403
qcom_pas_stop(struct rproc * rproc)404 static int qcom_pas_stop(struct rproc *rproc)
405 {
406 struct qcom_pas *pas = rproc->priv;
407 int handover;
408 int dtb_ret;
409 int ret;
410
411 ret = qcom_q6v5_request_stop(&pas->q6v5, pas->sysmon);
412 if (ret == -ETIMEDOUT)
413 dev_err(pas->dev, "timed out on wait\n");
414
415 ret = qcom_pas_shutdown(pas->pas_id);
416 if (ret && pas->decrypt_shutdown)
417 ret = qcom_pas_shutdown_poll_decrypt(pas);
418
419 if (ret)
420 dev_err(pas->dev, "failed to shutdown: %d\n", ret);
421
422 if (pas->dtb_pas_id) {
423 dtb_ret = qcom_pas_shutdown(pas->dtb_pas_id);
424 if (dtb_ret)
425 dev_err(pas->dev, "failed to shutdown dtb: %d\n", dtb_ret);
426
427 if (!ret && dtb_ret)
428 ret = dtb_ret;
429
430 qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size);
431 }
432
433 qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
434
435 handover = qcom_q6v5_unprepare(&pas->q6v5);
436 if (handover)
437 qcom_pas_handover(&pas->q6v5);
438
439 if (pas->smem_host_id)
440 ret = qcom_smem_bust_hwspin_lock_by_host(pas->smem_host_id);
441
442 return ret;
443 }
444
qcom_pas_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)445 static void *qcom_pas_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
446 {
447 struct qcom_pas *pas = rproc->priv;
448 int offset;
449
450 offset = da - pas->mem_reloc;
451 if (offset < 0 || offset + len > pas->mem_size)
452 return NULL;
453
454 if (is_iomem)
455 *is_iomem = true;
456
457 return (__force void *)pas->mem_region + offset;
458 }
459
qcom_pas_parse_firmware(struct rproc * rproc,const struct firmware * fw)460 static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmware *fw)
461 {
462 struct qcom_pas *pas = rproc->priv;
463 struct resource_table *table = NULL;
464 size_t output_rt_size;
465 void *output_rt;
466 size_t table_sz;
467 int ret;
468
469 ret = qcom_register_dump_segments(rproc, fw);
470 if (ret) {
471 dev_err(pas->dev, "Error in registering dump segments\n");
472 return ret;
473 }
474
475 if (!rproc->has_iommu)
476 return 0;
477
478 ret = rproc_elf_load_rsc_table(rproc, fw);
479 if (ret)
480 dev_dbg(&rproc->dev, "Failed to load resource table from firmware\n");
481
482 table = rproc->table_ptr;
483 table_sz = rproc->table_sz;
484
485 /*
486 * The resources consumed by Qualcomm remote processors fall into two categories:
487 * static (such as the memory carveouts for the rproc firmware) and dynamic (like
488 * shared memory pools). Both are managed by a Qualcomm hypervisor (such as QHEE
489 * or Gunyah), if one is present. Otherwise, a resource table must be retrieved
490 * via an SCM call. That table will list all dynamic resources (if any) and possibly
491 * the static ones. The static resources may also come from a resource table embedded
492 * in the rproc firmware instead.
493 *
494 * Here, we call rproc_elf_load_rsc_table() to check firmware binary has resources
495 * or not and if it is not having then we pass NULL and zero as input resource
496 * table pointer and size respectively to the argument of qcom_pas_get_rsc_table()
497 * and this is even true for Qualcomm remote processor who does follow remoteproc
498 * framework.
499 */
500 output_rt = qcom_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &output_rt_size);
501 ret = IS_ERR(output_rt) ? PTR_ERR(output_rt) : 0;
502 if (ret) {
503 dev_err(pas->dev, "Error in getting resource table: %d\n", ret);
504 return ret;
505 }
506
507 kfree(rproc->cached_table);
508 rproc->cached_table = output_rt;
509 rproc->table_ptr = rproc->cached_table;
510 rproc->table_sz = output_rt_size;
511
512 return ret;
513 }
514
qcom_pas_panic(struct rproc * rproc)515 static unsigned long qcom_pas_panic(struct rproc *rproc)
516 {
517 struct qcom_pas *pas = rproc->priv;
518
519 return qcom_q6v5_panic(&pas->q6v5);
520 }
521
qcom_pas_attach(struct rproc * rproc)522 static int qcom_pas_attach(struct rproc *rproc)
523 {
524 struct qcom_pas *pas = rproc->priv;
525 bool ready_state;
526 bool crash_state;
527 bool stop_state;
528 int ret;
529
530 pas->q6v5.handover_issued = true;
531
532 pas->q6v5.running = true;
533 ret = irq_get_irqchip_state(pas->q6v5.fatal_irq,
534 IRQCHIP_STATE_LINE_LEVEL, &crash_state);
535 if (ret)
536 goto disable_running;
537
538 if (crash_state) {
539 dev_err(pas->dev, "Subsystem has crashed before driver probe\n");
540 rproc_report_crash(rproc, RPROC_FATAL_ERROR);
541 ret = -EINVAL;
542 goto disable_running;
543 }
544
545 ret = irq_get_irqchip_state(pas->q6v5.stop_irq,
546 IRQCHIP_STATE_LINE_LEVEL, &stop_state);
547 if (ret)
548 goto disable_running;
549
550 if (stop_state || qcom_sysmon_shutdown_irq_state(pas->sysmon)) {
551 dev_info(pas->dev, "Subsystem found stop state set. Falling back to start.\n");
552 goto unroll_attach;
553 }
554
555 ret = irq_get_irqchip_state(pas->q6v5.ready_irq,
556 IRQCHIP_STATE_LINE_LEVEL, &ready_state);
557 if (ret)
558 goto disable_running;
559
560 if (unlikely(!ready_state)) {
561 /*
562 * The bootloader may not support early boot, mark the state as
563 * RPROC_OFFLINE so that the PAS driver can load the firmware and
564 * start the remoteproc.
565 */
566 dev_err(pas->dev, "Failed to get subsystem ready interrupt\n");
567 goto unroll_attach;
568 }
569
570 return 0;
571
572 unroll_attach:
573 pas->rproc->state = RPROC_OFFLINE;
574 ret = -EINVAL;
575 disable_running:
576 pas->q6v5.running = false;
577
578 return ret;
579 }
580
qcom_pas_coredump(struct rproc * rproc)581 static void qcom_pas_coredump(struct rproc *rproc)
582 {
583 struct qcom_pas *pas = rproc->priv;
584
585 pas->mem_region = qcom_pas_ctx_map(pas->pas_ctx);
586 if (!pas->mem_region)
587 return;
588
589 rproc_coredump(rproc);
590 iounmap(pas->mem_region);
591 pas->mem_region = NULL;
592 }
593
594 static const struct rproc_ops qcom_pas_ops = {
595 .unprepare = qcom_pas_unprepare,
596 .start = qcom_pas_start,
597 .stop = qcom_pas_stop,
598 .da_to_va = qcom_pas_da_to_va,
599 .parse_fw = qcom_pas_parse_firmware,
600 .load = qcom_pas_load,
601 .panic = qcom_pas_panic,
602 .attach = qcom_pas_attach,
603 .coredump = qcom_pas_coredump,
604 };
605
606 static const struct rproc_ops qcom_pas_minidump_ops = {
607 .unprepare = qcom_pas_unprepare,
608 .start = qcom_pas_start,
609 .stop = qcom_pas_stop,
610 .da_to_va = qcom_pas_da_to_va,
611 .parse_fw = qcom_pas_parse_firmware,
612 .load = qcom_pas_load,
613 .panic = qcom_pas_panic,
614 .coredump = qcom_pas_minidump,
615 .attach = qcom_pas_attach,
616 };
617
qcom_pas_init_clock(struct qcom_pas * pas)618 static int qcom_pas_init_clock(struct qcom_pas *pas)
619 {
620 pas->xo = devm_clk_get(pas->dev, "xo");
621 if (IS_ERR(pas->xo))
622 return dev_err_probe(pas->dev, PTR_ERR(pas->xo),
623 "failed to get xo clock");
624
625 pas->aggre2_clk = devm_clk_get_optional(pas->dev, "aggre2");
626 if (IS_ERR(pas->aggre2_clk))
627 return dev_err_probe(pas->dev, PTR_ERR(pas->aggre2_clk),
628 "failed to get aggre2 clock");
629
630 return 0;
631 }
632
qcom_pas_init_regulator(struct qcom_pas * pas)633 static int qcom_pas_init_regulator(struct qcom_pas *pas)
634 {
635 pas->cx_supply = devm_regulator_get_optional(pas->dev, "cx");
636 if (IS_ERR(pas->cx_supply)) {
637 if (PTR_ERR(pas->cx_supply) == -ENODEV)
638 pas->cx_supply = NULL;
639 else
640 return PTR_ERR(pas->cx_supply);
641 }
642
643 if (pas->cx_supply)
644 regulator_set_load(pas->cx_supply, 100000);
645
646 pas->px_supply = devm_regulator_get_optional(pas->dev, "px");
647 if (IS_ERR(pas->px_supply)) {
648 if (PTR_ERR(pas->px_supply) == -ENODEV)
649 pas->px_supply = NULL;
650 else
651 return PTR_ERR(pas->px_supply);
652 }
653
654 return 0;
655 }
656
qcom_pas_pds_attach(struct device * dev,struct device ** devs,char ** pd_names)657 static int qcom_pas_pds_attach(struct device *dev, struct device **devs, char **pd_names)
658 {
659 size_t num_pds = 0;
660 int ret;
661 int i;
662
663 if (!pd_names)
664 return 0;
665
666 while (pd_names[num_pds])
667 num_pds++;
668
669 /* Handle single power domain */
670 if (num_pds == 1 && dev->pm_domain) {
671 devs[0] = dev;
672 pm_runtime_enable(dev);
673 return 1;
674 }
675
676 for (i = 0; i < num_pds; i++) {
677 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
678 if (IS_ERR_OR_NULL(devs[i])) {
679 ret = PTR_ERR(devs[i]) ? : -ENODATA;
680 goto unroll_attach;
681 }
682 }
683
684 return num_pds;
685
686 unroll_attach:
687 for (i--; i >= 0; i--)
688 dev_pm_domain_detach(devs[i], false);
689
690 return ret;
691 };
692
qcom_pas_pds_detach(struct qcom_pas * pas,struct device ** pds,size_t pd_count)693 static void qcom_pas_pds_detach(struct qcom_pas *pas, struct device **pds, size_t pd_count)
694 {
695 struct device *dev = pas->dev;
696 int i;
697
698 /* Handle single power domain */
699 if (pd_count == 1 && dev->pm_domain) {
700 pm_runtime_disable(dev);
701 return;
702 }
703
704 for (i = 0; i < pd_count; i++)
705 dev_pm_domain_detach(pds[i], false);
706 }
707
qcom_pas_alloc_memory_region(struct qcom_pas * pas)708 static int qcom_pas_alloc_memory_region(struct qcom_pas *pas)
709 {
710 struct resource res;
711 int ret;
712
713 ret = of_reserved_mem_region_to_resource(pas->dev->of_node, 0, &res);
714 if (ret) {
715 dev_err(pas->dev, "unable to resolve memory-region\n");
716 return ret;
717 }
718
719 pas->mem_phys = pas->mem_reloc = res.start;
720 pas->mem_size = resource_size(&res);
721
722 pas->pas_ctx = devm_qcom_pas_context_alloc(pas->dev, pas->pas_id,
723 pas->mem_phys, pas->mem_size);
724 if (IS_ERR(pas->pas_ctx))
725 return PTR_ERR(pas->pas_ctx);
726
727 if (!pas->dtb_pas_id)
728 return 0;
729
730 ret = of_reserved_mem_region_to_resource(pas->dev->of_node, 1, &res);
731 if (ret) {
732 dev_err(pas->dev, "unable to resolve dtb memory-region\n");
733 return ret;
734 }
735
736 pas->dtb_mem_phys = pas->dtb_mem_reloc = res.start;
737 pas->dtb_mem_size = resource_size(&res);
738
739 pas->dtb_pas_ctx = devm_qcom_pas_context_alloc(pas->dev, pas->dtb_pas_id,
740 pas->dtb_mem_phys,
741 pas->dtb_mem_size);
742 if (IS_ERR(pas->dtb_pas_ctx))
743 return PTR_ERR(pas->dtb_pas_ctx);
744
745 return 0;
746 }
747
qcom_pas_assign_memory_region(struct qcom_pas * pas)748 static int qcom_pas_assign_memory_region(struct qcom_pas *pas)
749 {
750 struct qcom_scm_vmperm perm[MAX_ASSIGN_COUNT];
751 unsigned int perm_size;
752 int offset;
753 int ret;
754
755 if (!pas->region_assign_idx)
756 return 0;
757
758 for (offset = 0; offset < pas->region_assign_count; ++offset) {
759 struct resource res;
760
761 ret = of_reserved_mem_region_to_resource(pas->dev->of_node,
762 pas->region_assign_idx + offset,
763 &res);
764 if (ret) {
765 dev_err(pas->dev, "unable to resolve shareable memory-region index %d\n",
766 offset);
767 return ret;
768 }
769
770 if (pas->region_assign_shared) {
771 perm[0].vmid = QCOM_SCM_VMID_HLOS;
772 perm[0].perm = QCOM_SCM_PERM_RW;
773 perm[1].vmid = pas->region_assign_vmid;
774 perm[1].perm = QCOM_SCM_PERM_RW;
775 perm_size = 2;
776 } else {
777 perm[0].vmid = pas->region_assign_vmid;
778 perm[0].perm = QCOM_SCM_PERM_RW;
779 perm_size = 1;
780 }
781
782 pas->region_assign_phys[offset] = res.start;
783 pas->region_assign_size[offset] = resource_size(&res);
784 pas->region_assign_owners[offset] = BIT(QCOM_SCM_VMID_HLOS);
785
786 ret = qcom_scm_assign_mem(pas->region_assign_phys[offset],
787 pas->region_assign_size[offset],
788 &pas->region_assign_owners[offset],
789 perm, perm_size);
790 if (ret < 0) {
791 dev_err(pas->dev, "assign memory %d failed\n", offset);
792 return ret;
793 }
794 }
795
796 return 0;
797 }
798
qcom_pas_unassign_memory_region(struct qcom_pas * pas)799 static void qcom_pas_unassign_memory_region(struct qcom_pas *pas)
800 {
801 struct qcom_scm_vmperm perm;
802 int offset;
803 int ret;
804
805 if (!pas->region_assign_idx || pas->region_assign_shared)
806 return;
807
808 for (offset = 0; offset < pas->region_assign_count; ++offset) {
809 perm.vmid = QCOM_SCM_VMID_HLOS;
810 perm.perm = QCOM_SCM_PERM_RW;
811
812 ret = qcom_scm_assign_mem(pas->region_assign_phys[offset],
813 pas->region_assign_size[offset],
814 &pas->region_assign_owners[offset],
815 &perm, 1);
816 if (ret < 0)
817 dev_err(pas->dev, "unassign memory %d failed\n", offset);
818 }
819 }
820
qcom_pas_probe(struct platform_device * pdev)821 static int qcom_pas_probe(struct platform_device *pdev)
822 {
823 const struct qcom_pas_data *desc;
824 struct qcom_pas *pas;
825 struct rproc *rproc;
826 struct device_node *node;
827 const char *fw_name, *dtb_fw_name = NULL;
828 const struct rproc_ops *ops = &qcom_pas_ops;
829 int ret;
830
831 desc = of_device_get_match_data(&pdev->dev);
832 if (!desc)
833 return -EINVAL;
834
835 if (!qcom_pas_is_available())
836 return -EPROBE_DEFER;
837
838 fw_name = desc->firmware_name;
839 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
840 &fw_name);
841 if (ret < 0 && ret != -EINVAL)
842 return ret;
843
844 if (desc->dtb_firmware_name) {
845 dtb_fw_name = desc->dtb_firmware_name;
846 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 1,
847 &dtb_fw_name);
848 if (ret < 0 && ret != -EINVAL)
849 return ret;
850 }
851
852 if (desc->minidump_id)
853 ops = &qcom_pas_minidump_ops;
854
855 rproc = devm_rproc_alloc(&pdev->dev, desc->sysmon_name, ops, fw_name, sizeof(*pas));
856
857 if (!rproc) {
858 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
859 return -ENOMEM;
860 }
861
862 rproc->has_iommu = of_property_present(pdev->dev.of_node, "iommus");
863 rproc->auto_boot = desc->auto_boot;
864 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
865
866 pas = rproc->priv;
867 pas->dev = &pdev->dev;
868 pas->rproc = rproc;
869 pas->minidump_id = desc->minidump_id;
870 pas->pas_id = desc->pas_id;
871 pas->lite_pas_id = desc->lite_pas_id;
872 pas->lite_dtb_pas_id = desc->lite_dtb_pas_id;
873 pas->info_name = desc->sysmon_name;
874 pas->smem_host_id = desc->smem_host_id;
875 pas->decrypt_shutdown = desc->decrypt_shutdown;
876 pas->region_assign_idx = desc->region_assign_idx;
877 pas->region_assign_count = min_t(int, MAX_ASSIGN_COUNT, desc->region_assign_count);
878 pas->region_assign_vmid = desc->region_assign_vmid;
879 pas->region_assign_shared = desc->region_assign_shared;
880 if (dtb_fw_name) {
881 pas->dtb_firmware_name = dtb_fw_name;
882 pas->dtb_pas_id = desc->dtb_pas_id;
883 }
884 platform_set_drvdata(pdev, pas);
885
886 ret = device_init_wakeup(pas->dev, true);
887 if (ret)
888 goto free_rproc;
889
890 ret = qcom_pas_alloc_memory_region(pas);
891 if (ret)
892 goto free_rproc;
893
894 ret = qcom_pas_assign_memory_region(pas);
895 if (ret)
896 goto free_rproc;
897
898 ret = qcom_pas_init_clock(pas);
899 if (ret)
900 goto unassign_mem;
901
902 ret = qcom_pas_init_regulator(pas);
903 if (ret)
904 goto unassign_mem;
905
906 ret = qcom_pas_pds_attach(&pdev->dev, pas->proxy_pds, desc->proxy_pd_names);
907 if (ret < 0)
908 goto unassign_mem;
909 pas->proxy_pd_count = ret;
910
911 ret = qcom_q6v5_init(&pas->q6v5, pdev, rproc, desc->crash_reason_smem,
912 desc->load_state, qcom_pas_handover);
913 if (ret)
914 goto detach_proxy_pds;
915
916 qcom_add_glink_subdev(rproc, &pas->glink_subdev, desc->ssr_name);
917 qcom_add_smd_subdev(rproc, &pas->smd_subdev);
918 qcom_add_pdm_subdev(rproc, &pas->pdm_subdev);
919 pas->sysmon = qcom_add_sysmon_subdev(rproc, desc->sysmon_name, desc->ssctl_id);
920 if (IS_ERR(pas->sysmon)) {
921 ret = PTR_ERR(pas->sysmon);
922 goto deinit_remove_pdm_smd_glink;
923 }
924
925 qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name);
926
927 pas->pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
928 if (pas->dtb_pas_id)
929 pas->dtb_pas_ctx->use_tzmem = desc->needs_tzmem || rproc->has_iommu;
930
931 if (desc->early_boot)
932 pas->rproc->state = RPROC_DETACHED;
933
934 ret = rproc_add(rproc);
935 if (ret)
936 goto remove_ssr_sysmon;
937
938 node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux");
939 pas->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev);
940 of_node_put(node);
941
942 return 0;
943
944 remove_ssr_sysmon:
945 qcom_remove_ssr_subdev(rproc, &pas->ssr_subdev);
946 qcom_remove_sysmon_subdev(pas->sysmon);
947 deinit_remove_pdm_smd_glink:
948 qcom_remove_pdm_subdev(rproc, &pas->pdm_subdev);
949 qcom_remove_smd_subdev(rproc, &pas->smd_subdev);
950 qcom_remove_glink_subdev(rproc, &pas->glink_subdev);
951 qcom_q6v5_deinit(&pas->q6v5);
952 detach_proxy_pds:
953 qcom_pas_pds_detach(pas, pas->proxy_pds, pas->proxy_pd_count);
954 unassign_mem:
955 qcom_pas_unassign_memory_region(pas);
956 free_rproc:
957 device_init_wakeup(pas->dev, false);
958
959 return ret;
960 }
961
qcom_pas_remove(struct platform_device * pdev)962 static void qcom_pas_remove(struct platform_device *pdev)
963 {
964 struct qcom_pas *pas = platform_get_drvdata(pdev);
965
966 if (pas->bam_dmux)
967 of_platform_device_destroy(&pas->bam_dmux->dev, NULL);
968
969 rproc_del(pas->rproc);
970
971 qcom_q6v5_deinit(&pas->q6v5);
972 qcom_pas_unassign_memory_region(pas);
973 qcom_remove_glink_subdev(pas->rproc, &pas->glink_subdev);
974 qcom_remove_sysmon_subdev(pas->sysmon);
975 qcom_remove_smd_subdev(pas->rproc, &pas->smd_subdev);
976 qcom_remove_pdm_subdev(pas->rproc, &pas->pdm_subdev);
977 qcom_remove_ssr_subdev(pas->rproc, &pas->ssr_subdev);
978 qcom_pas_pds_detach(pas, pas->proxy_pds, pas->proxy_pd_count);
979 device_init_wakeup(pas->dev, false);
980 }
981
982 static const struct qcom_pas_data adsp_resource_init = {
983 .crash_reason_smem = 423,
984 .firmware_name = "adsp.mdt",
985 .pas_id = 1,
986 .auto_boot = true,
987 .ssr_name = "lpass",
988 .sysmon_name = "adsp",
989 .ssctl_id = 0x14,
990 };
991
992 static const struct qcom_pas_data sa8775p_adsp_resource = {
993 .crash_reason_smem = 423,
994 .firmware_name = "adsp.mbn",
995 .pas_id = 1,
996 .minidump_id = 5,
997 .auto_boot = true,
998 .proxy_pd_names = (char*[]){
999 "lcx",
1000 "lmx",
1001 NULL
1002 },
1003 .load_state = "adsp",
1004 .ssr_name = "lpass",
1005 .sysmon_name = "adsp",
1006 .ssctl_id = 0x14,
1007 };
1008
1009 static const struct qcom_pas_data sdm845_adsp_resource_init = {
1010 .crash_reason_smem = 423,
1011 .firmware_name = "adsp.mdt",
1012 .pas_id = 1,
1013 .auto_boot = true,
1014 .load_state = "adsp",
1015 .ssr_name = "lpass",
1016 .sysmon_name = "adsp",
1017 .ssctl_id = 0x14,
1018 };
1019
1020 static const struct qcom_pas_data sm6350_adsp_resource = {
1021 .crash_reason_smem = 423,
1022 .firmware_name = "adsp.mdt",
1023 .pas_id = 1,
1024 .auto_boot = true,
1025 .proxy_pd_names = (char*[]){
1026 "lcx",
1027 "lmx",
1028 NULL
1029 },
1030 .load_state = "adsp",
1031 .ssr_name = "lpass",
1032 .sysmon_name = "adsp",
1033 .ssctl_id = 0x14,
1034 };
1035
1036 static const struct qcom_pas_data sm6375_mpss_resource = {
1037 .crash_reason_smem = 421,
1038 .firmware_name = "modem.mdt",
1039 .pas_id = 4,
1040 .minidump_id = 3,
1041 .auto_boot = false,
1042 .proxy_pd_names = (char*[]){
1043 "cx",
1044 NULL
1045 },
1046 .ssr_name = "mpss",
1047 .sysmon_name = "modem",
1048 .ssctl_id = 0x12,
1049 };
1050
1051 static const struct qcom_pas_data sm8150_adsp_resource = {
1052 .crash_reason_smem = 423,
1053 .firmware_name = "adsp.mdt",
1054 .pas_id = 1,
1055 .auto_boot = true,
1056 .proxy_pd_names = (char*[]){
1057 "cx",
1058 NULL
1059 },
1060 .load_state = "adsp",
1061 .ssr_name = "lpass",
1062 .sysmon_name = "adsp",
1063 .ssctl_id = 0x14,
1064 };
1065
1066 static const struct qcom_pas_data sm8250_adsp_resource = {
1067 .crash_reason_smem = 423,
1068 .firmware_name = "adsp.mdt",
1069 .pas_id = 1,
1070 .minidump_id = 5,
1071 .auto_boot = true,
1072 .proxy_pd_names = (char*[]){
1073 "lcx",
1074 "lmx",
1075 NULL
1076 },
1077 .load_state = "adsp",
1078 .ssr_name = "lpass",
1079 .sysmon_name = "adsp",
1080 .ssctl_id = 0x14,
1081 };
1082
1083 static const struct qcom_pas_data sm8350_adsp_resource = {
1084 .crash_reason_smem = 423,
1085 .firmware_name = "adsp.mdt",
1086 .pas_id = 1,
1087 .auto_boot = true,
1088 .proxy_pd_names = (char*[]){
1089 "lcx",
1090 "lmx",
1091 NULL
1092 },
1093 .load_state = "adsp",
1094 .ssr_name = "lpass",
1095 .sysmon_name = "adsp",
1096 .ssctl_id = 0x14,
1097 };
1098
1099 static const struct qcom_pas_data msm8996_adsp_resource = {
1100 .crash_reason_smem = 423,
1101 .firmware_name = "adsp.mdt",
1102 .pas_id = 1,
1103 .auto_boot = true,
1104 .proxy_pd_names = (char*[]){
1105 "cx",
1106 NULL
1107 },
1108 .ssr_name = "lpass",
1109 .sysmon_name = "adsp",
1110 .ssctl_id = 0x14,
1111 };
1112
1113 static const struct qcom_pas_data cdsp_resource_init = {
1114 .crash_reason_smem = 601,
1115 .firmware_name = "cdsp.mdt",
1116 .pas_id = 18,
1117 .auto_boot = true,
1118 .ssr_name = "cdsp",
1119 .sysmon_name = "cdsp",
1120 .ssctl_id = 0x17,
1121 };
1122
1123 static const struct qcom_pas_data sa8775p_cdsp0_resource = {
1124 .crash_reason_smem = 601,
1125 .firmware_name = "cdsp0.mbn",
1126 .pas_id = 18,
1127 .minidump_id = 7,
1128 .auto_boot = true,
1129 .proxy_pd_names = (char*[]){
1130 "cx",
1131 "mxc",
1132 "nsp",
1133 NULL
1134 },
1135 .load_state = "cdsp",
1136 .ssr_name = "cdsp",
1137 .sysmon_name = "cdsp",
1138 .ssctl_id = 0x17,
1139 };
1140
1141 static const struct qcom_pas_data sa8775p_cdsp1_resource = {
1142 .crash_reason_smem = 633,
1143 .firmware_name = "cdsp1.mbn",
1144 .pas_id = 30,
1145 .minidump_id = 20,
1146 .auto_boot = true,
1147 .proxy_pd_names = (char*[]){
1148 "cx",
1149 "mxc",
1150 "nsp",
1151 NULL
1152 },
1153 .load_state = "nsp",
1154 .ssr_name = "cdsp1",
1155 .sysmon_name = "cdsp1",
1156 .ssctl_id = 0x20,
1157 };
1158
1159 static const struct qcom_pas_data sdm845_cdsp_resource_init = {
1160 .crash_reason_smem = 601,
1161 .firmware_name = "cdsp.mdt",
1162 .pas_id = 18,
1163 .auto_boot = true,
1164 .load_state = "cdsp",
1165 .ssr_name = "cdsp",
1166 .sysmon_name = "cdsp",
1167 .ssctl_id = 0x17,
1168 };
1169
1170 static const struct qcom_pas_data sm6350_cdsp_resource = {
1171 .crash_reason_smem = 601,
1172 .firmware_name = "cdsp.mdt",
1173 .pas_id = 18,
1174 .auto_boot = true,
1175 .proxy_pd_names = (char*[]){
1176 "cx",
1177 "mx",
1178 NULL
1179 },
1180 .load_state = "cdsp",
1181 .ssr_name = "cdsp",
1182 .sysmon_name = "cdsp",
1183 .ssctl_id = 0x17,
1184 };
1185
1186 static const struct qcom_pas_data sm8150_cdsp_resource = {
1187 .crash_reason_smem = 601,
1188 .firmware_name = "cdsp.mdt",
1189 .pas_id = 18,
1190 .auto_boot = true,
1191 .proxy_pd_names = (char*[]){
1192 "cx",
1193 NULL
1194 },
1195 .load_state = "cdsp",
1196 .ssr_name = "cdsp",
1197 .sysmon_name = "cdsp",
1198 .ssctl_id = 0x17,
1199 };
1200
1201 static const struct qcom_pas_data sm8250_cdsp_resource = {
1202 .crash_reason_smem = 601,
1203 .firmware_name = "cdsp.mdt",
1204 .pas_id = 18,
1205 .auto_boot = true,
1206 .proxy_pd_names = (char*[]){
1207 "cx",
1208 NULL
1209 },
1210 .load_state = "cdsp",
1211 .ssr_name = "cdsp",
1212 .sysmon_name = "cdsp",
1213 .ssctl_id = 0x17,
1214 };
1215
1216 static const struct qcom_pas_data sc8280xp_nsp0_resource = {
1217 .crash_reason_smem = 601,
1218 .firmware_name = "cdsp.mdt",
1219 .pas_id = 18,
1220 .auto_boot = true,
1221 .proxy_pd_names = (char*[]){
1222 "nsp",
1223 NULL
1224 },
1225 .ssr_name = "cdsp0",
1226 .sysmon_name = "cdsp",
1227 .ssctl_id = 0x17,
1228 };
1229
1230 static const struct qcom_pas_data sc8280xp_nsp1_resource = {
1231 .crash_reason_smem = 633,
1232 .firmware_name = "cdsp.mdt",
1233 .pas_id = 30,
1234 .auto_boot = true,
1235 .proxy_pd_names = (char*[]){
1236 "nsp",
1237 NULL
1238 },
1239 .ssr_name = "cdsp1",
1240 .sysmon_name = "cdsp1",
1241 .ssctl_id = 0x20,
1242 };
1243
1244 static const struct qcom_pas_data x1e80100_adsp_resource = {
1245 .crash_reason_smem = 423,
1246 .firmware_name = "adsp.mdt",
1247 .dtb_firmware_name = "adsp_dtb.mdt",
1248 .pas_id = 1,
1249 .dtb_pas_id = 0x24,
1250 .lite_pas_id = 0x1f,
1251 .lite_dtb_pas_id = 0x29,
1252 .minidump_id = 5,
1253 .auto_boot = true,
1254 .proxy_pd_names = (char*[]){
1255 "lcx",
1256 "lmx",
1257 NULL
1258 },
1259 .load_state = "adsp",
1260 .ssr_name = "lpass",
1261 .sysmon_name = "adsp",
1262 .ssctl_id = 0x14,
1263 };
1264
1265 static const struct qcom_pas_data x1e80100_cdsp_resource = {
1266 .crash_reason_smem = 601,
1267 .firmware_name = "cdsp.mdt",
1268 .dtb_firmware_name = "cdsp_dtb.mdt",
1269 .pas_id = 18,
1270 .dtb_pas_id = 0x25,
1271 .minidump_id = 7,
1272 .auto_boot = true,
1273 .proxy_pd_names = (char*[]){
1274 "cx",
1275 "mxc",
1276 "nsp",
1277 NULL
1278 },
1279 .load_state = "cdsp",
1280 .ssr_name = "cdsp",
1281 .sysmon_name = "cdsp",
1282 .ssctl_id = 0x17,
1283 };
1284
1285 static const struct qcom_pas_data sm8350_cdsp_resource = {
1286 .crash_reason_smem = 601,
1287 .firmware_name = "cdsp.mdt",
1288 .pas_id = 18,
1289 .minidump_id = 7,
1290 .auto_boot = true,
1291 .proxy_pd_names = (char*[]){
1292 "cx",
1293 "mxc",
1294 NULL
1295 },
1296 .load_state = "cdsp",
1297 .ssr_name = "cdsp",
1298 .sysmon_name = "cdsp",
1299 .ssctl_id = 0x17,
1300 };
1301
1302 static const struct qcom_pas_data sa8775p_gpdsp0_resource = {
1303 .crash_reason_smem = 640,
1304 .firmware_name = "gpdsp0.mbn",
1305 .pas_id = 39,
1306 .minidump_id = 21,
1307 .auto_boot = true,
1308 .proxy_pd_names = (char*[]){
1309 "cx",
1310 "mxc",
1311 NULL
1312 },
1313 .load_state = "gpdsp0",
1314 .ssr_name = "gpdsp0",
1315 .sysmon_name = "gpdsp0",
1316 .ssctl_id = 0x21,
1317 };
1318
1319 static const struct qcom_pas_data sa8775p_gpdsp1_resource = {
1320 .crash_reason_smem = 641,
1321 .firmware_name = "gpdsp1.mbn",
1322 .pas_id = 40,
1323 .minidump_id = 22,
1324 .auto_boot = true,
1325 .proxy_pd_names = (char*[]){
1326 "cx",
1327 "mxc",
1328 NULL
1329 },
1330 .load_state = "gpdsp1",
1331 .ssr_name = "gpdsp1",
1332 .sysmon_name = "gpdsp1",
1333 .ssctl_id = 0x22,
1334 };
1335
1336 static const struct qcom_pas_data mpss_resource_init = {
1337 .crash_reason_smem = 421,
1338 .firmware_name = "modem.mdt",
1339 .pas_id = 4,
1340 .minidump_id = 3,
1341 .auto_boot = false,
1342 .proxy_pd_names = (char*[]){
1343 "cx",
1344 "mss",
1345 NULL
1346 },
1347 .load_state = "modem",
1348 .ssr_name = "mpss",
1349 .sysmon_name = "modem",
1350 .ssctl_id = 0x12,
1351 };
1352
1353 static const struct qcom_pas_data sc8180x_mpss_resource = {
1354 .crash_reason_smem = 421,
1355 .firmware_name = "modem.mdt",
1356 .pas_id = 4,
1357 .auto_boot = false,
1358 .proxy_pd_names = (char*[]){
1359 "cx",
1360 NULL
1361 },
1362 .load_state = "modem",
1363 .ssr_name = "mpss",
1364 .sysmon_name = "modem",
1365 .ssctl_id = 0x12,
1366 };
1367
1368 static const struct qcom_pas_data msm8996_slpi_resource_init = {
1369 .crash_reason_smem = 424,
1370 .firmware_name = "slpi.mdt",
1371 .pas_id = 12,
1372 .auto_boot = true,
1373 .proxy_pd_names = (char*[]){
1374 "ssc_cx",
1375 NULL
1376 },
1377 .ssr_name = "dsps",
1378 .sysmon_name = "slpi",
1379 .ssctl_id = 0x16,
1380 };
1381
1382 static const struct qcom_pas_data sdm845_slpi_resource_init = {
1383 .crash_reason_smem = 424,
1384 .firmware_name = "slpi.mdt",
1385 .pas_id = 12,
1386 .auto_boot = true,
1387 .proxy_pd_names = (char*[]){
1388 "lcx",
1389 "lmx",
1390 NULL
1391 },
1392 .load_state = "slpi",
1393 .ssr_name = "dsps",
1394 .sysmon_name = "slpi",
1395 .ssctl_id = 0x16,
1396 };
1397
1398 static const struct qcom_pas_data wcss_resource_init = {
1399 .crash_reason_smem = 421,
1400 .firmware_name = "wcnss.mdt",
1401 .pas_id = 6,
1402 .auto_boot = true,
1403 .ssr_name = "mpss",
1404 .sysmon_name = "wcnss",
1405 .ssctl_id = 0x12,
1406 };
1407
1408 static const struct qcom_pas_data sdx55_mpss_resource = {
1409 .crash_reason_smem = 421,
1410 .firmware_name = "modem.mdt",
1411 .pas_id = 4,
1412 .auto_boot = true,
1413 .proxy_pd_names = (char*[]){
1414 "cx",
1415 "mss",
1416 NULL
1417 },
1418 .ssr_name = "mpss",
1419 .sysmon_name = "modem",
1420 .ssctl_id = 0x22,
1421 };
1422
1423 static const struct qcom_pas_data milos_cdsp_resource = {
1424 .crash_reason_smem = 601,
1425 .firmware_name = "cdsp.mbn",
1426 .dtb_firmware_name = "cdsp_dtb.mbn",
1427 .pas_id = 18,
1428 .dtb_pas_id = 0x25,
1429 .minidump_id = 7,
1430 .auto_boot = true,
1431 .proxy_pd_names = (char*[]){
1432 "cx",
1433 "mx",
1434 NULL
1435 },
1436 .load_state = "cdsp",
1437 .ssr_name = "cdsp",
1438 .sysmon_name = "cdsp",
1439 .ssctl_id = 0x17,
1440 .smem_host_id = 5,
1441 };
1442
1443 static const struct qcom_pas_data nord_adsp_resource = {
1444 .crash_reason_smem = 423,
1445 .firmware_name = "adsp.mbn",
1446 .dtb_firmware_name = "adsp_dtb.mbn",
1447 .pas_id = 1,
1448 .dtb_pas_id = 36,
1449 .minidump_id = 5,
1450 .auto_boot = true,
1451 .early_boot = true,
1452 .proxy_pd_names = (char*[]){
1453 "cx",
1454 "mx",
1455 NULL
1456 },
1457 .load_state = "adsp",
1458 .ssr_name = "lpass",
1459 .sysmon_name = "adsp",
1460 .ssctl_id = 0x14,
1461 .smem_host_id = 2,
1462 };
1463
1464 static const struct qcom_pas_data nord_cdsp0_resource = {
1465 .crash_reason_smem = 601,
1466 .firmware_name = "cdsp.mbn",
1467 .dtb_firmware_name = "cdsp_dtb.mbn",
1468 .pas_id = 18,
1469 .dtb_pas_id = 37,
1470 .minidump_id = 7,
1471 .auto_boot = true,
1472 .proxy_pd_names = (char*[]){
1473 "cx",
1474 "mx",
1475 "nsp",
1476 NULL
1477 },
1478 .load_state = "cdsp",
1479 .ssr_name = "cdsp0",
1480 .sysmon_name = "cdsp0",
1481 .ssctl_id = 0x17,
1482 .smem_host_id = 5,
1483 };
1484
1485 static const struct qcom_pas_data nord_cdsp1_resource = {
1486 .crash_reason_smem = 633,
1487 .firmware_name = "cdsp1.mbn",
1488 .dtb_firmware_name = "cdsp1_dtb.mbn",
1489 .pas_id = 30,
1490 .dtb_pas_id = 59,
1491 .minidump_id = 20,
1492 .auto_boot = true,
1493 .proxy_pd_names = (char*[]){
1494 "cx",
1495 "mx",
1496 "nsp",
1497 NULL
1498 },
1499 .load_state = "cdsp1",
1500 .ssr_name = "cdsp1",
1501 .sysmon_name = "cdsp1",
1502 .ssctl_id = 0x20,
1503 .smem_host_id = 69,
1504 };
1505
1506 static const struct qcom_pas_data nord_cdsp2_resource = {
1507 .crash_reason_smem = 665,
1508 .firmware_name = "cdsp2.mbn",
1509 .dtb_firmware_name = "cdsp2_dtb.mbn",
1510 .pas_id = 57,
1511 .dtb_pas_id = 60,
1512 .minidump_id = 29,
1513 .auto_boot = true,
1514 .proxy_pd_names = (char*[]){
1515 "cx",
1516 "mx",
1517 "nsp",
1518 NULL
1519 },
1520 .load_state = "cdsp2",
1521 .ssr_name = "cdsp2",
1522 .sysmon_name = "cdsp2",
1523 .ssctl_id = 0x1f,
1524 .smem_host_id = 133,
1525 };
1526
1527 static const struct qcom_pas_data nord_cdsp3_resource = {
1528 .crash_reason_smem = 666,
1529 .firmware_name = "cdsp3.mbn",
1530 .dtb_firmware_name = "cdsp3_dtb.mbn",
1531 .pas_id = 58,
1532 .dtb_pas_id = 61,
1533 .minidump_id = 30,
1534 .auto_boot = true,
1535 .proxy_pd_names = (char*[]){
1536 "cx",
1537 "mx",
1538 "nsp",
1539 NULL
1540 },
1541 .load_state = "cdsp3",
1542 .ssr_name = "cdsp3",
1543 .sysmon_name = "cdsp3",
1544 .ssctl_id = 0x1a,
1545 .smem_host_id = 197,
1546 };
1547
1548 static const struct qcom_pas_data sm8450_mpss_resource = {
1549 .crash_reason_smem = 421,
1550 .firmware_name = "modem.mdt",
1551 .pas_id = 4,
1552 .minidump_id = 3,
1553 .auto_boot = false,
1554 .decrypt_shutdown = true,
1555 .proxy_pd_names = (char*[]){
1556 "cx",
1557 "mss",
1558 NULL
1559 },
1560 .load_state = "modem",
1561 .ssr_name = "mpss",
1562 .sysmon_name = "modem",
1563 .ssctl_id = 0x12,
1564 };
1565
1566 static const struct qcom_pas_data sm8550_adsp_resource = {
1567 .crash_reason_smem = 423,
1568 .firmware_name = "adsp.mdt",
1569 .dtb_firmware_name = "adsp_dtb.mdt",
1570 .pas_id = 1,
1571 .dtb_pas_id = 0x24,
1572 .minidump_id = 5,
1573 .auto_boot = true,
1574 .proxy_pd_names = (char*[]){
1575 "lcx",
1576 "lmx",
1577 NULL
1578 },
1579 .load_state = "adsp",
1580 .ssr_name = "lpass",
1581 .sysmon_name = "adsp",
1582 .ssctl_id = 0x14,
1583 .smem_host_id = 2,
1584 };
1585
1586 static const struct qcom_pas_data sm8550_cdsp_resource = {
1587 .crash_reason_smem = 601,
1588 .firmware_name = "cdsp.mdt",
1589 .dtb_firmware_name = "cdsp_dtb.mdt",
1590 .pas_id = 18,
1591 .dtb_pas_id = 0x25,
1592 .minidump_id = 7,
1593 .auto_boot = true,
1594 .proxy_pd_names = (char*[]){
1595 "cx",
1596 "mxc",
1597 "nsp",
1598 NULL
1599 },
1600 .load_state = "cdsp",
1601 .ssr_name = "cdsp",
1602 .sysmon_name = "cdsp",
1603 .ssctl_id = 0x17,
1604 .smem_host_id = 5,
1605 };
1606
1607 static const struct qcom_pas_data sm8550_mpss_resource = {
1608 .crash_reason_smem = 421,
1609 .firmware_name = "modem.mdt",
1610 .dtb_firmware_name = "modem_dtb.mdt",
1611 .pas_id = 4,
1612 .dtb_pas_id = 0x26,
1613 .minidump_id = 3,
1614 .auto_boot = false,
1615 .decrypt_shutdown = true,
1616 .proxy_pd_names = (char*[]){
1617 "cx",
1618 "mss",
1619 NULL
1620 },
1621 .load_state = "modem",
1622 .ssr_name = "mpss",
1623 .sysmon_name = "modem",
1624 .ssctl_id = 0x12,
1625 .smem_host_id = 1,
1626 .region_assign_idx = 2,
1627 .region_assign_count = 1,
1628 .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
1629 };
1630
1631 static const struct qcom_pas_data sc7280_wpss_resource = {
1632 .crash_reason_smem = 626,
1633 .firmware_name = "wpss.mdt",
1634 .pas_id = 6,
1635 .minidump_id = 4,
1636 .auto_boot = false,
1637 .proxy_pd_names = (char*[]){
1638 "cx",
1639 "mx",
1640 NULL
1641 },
1642 .load_state = "wpss",
1643 .ssr_name = "wpss",
1644 .sysmon_name = "wpss",
1645 .ssctl_id = 0x19,
1646 };
1647
1648 static const struct qcom_pas_data shikra_cdsp_resource = {
1649 .crash_reason_smem = 601,
1650 .firmware_name = "cdsp.mbn",
1651 .pas_id = 18,
1652 .minidump_id = 7,
1653 .auto_boot = true,
1654 .proxy_pd_names = (char *[]){
1655 "cx",
1656 NULL
1657 },
1658 .load_state = "cdsp",
1659 .ssr_name = "cdsp",
1660 .sysmon_name = "cdsp",
1661 .ssctl_id = 0x17,
1662 .smem_host_id = 5,
1663 };
1664
1665 static const struct qcom_pas_data shikra_lpaicp_resource = {
1666 .crash_reason_smem = 682,
1667 .firmware_name = "lpaicp.mbn",
1668 .dtb_firmware_name = "lpaicp_dtb.mbn",
1669 .pas_id = 0x56,
1670 .dtb_pas_id = 0x57,
1671 .minidump_id = 0,
1672 .auto_boot = true,
1673 .ssr_name = "lpaicp",
1674 .sysmon_name = "lpaicp",
1675 };
1676
1677 static const struct qcom_pas_data shikra_mpss_resource = {
1678 .crash_reason_smem = 421,
1679 .firmware_name = "qdsp6sw.mbn",
1680 .pas_id = 4,
1681 .minidump_id = 3,
1682 .auto_boot = false,
1683 .proxy_pd_names = (char *[]){
1684 "cx",
1685 NULL
1686 },
1687 .load_state = "modem",
1688 .ssr_name = "mpss",
1689 .sysmon_name = "modem",
1690 .ssctl_id = 0x12,
1691 };
1692
1693 static const struct qcom_pas_data sm8650_cdsp_resource = {
1694 .crash_reason_smem = 601,
1695 .firmware_name = "cdsp.mdt",
1696 .dtb_firmware_name = "cdsp_dtb.mdt",
1697 .pas_id = 18,
1698 .dtb_pas_id = 0x25,
1699 .minidump_id = 7,
1700 .auto_boot = true,
1701 .proxy_pd_names = (char*[]){
1702 "cx",
1703 "mxc",
1704 "nsp",
1705 NULL
1706 },
1707 .load_state = "cdsp",
1708 .ssr_name = "cdsp",
1709 .sysmon_name = "cdsp",
1710 .ssctl_id = 0x17,
1711 .smem_host_id = 5,
1712 .region_assign_idx = 2,
1713 .region_assign_count = 1,
1714 .region_assign_shared = true,
1715 .region_assign_vmid = QCOM_SCM_VMID_CDSP,
1716 };
1717
1718 static const struct qcom_pas_data sm8650_mpss_resource = {
1719 .crash_reason_smem = 421,
1720 .firmware_name = "modem.mdt",
1721 .dtb_firmware_name = "modem_dtb.mdt",
1722 .pas_id = 4,
1723 .dtb_pas_id = 0x26,
1724 .minidump_id = 3,
1725 .auto_boot = false,
1726 .decrypt_shutdown = true,
1727 .proxy_pd_names = (char*[]){
1728 "cx",
1729 "mss",
1730 NULL
1731 },
1732 .load_state = "modem",
1733 .ssr_name = "mpss",
1734 .sysmon_name = "modem",
1735 .ssctl_id = 0x12,
1736 .smem_host_id = 1,
1737 .region_assign_idx = 2,
1738 .region_assign_count = 3,
1739 .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
1740 };
1741
1742 static const struct qcom_pas_data sm8750_mpss_resource = {
1743 .crash_reason_smem = 421,
1744 .firmware_name = "modem.mdt",
1745 .dtb_firmware_name = "modem_dtb.mdt",
1746 .pas_id = 4,
1747 .dtb_pas_id = 0x26,
1748 .minidump_id = 3,
1749 .auto_boot = false,
1750 .decrypt_shutdown = true,
1751 .proxy_pd_names = (char*[]){
1752 "cx",
1753 "mss",
1754 NULL
1755 },
1756 .load_state = "modem",
1757 .ssr_name = "mpss",
1758 .sysmon_name = "modem",
1759 .ssctl_id = 0x12,
1760 .smem_host_id = 1,
1761 .region_assign_idx = 2,
1762 .region_assign_count = 2,
1763 .region_assign_vmid = QCOM_SCM_VMID_MSS_MSA,
1764 };
1765
1766 static const struct qcom_pas_data kaanapali_soccp_resource = {
1767 .crash_reason_smem = 656,
1768 .firmware_name = "soccp.mbn",
1769 .dtb_firmware_name = "soccp_dtb.mbn",
1770 .pas_id = 51,
1771 .dtb_pas_id = 0x41,
1772 .proxy_pd_names = (char*[]){
1773 "cx",
1774 "mx",
1775 NULL
1776 },
1777 .ssr_name = "soccp",
1778 .sysmon_name = "soccp",
1779 .auto_boot = true,
1780 .early_boot = true,
1781 };
1782
1783 static const struct qcom_pas_data glymur_soccp_resource = {
1784 .crash_reason_smem = 656,
1785 .firmware_name = "soccp.mbn",
1786 .dtb_firmware_name = "soccp_dtb.mbn",
1787 .pas_id = 51,
1788 .dtb_pas_id = 0x41,
1789 .proxy_pd_names = (char*[]){
1790 "cx",
1791 "mx",
1792 NULL
1793 },
1794 .ssr_name = "soccp",
1795 .sysmon_name = "soccp",
1796 .auto_boot = true,
1797 .early_boot = true,
1798 .needs_tzmem = true,
1799 };
1800
1801 static const struct qcom_pas_data eliza_cdsp_resource = {
1802 .crash_reason_smem = 601,
1803 .firmware_name = "cdsp.mbn",
1804 .dtb_firmware_name = "cdsp_dtb.mbn",
1805 .pas_id = 18,
1806 .dtb_pas_id = 0x25,
1807 .minidump_id = 7,
1808 .auto_boot = true,
1809 .proxy_pd_names = (char*[]){
1810 "cx",
1811 "mx",
1812 "nsp",
1813 NULL
1814 },
1815 .load_state = "cdsp",
1816 .ssr_name = "cdsp",
1817 .sysmon_name = "cdsp",
1818 .ssctl_id = 0x17,
1819 .smem_host_id = 5,
1820 .region_assign_idx = 2,
1821 .region_assign_count = 1,
1822 .region_assign_shared = true,
1823 .region_assign_vmid = QCOM_SCM_VMID_CDSP,
1824 };
1825
1826 static const struct of_device_id qcom_pas_of_match[] = {
1827 { .compatible = "qcom,eliza-adsp-pas", .data = &sm8550_adsp_resource },
1828 { .compatible = "qcom,eliza-cdsp-pas", .data = &eliza_cdsp_resource },
1829 { .compatible = "qcom,glymur-soccp-pas", .data = &glymur_soccp_resource },
1830 { .compatible = "qcom,kaanapali-soccp-pas", .data = &kaanapali_soccp_resource },
1831 { .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource },
1832 { .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource },
1833 { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource },
1834 { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource },
1835 { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource },
1836 { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource },
1837 { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource },
1838 { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource },
1839 { .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init },
1840 { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource },
1841 { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init },
1842 { .compatible = "qcom,nord-adsp-pas", .data = &nord_adsp_resource },
1843 { .compatible = "qcom,nord-cdsp0-pas", .data = &nord_cdsp0_resource },
1844 { .compatible = "qcom,nord-cdsp1-pas", .data = &nord_cdsp1_resource },
1845 { .compatible = "qcom,nord-cdsp2-pas", .data = &nord_cdsp2_resource },
1846 { .compatible = "qcom,nord-cdsp3-pas", .data = &nord_cdsp3_resource },
1847 { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
1848 { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
1849 { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
1850 { .compatible = "qcom,sa8775p-adsp-pas", .data = &sa8775p_adsp_resource },
1851 { .compatible = "qcom,sa8775p-cdsp0-pas", .data = &sa8775p_cdsp0_resource },
1852 { .compatible = "qcom,sa8775p-cdsp1-pas", .data = &sa8775p_cdsp1_resource },
1853 { .compatible = "qcom,sa8775p-gpdsp0-pas", .data = &sa8775p_gpdsp0_resource },
1854 { .compatible = "qcom,sa8775p-gpdsp1-pas", .data = &sa8775p_gpdsp1_resource },
1855 { .compatible = "qcom,sar2130p-adsp-pas", .data = &sm8350_adsp_resource },
1856 { .compatible = "qcom,sc7180-adsp-pas", .data = &sm8250_adsp_resource },
1857 { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init },
1858 { .compatible = "qcom,sc7280-adsp-pas", .data = &sm8350_adsp_resource },
1859 { .compatible = "qcom,sc7280-cdsp-pas", .data = &sm6350_cdsp_resource },
1860 { .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init },
1861 { .compatible = "qcom,sc7280-wpss-pas", .data = &sc7280_wpss_resource },
1862 { .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource },
1863 { .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource },
1864 { .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource },
1865 { .compatible = "qcom,sc8280xp-adsp-pas", .data = &sm8250_adsp_resource },
1866 { .compatible = "qcom,sc8280xp-nsp0-pas", .data = &sc8280xp_nsp0_resource },
1867 { .compatible = "qcom,sc8280xp-nsp1-pas", .data = &sc8280xp_nsp1_resource },
1868 { .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init },
1869 { .compatible = "qcom,sdm660-cdsp-pas", .data = &cdsp_resource_init },
1870 { .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init },
1871 { .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init },
1872 { .compatible = "qcom,sdm845-slpi-pas", .data = &sdm845_slpi_resource_init },
1873 { .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource },
1874 { .compatible = "qcom,sdx75-mpss-pas", .data = &sm8650_mpss_resource },
1875 { .compatible = "qcom,shikra-cdsp-pas", .data = &shikra_cdsp_resource },
1876 { .compatible = "qcom,shikra-lpaicp-pas", .data = &shikra_lpaicp_resource },
1877 { .compatible = "qcom,shikra-mpss-pas", .data = &shikra_mpss_resource },
1878 { .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init },
1879 { .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init },
1880 { .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource },
1881 { .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource },
1882 { .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource },
1883 { .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init },
1884 { .compatible = "qcom,sm6375-adsp-pas", .data = &sm6350_adsp_resource },
1885 { .compatible = "qcom,sm6375-cdsp-pas", .data = &sm8150_cdsp_resource },
1886 { .compatible = "qcom,sm6375-mpss-pas", .data = &sm6375_mpss_resource },
1887 { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource },
1888 { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource },
1889 { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init },
1890 { .compatible = "qcom,sm8150-slpi-pas", .data = &sdm845_slpi_resource_init },
1891 { .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource },
1892 { .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource },
1893 { .compatible = "qcom,sm8250-slpi-pas", .data = &sdm845_slpi_resource_init },
1894 { .compatible = "qcom,sm8350-adsp-pas", .data = &sm8350_adsp_resource },
1895 { .compatible = "qcom,sm8350-cdsp-pas", .data = &sm8350_cdsp_resource },
1896 { .compatible = "qcom,sm8350-slpi-pas", .data = &sdm845_slpi_resource_init },
1897 { .compatible = "qcom,sm8350-mpss-pas", .data = &mpss_resource_init },
1898 { .compatible = "qcom,sm8450-adsp-pas", .data = &sm8350_adsp_resource },
1899 { .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource },
1900 { .compatible = "qcom,sm8450-slpi-pas", .data = &sdm845_slpi_resource_init },
1901 { .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource },
1902 { .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource },
1903 { .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource },
1904 { .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource },
1905 { .compatible = "qcom,sm8650-adsp-pas", .data = &sm8550_adsp_resource },
1906 { .compatible = "qcom,sm8650-cdsp-pas", .data = &sm8650_cdsp_resource },
1907 { .compatible = "qcom,sm8650-mpss-pas", .data = &sm8650_mpss_resource },
1908 { .compatible = "qcom,sm8750-mpss-pas", .data = &sm8750_mpss_resource },
1909 { .compatible = "qcom,x1e80100-adsp-pas", .data = &x1e80100_adsp_resource },
1910 { .compatible = "qcom,x1e80100-cdsp-pas", .data = &x1e80100_cdsp_resource },
1911 { },
1912 };
1913 MODULE_DEVICE_TABLE(of, qcom_pas_of_match);
1914
1915 static struct platform_driver qcom_pas_driver = {
1916 .probe = qcom_pas_probe,
1917 .remove = qcom_pas_remove,
1918 .driver = {
1919 .name = "qcom_q6v5_pas",
1920 .of_match_table = qcom_pas_of_match,
1921 },
1922 };
1923
1924 module_platform_driver(qcom_pas_driver);
1925 MODULE_DESCRIPTION("Qualcomm Peripheral Authentication Service remoteproc driver");
1926 MODULE_LICENSE("GPL v2");
1927