1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/array_size.h>
4 #include <linux/bitfield.h>
5 #include <linux/bits.h>
6 #include <linux/dev_printk.h>
7 #include <linux/device.h>
8 #include <linux/export.h>
9 #include <linux/math64.h>
10 #include <linux/module.h>
11 #include <linux/netlink.h>
12 #include <linux/regmap.h>
13 #include <linux/sprintf.h>
14 #include <linux/string_choices.h>
15 #include <linux/unaligned.h>
16 #include <net/devlink.h>
17
18 #include "core.h"
19 #include "devlink.h"
20 #include "dpll.h"
21 #include "regs.h"
22
23 /* Chip IDs for zl30731 */
24 static const u16 zl30731_ids[] = {
25 0x0E93,
26 0x1E93,
27 0x2E93,
28 };
29
30 const struct zl3073x_chip_info zl30731_chip_info = {
31 .ids = zl30731_ids,
32 .num_ids = ARRAY_SIZE(zl30731_ids),
33 .num_channels = 1,
34 };
35 EXPORT_SYMBOL_NS_GPL(zl30731_chip_info, "ZL3073X");
36
37 /* Chip IDs for zl30732 */
38 static const u16 zl30732_ids[] = {
39 0x0E30,
40 0x0E94,
41 0x1E94,
42 0x1F60,
43 0x2E94,
44 0x3FC4,
45 };
46
47 const struct zl3073x_chip_info zl30732_chip_info = {
48 .ids = zl30732_ids,
49 .num_ids = ARRAY_SIZE(zl30732_ids),
50 .num_channels = 2,
51 };
52 EXPORT_SYMBOL_NS_GPL(zl30732_chip_info, "ZL3073X");
53
54 /* Chip IDs for zl30733 */
55 static const u16 zl30733_ids[] = {
56 0x0E95,
57 0x1E95,
58 0x2E95,
59 };
60
61 const struct zl3073x_chip_info zl30733_chip_info = {
62 .ids = zl30733_ids,
63 .num_ids = ARRAY_SIZE(zl30733_ids),
64 .num_channels = 3,
65 };
66 EXPORT_SYMBOL_NS_GPL(zl30733_chip_info, "ZL3073X");
67
68 /* Chip IDs for zl30734 */
69 static const u16 zl30734_ids[] = {
70 0x0E96,
71 0x1E96,
72 0x2E96,
73 };
74
75 const struct zl3073x_chip_info zl30734_chip_info = {
76 .ids = zl30734_ids,
77 .num_ids = ARRAY_SIZE(zl30734_ids),
78 .num_channels = 4,
79 };
80 EXPORT_SYMBOL_NS_GPL(zl30734_chip_info, "ZL3073X");
81
82 /* Chip IDs for zl30735 */
83 static const u16 zl30735_ids[] = {
84 0x0E97,
85 0x1E97,
86 0x2E97,
87 };
88
89 const struct zl3073x_chip_info zl30735_chip_info = {
90 .ids = zl30735_ids,
91 .num_ids = ARRAY_SIZE(zl30735_ids),
92 .num_channels = 5,
93 };
94 EXPORT_SYMBOL_NS_GPL(zl30735_chip_info, "ZL3073X");
95
96 #define ZL_RANGE_OFFSET 0x80
97 #define ZL_PAGE_SIZE 0x80
98 #define ZL_NUM_PAGES 15
99 #define ZL_PAGE_SEL 0x7F
100 #define ZL_PAGE_SEL_MASK GENMASK(3, 0)
101 #define ZL_NUM_REGS (ZL_NUM_PAGES * ZL_PAGE_SIZE)
102
103 /* Regmap range configuration */
104 static const struct regmap_range_cfg zl3073x_regmap_range = {
105 .range_min = ZL_RANGE_OFFSET,
106 .range_max = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1,
107 .selector_reg = ZL_PAGE_SEL,
108 .selector_mask = ZL_PAGE_SEL_MASK,
109 .selector_shift = 0,
110 .window_start = 0,
111 .window_len = ZL_PAGE_SIZE,
112 };
113
114 static bool
zl3073x_is_volatile_reg(struct device * dev __maybe_unused,unsigned int reg)115 zl3073x_is_volatile_reg(struct device *dev __maybe_unused, unsigned int reg)
116 {
117 /* Only page selector is non-volatile */
118 return reg != ZL_PAGE_SEL;
119 }
120
121 const struct regmap_config zl3073x_regmap_config = {
122 .reg_bits = 8,
123 .val_bits = 8,
124 .max_register = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1,
125 .ranges = &zl3073x_regmap_range,
126 .num_ranges = 1,
127 .cache_type = REGCACHE_MAPLE,
128 .volatile_reg = zl3073x_is_volatile_reg,
129 };
130 EXPORT_SYMBOL_NS_GPL(zl3073x_regmap_config, "ZL3073X");
131
132 /**
133 * zl3073x_ref_freq_factorize - factorize given frequency
134 * @freq: input frequency
135 * @base: base frequency
136 * @mult: multiplier
137 *
138 * Checks if the given frequency can be factorized using one of the
139 * supported base frequencies. If so the base frequency and multiplier
140 * are stored into appropriate parameters if they are not NULL.
141 *
142 * Return: 0 on success, -EINVAL if the frequency cannot be factorized
143 */
144 int
zl3073x_ref_freq_factorize(u32 freq,u16 * base,u16 * mult)145 zl3073x_ref_freq_factorize(u32 freq, u16 *base, u16 *mult)
146 {
147 static const u16 base_freqs[] = {
148 1, 2, 4, 5, 8, 10, 16, 20, 25, 32, 40, 50, 64, 80, 100, 125,
149 128, 160, 200, 250, 256, 320, 400, 500, 625, 640, 800, 1000,
150 1250, 1280, 1600, 2000, 2500, 3125, 3200, 4000, 5000, 6250,
151 6400, 8000, 10000, 12500, 15625, 16000, 20000, 25000, 31250,
152 32000, 40000, 50000, 62500,
153 };
154 u32 div;
155 int i;
156
157 for (i = 0; i < ARRAY_SIZE(base_freqs); i++) {
158 div = freq / base_freqs[i];
159
160 if (div <= U16_MAX && (freq % base_freqs[i]) == 0) {
161 if (base)
162 *base = base_freqs[i];
163 if (mult)
164 *mult = div;
165
166 return 0;
167 }
168 }
169
170 return -EINVAL;
171 }
172
173 static bool
zl3073x_check_reg(struct zl3073x_dev * zldev,unsigned int reg,size_t size)174 zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size)
175 {
176 /* Check that multiop lock is held when accessing registers
177 * from page 10 and above.
178 */
179 if (ZL_REG_PAGE(reg) >= 10)
180 lockdep_assert_held(&zldev->multiop_lock);
181
182 /* Check the index is in valid range for indexed register */
183 if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) {
184 dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n",
185 ZL_REG_ADDR(reg));
186 return false;
187 }
188 /* Check the requested size corresponds to register size */
189 if (ZL_REG_SIZE(reg) != size) {
190 dev_err(zldev->dev, "Invalid size %zu for reg 0x%04lx\n",
191 size, ZL_REG_ADDR(reg));
192 return false;
193 }
194
195 return true;
196 }
197
198 static int
zl3073x_read_reg(struct zl3073x_dev * zldev,unsigned int reg,void * val,size_t size)199 zl3073x_read_reg(struct zl3073x_dev *zldev, unsigned int reg, void *val,
200 size_t size)
201 {
202 int rc;
203
204 if (!zl3073x_check_reg(zldev, reg, size))
205 return -EINVAL;
206
207 /* Map the register address to virtual range */
208 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
209
210 rc = regmap_bulk_read(zldev->regmap, reg, val, size);
211 if (rc) {
212 dev_err(zldev->dev, "Failed to read reg 0x%04x: %pe\n", reg,
213 ERR_PTR(rc));
214 return rc;
215 }
216
217 return 0;
218 }
219
220 static int
zl3073x_write_reg(struct zl3073x_dev * zldev,unsigned int reg,const void * val,size_t size)221 zl3073x_write_reg(struct zl3073x_dev *zldev, unsigned int reg, const void *val,
222 size_t size)
223 {
224 int rc;
225
226 if (!zl3073x_check_reg(zldev, reg, size))
227 return -EINVAL;
228
229 /* Map the register address to virtual range */
230 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
231
232 rc = regmap_bulk_write(zldev->regmap, reg, val, size);
233 if (rc) {
234 dev_err(zldev->dev, "Failed to write reg 0x%04x: %pe\n", reg,
235 ERR_PTR(rc));
236 return rc;
237 }
238
239 return 0;
240 }
241
242 /**
243 * zl3073x_read_u8 - read value from 8bit register
244 * @zldev: zl3073x device pointer
245 * @reg: register to write to
246 * @val: value to write
247 *
248 * Reads value from given 8bit register.
249 *
250 * Returns: 0 on success, <0 on error
251 */
zl3073x_read_u8(struct zl3073x_dev * zldev,unsigned int reg,u8 * val)252 int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val)
253 {
254 return zl3073x_read_reg(zldev, reg, val, sizeof(*val));
255 }
256
257 /**
258 * zl3073x_write_u8 - write value to 16bit register
259 * @zldev: zl3073x device pointer
260 * @reg: register to write to
261 * @val: value to write
262 *
263 * Writes value into given 8bit register.
264 *
265 * Returns: 0 on success, <0 on error
266 */
zl3073x_write_u8(struct zl3073x_dev * zldev,unsigned int reg,u8 val)267 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val)
268 {
269 return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
270 }
271
272 /**
273 * zl3073x_read_u16 - read value from 16bit register
274 * @zldev: zl3073x device pointer
275 * @reg: register to write to
276 * @val: value to write
277 *
278 * Reads value from given 16bit register.
279 *
280 * Returns: 0 on success, <0 on error
281 */
zl3073x_read_u16(struct zl3073x_dev * zldev,unsigned int reg,u16 * val)282 int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val)
283 {
284 int rc;
285
286 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val));
287 if (!rc)
288 be16_to_cpus(val);
289
290 return rc;
291 }
292
293 /**
294 * zl3073x_write_u16 - write value to 16bit register
295 * @zldev: zl3073x device pointer
296 * @reg: register to write to
297 * @val: value to write
298 *
299 * Writes value into given 16bit register.
300 *
301 * Returns: 0 on success, <0 on error
302 */
zl3073x_write_u16(struct zl3073x_dev * zldev,unsigned int reg,u16 val)303 int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val)
304 {
305 cpu_to_be16s(&val);
306
307 return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
308 }
309
310 /**
311 * zl3073x_read_u32 - read value from 32bit register
312 * @zldev: zl3073x device pointer
313 * @reg: register to write to
314 * @val: value to write
315 *
316 * Reads value from given 32bit register.
317 *
318 * Returns: 0 on success, <0 on error
319 */
zl3073x_read_u32(struct zl3073x_dev * zldev,unsigned int reg,u32 * val)320 int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val)
321 {
322 int rc;
323
324 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val));
325 if (!rc)
326 be32_to_cpus(val);
327
328 return rc;
329 }
330
331 /**
332 * zl3073x_write_u32 - write value to 32bit register
333 * @zldev: zl3073x device pointer
334 * @reg: register to write to
335 * @val: value to write
336 *
337 * Writes value into given 32bit register.
338 *
339 * Returns: 0 on success, <0 on error
340 */
zl3073x_write_u32(struct zl3073x_dev * zldev,unsigned int reg,u32 val)341 int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val)
342 {
343 cpu_to_be32s(&val);
344
345 return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
346 }
347
348 /**
349 * zl3073x_read_u48 - read value from 48bit register
350 * @zldev: zl3073x device pointer
351 * @reg: register to write to
352 * @val: value to write
353 *
354 * Reads value from given 48bit register.
355 *
356 * Returns: 0 on success, <0 on error
357 */
zl3073x_read_u48(struct zl3073x_dev * zldev,unsigned int reg,u64 * val)358 int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val)
359 {
360 u8 buf[6];
361 int rc;
362
363 rc = zl3073x_read_reg(zldev, reg, buf, sizeof(buf));
364 if (!rc)
365 *val = get_unaligned_be48(buf);
366
367 return rc;
368 }
369
370 /**
371 * zl3073x_write_u48 - write value to 48bit register
372 * @zldev: zl3073x device pointer
373 * @reg: register to write to
374 * @val: value to write
375 *
376 * Writes value into given 48bit register.
377 * The value must be from the interval -S48_MIN to U48_MAX.
378 *
379 * Returns: 0 on success, <0 on error
380 */
zl3073x_write_u48(struct zl3073x_dev * zldev,unsigned int reg,u64 val)381 int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val)
382 {
383 u8 buf[6];
384
385 /* Check the value belongs to <S48_MIN, U48_MAX>
386 * Any value >= S48_MIN has bits 47..63 set.
387 */
388 if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) {
389 dev_err(zldev->dev, "Value 0x%0llx out of range\n", val);
390 return -EINVAL;
391 }
392
393 put_unaligned_be48(val, buf);
394
395 return zl3073x_write_reg(zldev, reg, buf, sizeof(buf));
396 }
397
398 /**
399 * zl3073x_poll_zero_u8 - wait for register to be cleared by device
400 * @zldev: zl3073x device pointer
401 * @reg: register to poll (has to be 8bit register)
402 * @mask: bit mask for polling
403 *
404 * Waits for bits specified by @mask in register @reg value to be cleared
405 * by the device.
406 *
407 * Returns: 0 on success, <0 on error
408 */
zl3073x_poll_zero_u8(struct zl3073x_dev * zldev,unsigned int reg,u8 mask)409 int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask)
410 {
411 /* Register polling sleep & timeout */
412 #define ZL_POLL_SLEEP_US 10
413 #define ZL_POLL_TIMEOUT_US 2000000
414 unsigned int val;
415
416 /* Check the register is 8bit */
417 if (ZL_REG_SIZE(reg) != 1) {
418 dev_err(zldev->dev, "Invalid reg 0x%04lx size for polling\n",
419 ZL_REG_ADDR(reg));
420 return -EINVAL;
421 }
422
423 /* Map the register address to virtual range */
424 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
425
426 return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask),
427 ZL_POLL_SLEEP_US, ZL_POLL_TIMEOUT_US);
428 }
429
zl3073x_mb_op(struct zl3073x_dev * zldev,unsigned int op_reg,u8 op_val,unsigned int mask_reg,u16 mask_val)430 int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,
431 unsigned int mask_reg, u16 mask_val)
432 {
433 int rc;
434
435 /* Set mask for the operation */
436 rc = zl3073x_write_u16(zldev, mask_reg, mask_val);
437 if (rc)
438 return rc;
439
440 /* Trigger the operation */
441 rc = zl3073x_write_u8(zldev, op_reg, op_val);
442 if (rc)
443 return rc;
444
445 /* Wait for the operation to actually finish */
446 return zl3073x_poll_zero_u8(zldev, op_reg, op_val);
447 }
448
449 /**
450 * zl3073x_ref_state_fetch - get input reference state
451 * @zldev: pointer to zl3073x_dev structure
452 * @index: input reference index to fetch state for
453 *
454 * Function fetches information for the given input reference that are
455 * invariant and stores them for later use.
456 *
457 * Return: 0 on success, <0 on error
458 */
459 static int
zl3073x_ref_state_fetch(struct zl3073x_dev * zldev,u8 index)460 zl3073x_ref_state_fetch(struct zl3073x_dev *zldev, u8 index)
461 {
462 struct zl3073x_ref *input = &zldev->ref[index];
463 u8 ref_config;
464 int rc;
465
466 /* If the input is differential then the configuration for N-pin
467 * reference is ignored and P-pin config is used for both.
468 */
469 if (zl3073x_is_n_pin(index) &&
470 zl3073x_ref_is_diff(zldev, index - 1)) {
471 input->enabled = zl3073x_ref_is_enabled(zldev, index - 1);
472 input->diff = true;
473
474 return 0;
475 }
476
477 guard(mutex)(&zldev->multiop_lock);
478
479 /* Read reference configuration */
480 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
481 ZL_REG_REF_MB_MASK, BIT(index));
482 if (rc)
483 return rc;
484
485 /* Read ref_config register */
486 rc = zl3073x_read_u8(zldev, ZL_REG_REF_CONFIG, &ref_config);
487 if (rc)
488 return rc;
489
490 input->enabled = FIELD_GET(ZL_REF_CONFIG_ENABLE, ref_config);
491 input->diff = FIELD_GET(ZL_REF_CONFIG_DIFF_EN, ref_config);
492
493 dev_dbg(zldev->dev, "REF%u is %s and configured as %s\n", index,
494 str_enabled_disabled(input->enabled),
495 input->diff ? "differential" : "single-ended");
496
497 return rc;
498 }
499
500 /**
501 * zl3073x_out_state_fetch - get output state
502 * @zldev: pointer to zl3073x_dev structure
503 * @index: output index to fetch state for
504 *
505 * Function fetches information for the given output (not output pin)
506 * that are invariant and stores them for later use.
507 *
508 * Return: 0 on success, <0 on error
509 */
510 static int
zl3073x_out_state_fetch(struct zl3073x_dev * zldev,u8 index)511 zl3073x_out_state_fetch(struct zl3073x_dev *zldev, u8 index)
512 {
513 struct zl3073x_out *out = &zldev->out[index];
514 u8 output_ctrl, output_mode;
515 int rc;
516
517 /* Read output configuration */
518 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_CTRL(index), &output_ctrl);
519 if (rc)
520 return rc;
521
522 /* Store info about output enablement and synthesizer the output
523 * is connected to.
524 */
525 out->enabled = FIELD_GET(ZL_OUTPUT_CTRL_EN, output_ctrl);
526 out->synth = FIELD_GET(ZL_OUTPUT_CTRL_SYNTH_SEL, output_ctrl);
527
528 dev_dbg(zldev->dev, "OUT%u is %s and connected to SYNTH%u\n", index,
529 str_enabled_disabled(out->enabled), out->synth);
530
531 guard(mutex)(&zldev->multiop_lock);
532
533 /* Read output configuration */
534 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
535 ZL_REG_OUTPUT_MB_MASK, BIT(index));
536 if (rc)
537 return rc;
538
539 /* Read output_mode */
540 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode);
541 if (rc)
542 return rc;
543
544 /* Extract and store output signal format */
545 out->signal_format = FIELD_GET(ZL_OUTPUT_MODE_SIGNAL_FORMAT,
546 output_mode);
547
548 dev_dbg(zldev->dev, "OUT%u has signal format 0x%02x\n", index,
549 out->signal_format);
550
551 return rc;
552 }
553
554 /**
555 * zl3073x_synth_state_fetch - get synth state
556 * @zldev: pointer to zl3073x_dev structure
557 * @index: synth index to fetch state for
558 *
559 * Function fetches information for the given synthesizer that are
560 * invariant and stores them for later use.
561 *
562 * Return: 0 on success, <0 on error
563 */
564 static int
zl3073x_synth_state_fetch(struct zl3073x_dev * zldev,u8 index)565 zl3073x_synth_state_fetch(struct zl3073x_dev *zldev, u8 index)
566 {
567 struct zl3073x_synth *synth = &zldev->synth[index];
568 u16 base, m, n;
569 u8 synth_ctrl;
570 u32 mult;
571 int rc;
572
573 /* Read synth control register */
574 rc = zl3073x_read_u8(zldev, ZL_REG_SYNTH_CTRL(index), &synth_ctrl);
575 if (rc)
576 return rc;
577
578 /* Store info about synth enablement and DPLL channel the synth is
579 * driven by.
580 */
581 synth->enabled = FIELD_GET(ZL_SYNTH_CTRL_EN, synth_ctrl);
582 synth->dpll = FIELD_GET(ZL_SYNTH_CTRL_DPLL_SEL, synth_ctrl);
583
584 dev_dbg(zldev->dev, "SYNTH%u is %s and driven by DPLL%u\n", index,
585 str_enabled_disabled(synth->enabled), synth->dpll);
586
587 guard(mutex)(&zldev->multiop_lock);
588
589 /* Read synth configuration */
590 rc = zl3073x_mb_op(zldev, ZL_REG_SYNTH_MB_SEM, ZL_SYNTH_MB_SEM_RD,
591 ZL_REG_SYNTH_MB_MASK, BIT(index));
592 if (rc)
593 return rc;
594
595 /* The output frequency is determined by the following formula:
596 * base * multiplier * numerator / denominator
597 *
598 * Read registers with these values
599 */
600 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_BASE, &base);
601 if (rc)
602 return rc;
603
604 rc = zl3073x_read_u32(zldev, ZL_REG_SYNTH_FREQ_MULT, &mult);
605 if (rc)
606 return rc;
607
608 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_M, &m);
609 if (rc)
610 return rc;
611
612 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_N, &n);
613 if (rc)
614 return rc;
615
616 /* Check denominator for zero to avoid div by 0 */
617 if (!n) {
618 dev_err(zldev->dev,
619 "Zero divisor for SYNTH%u retrieved from device\n",
620 index);
621 return -EINVAL;
622 }
623
624 /* Compute and store synth frequency */
625 zldev->synth[index].freq = div_u64(mul_u32_u32(base * m, mult), n);
626
627 dev_dbg(zldev->dev, "SYNTH%u frequency: %u Hz\n", index,
628 zldev->synth[index].freq);
629
630 return rc;
631 }
632
633 static int
zl3073x_dev_state_fetch(struct zl3073x_dev * zldev)634 zl3073x_dev_state_fetch(struct zl3073x_dev *zldev)
635 {
636 int rc;
637 u8 i;
638
639 for (i = 0; i < ZL3073X_NUM_REFS; i++) {
640 rc = zl3073x_ref_state_fetch(zldev, i);
641 if (rc) {
642 dev_err(zldev->dev,
643 "Failed to fetch input state: %pe\n",
644 ERR_PTR(rc));
645 return rc;
646 }
647 }
648
649 for (i = 0; i < ZL3073X_NUM_SYNTHS; i++) {
650 rc = zl3073x_synth_state_fetch(zldev, i);
651 if (rc) {
652 dev_err(zldev->dev,
653 "Failed to fetch synth state: %pe\n",
654 ERR_PTR(rc));
655 return rc;
656 }
657 }
658
659 for (i = 0; i < ZL3073X_NUM_OUTS; i++) {
660 rc = zl3073x_out_state_fetch(zldev, i);
661 if (rc) {
662 dev_err(zldev->dev,
663 "Failed to fetch output state: %pe\n",
664 ERR_PTR(rc));
665 return rc;
666 }
667 }
668
669 return rc;
670 }
671
672 /**
673 * zl3073x_ref_phase_offsets_update - update reference phase offsets
674 * @zldev: pointer to zl3073x_dev structure
675 * @channel: DPLL channel number or -1
676 *
677 * The function asks device to update phase offsets latch registers with
678 * the latest measured values. There are 2 sets of latch registers:
679 *
680 * 1) Up to 5 DPLL-to-connected-ref registers that contain phase offset
681 * values between particular DPLL channel and its *connected* input
682 * reference.
683 *
684 * 2) 10 selected-DPLL-to-all-ref registers that contain phase offset values
685 * between selected DPLL channel and all input references.
686 *
687 * If the caller is interested in 2) then it has to pass DPLL channel number
688 * in @channel parameter. If it is interested only in 1) then it should pass
689 * @channel parameter with value of -1.
690 *
691 * Return: 0 on success, <0 on error
692 */
zl3073x_ref_phase_offsets_update(struct zl3073x_dev * zldev,int channel)693 int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel)
694 {
695 int rc;
696
697 /* Per datasheet we have to wait for 'dpll_ref_phase_err_rqst_rd'
698 * to be zero to ensure that the measured data are coherent.
699 */
700 rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
701 ZL_REF_PHASE_ERR_READ_RQST_RD);
702 if (rc)
703 return rc;
704
705 /* Select DPLL channel if it is specified */
706 if (channel != -1) {
707 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel);
708 if (rc)
709 return rc;
710 }
711
712 /* Request to update phase offsets measurement values */
713 rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
714 ZL_REF_PHASE_ERR_READ_RQST_RD);
715 if (rc)
716 return rc;
717
718 /* Wait for finish */
719 return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
720 ZL_REF_PHASE_ERR_READ_RQST_RD);
721 }
722
723 /**
724 * zl3073x_ref_ffo_update - update reference fractional frequency offsets
725 * @zldev: pointer to zl3073x_dev structure
726 *
727 * The function asks device to update fractional frequency offsets latch
728 * registers the latest measured values, reads and stores them into
729 *
730 * Return: 0 on success, <0 on error
731 */
732 static int
zl3073x_ref_ffo_update(struct zl3073x_dev * zldev)733 zl3073x_ref_ffo_update(struct zl3073x_dev *zldev)
734 {
735 int i, rc;
736
737 /* Per datasheet we have to wait for 'ref_freq_meas_ctrl' to be zero
738 * to ensure that the measured data are coherent.
739 */
740 rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
741 ZL_REF_FREQ_MEAS_CTRL);
742 if (rc)
743 return rc;
744
745 /* Select all references for measurement */
746 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0,
747 GENMASK(7, 0)); /* REF0P..REF3N */
748 if (rc)
749 return rc;
750 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4,
751 GENMASK(1, 0)); /* REF4P..REF4N */
752 if (rc)
753 return rc;
754
755 /* Request frequency offset measurement */
756 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
757 ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF);
758 if (rc)
759 return rc;
760
761 /* Wait for finish */
762 rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
763 ZL_REF_FREQ_MEAS_CTRL);
764 if (rc)
765 return rc;
766
767 /* Read DPLL-to-REFx frequency offset measurements */
768 for (i = 0; i < ZL3073X_NUM_REFS; i++) {
769 s32 value;
770
771 /* Read value stored in units of 2^-32 signed */
772 rc = zl3073x_read_u32(zldev, ZL_REG_REF_FREQ(i), &value);
773 if (rc)
774 return rc;
775
776 /* Convert to ppm -> ffo = (10^6 * value) / 2^32 */
777 zldev->ref[i].ffo = mul_s64_u64_shr(value, 1000000, 32);
778 }
779
780 return 0;
781 }
782
783 static void
zl3073x_dev_periodic_work(struct kthread_work * work)784 zl3073x_dev_periodic_work(struct kthread_work *work)
785 {
786 struct zl3073x_dev *zldev = container_of(work, struct zl3073x_dev,
787 work.work);
788 struct zl3073x_dpll *zldpll;
789 int rc;
790
791 /* Update DPLL-to-connected-ref phase offsets registers */
792 rc = zl3073x_ref_phase_offsets_update(zldev, -1);
793 if (rc)
794 dev_warn(zldev->dev, "Failed to update phase offsets: %pe\n",
795 ERR_PTR(rc));
796
797 /* Update references' fractional frequency offsets */
798 rc = zl3073x_ref_ffo_update(zldev);
799 if (rc)
800 dev_warn(zldev->dev,
801 "Failed to update fractional frequency offsets: %pe\n",
802 ERR_PTR(rc));
803
804 list_for_each_entry(zldpll, &zldev->dplls, list)
805 zl3073x_dpll_changes_check(zldpll);
806
807 /* Run twice a second */
808 kthread_queue_delayed_work(zldev->kworker, &zldev->work,
809 msecs_to_jiffies(500));
810 }
811
zl3073x_dev_dpll_fini(void * ptr)812 static void zl3073x_dev_dpll_fini(void *ptr)
813 {
814 struct zl3073x_dpll *zldpll, *next;
815 struct zl3073x_dev *zldev = ptr;
816
817 /* Stop monitoring thread */
818 if (zldev->kworker) {
819 kthread_cancel_delayed_work_sync(&zldev->work);
820 kthread_destroy_worker(zldev->kworker);
821 zldev->kworker = NULL;
822 }
823
824 /* Release DPLLs */
825 list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) {
826 zl3073x_dpll_unregister(zldpll);
827 list_del(&zldpll->list);
828 zl3073x_dpll_free(zldpll);
829 }
830 }
831
832 static int
zl3073x_devm_dpll_init(struct zl3073x_dev * zldev,u8 num_dplls)833 zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls)
834 {
835 struct kthread_worker *kworker;
836 struct zl3073x_dpll *zldpll;
837 unsigned int i;
838 int rc;
839
840 INIT_LIST_HEAD(&zldev->dplls);
841
842 /* Initialize all DPLLs */
843 for (i = 0; i < num_dplls; i++) {
844 zldpll = zl3073x_dpll_alloc(zldev, i);
845 if (IS_ERR(zldpll)) {
846 dev_err_probe(zldev->dev, PTR_ERR(zldpll),
847 "Failed to alloc DPLL%u\n", i);
848 rc = PTR_ERR(zldpll);
849 goto error;
850 }
851
852 rc = zl3073x_dpll_register(zldpll);
853 if (rc) {
854 dev_err_probe(zldev->dev, rc,
855 "Failed to register DPLL%u\n", i);
856 zl3073x_dpll_free(zldpll);
857 goto error;
858 }
859
860 list_add_tail(&zldpll->list, &zldev->dplls);
861 }
862
863 /* Perform initial firmware fine phase correction */
864 rc = zl3073x_dpll_init_fine_phase_adjust(zldev);
865 if (rc) {
866 dev_err_probe(zldev->dev, rc,
867 "Failed to init fine phase correction\n");
868 goto error;
869 }
870
871 /* Initialize monitoring thread */
872 kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work);
873 kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev));
874 if (IS_ERR(kworker)) {
875 rc = PTR_ERR(kworker);
876 goto error;
877 }
878
879 zldev->kworker = kworker;
880 kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0);
881
882 /* Add devres action to release DPLL related resources */
883 rc = devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev);
884 if (rc)
885 goto error;
886
887 return 0;
888
889 error:
890 zl3073x_dev_dpll_fini(zldev);
891
892 return rc;
893 }
894
895 /**
896 * zl3073x_dev_phase_meas_setup - setup phase offset measurement
897 * @zldev: pointer to zl3073x_dev structure
898 * @num_channels: number of DPLL channels
899 *
900 * Enable phase offset measurement block, set measurement averaging factor
901 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
902 *
903 * Returns: 0 on success, <0 on error
904 */
905 static int
zl3073x_dev_phase_meas_setup(struct zl3073x_dev * zldev,int num_channels)906 zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev, int num_channels)
907 {
908 u8 dpll_meas_ctrl, mask;
909 int i, rc;
910
911 /* Read DPLL phase measurement control register */
912 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl);
913 if (rc)
914 return rc;
915
916 /* Setup phase measurement averaging factor */
917 dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR;
918 dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3);
919
920 /* Enable DPLL measurement block */
921 dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN;
922
923 /* Update phase measurement control register */
924 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
925 if (rc)
926 return rc;
927
928 /* Enable DPLL-to-connected-ref measurement for each channel */
929 for (i = 0, mask = 0; i < num_channels; i++)
930 mask |= BIT(i);
931
932 return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask);
933 }
934
935 /**
936 * zl3073x_dev_probe - initialize zl3073x device
937 * @zldev: pointer to zl3073x device
938 * @chip_info: chip info based on compatible
939 *
940 * Common initialization of zl3073x device structure.
941 *
942 * Returns: 0 on success, <0 on error
943 */
zl3073x_dev_probe(struct zl3073x_dev * zldev,const struct zl3073x_chip_info * chip_info)944 int zl3073x_dev_probe(struct zl3073x_dev *zldev,
945 const struct zl3073x_chip_info *chip_info)
946 {
947 u16 id, revision, fw_ver;
948 unsigned int i;
949 u32 cfg_ver;
950 int rc;
951
952 /* Read chip ID */
953 rc = zl3073x_read_u16(zldev, ZL_REG_ID, &id);
954 if (rc)
955 return rc;
956
957 /* Check it matches */
958 for (i = 0; i < chip_info->num_ids; i++) {
959 if (id == chip_info->ids[i])
960 break;
961 }
962
963 if (i == chip_info->num_ids) {
964 return dev_err_probe(zldev->dev, -ENODEV,
965 "Unknown or non-match chip ID: 0x%0x\n",
966 id);
967 }
968
969 /* Read revision, firmware version and custom config version */
970 rc = zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision);
971 if (rc)
972 return rc;
973 rc = zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver);
974 if (rc)
975 return rc;
976 rc = zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver);
977 if (rc)
978 return rc;
979
980 dev_dbg(zldev->dev, "ChipID(%X), ChipRev(%X), FwVer(%u)\n", id,
981 revision, fw_ver);
982 dev_dbg(zldev->dev, "Custom config version: %lu.%lu.%lu.%lu\n",
983 FIELD_GET(GENMASK(31, 24), cfg_ver),
984 FIELD_GET(GENMASK(23, 16), cfg_ver),
985 FIELD_GET(GENMASK(15, 8), cfg_ver),
986 FIELD_GET(GENMASK(7, 0), cfg_ver));
987
988 /* Generate random clock ID as the device has not such property that
989 * could be used for this purpose. A user can later change this value
990 * using devlink.
991 */
992 zldev->clock_id = get_random_u64();
993
994 /* Initialize mutex for operations where multiple reads, writes
995 * and/or polls are required to be done atomically.
996 */
997 rc = devm_mutex_init(zldev->dev, &zldev->multiop_lock);
998 if (rc)
999 return dev_err_probe(zldev->dev, rc,
1000 "Failed to initialize mutex\n");
1001
1002 /* Fetch device state */
1003 rc = zl3073x_dev_state_fetch(zldev);
1004 if (rc)
1005 return rc;
1006
1007 /* Setup phase offset measurement block */
1008 rc = zl3073x_dev_phase_meas_setup(zldev, chip_info->num_channels);
1009 if (rc)
1010 return dev_err_probe(zldev->dev, rc,
1011 "Failed to setup phase measurement\n");
1012
1013 /* Register DPLL channels */
1014 rc = zl3073x_devm_dpll_init(zldev, chip_info->num_channels);
1015 if (rc)
1016 return rc;
1017
1018 /* Register the devlink instance and parameters */
1019 rc = zl3073x_devlink_register(zldev);
1020 if (rc)
1021 return dev_err_probe(zldev->dev, rc,
1022 "Failed to register devlink instance\n");
1023
1024 return 0;
1025 }
1026 EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X");
1027
1028 MODULE_AUTHOR("Ivan Vecera <ivecera@redhat.com>");
1029 MODULE_DESCRIPTION("Microchip ZL3073x core driver");
1030 MODULE_LICENSE("GPL");
1031