1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28 #include <linux/list_sort.h>
29 #include <linux/pci.h>
30 #include <linux/uaccess.h>
31
32 #include <drm/drm_device.h>
33 #include <drm/drm_file.h>
34 #include <drm/radeon_drm.h>
35
36 #include "radeon.h"
37 #include "radeon_reg.h"
38 #include "radeon_trace.h"
39
40 #define RADEON_CS_MAX_PRIORITY 32u
41 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
42
43 /* This is based on the bucket sort with O(n) time complexity.
44 * An item with priority "i" is added to bucket[i]. The lists are then
45 * concatenated in descending order.
46 */
47 struct radeon_cs_buckets {
48 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
49 };
50
radeon_cs_buckets_init(struct radeon_cs_buckets * b)51 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
52 {
53 unsigned i;
54
55 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
56 INIT_LIST_HEAD(&b->bucket[i]);
57 }
58
radeon_cs_buckets_add(struct radeon_cs_buckets * b,struct list_head * item,unsigned priority)59 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
60 struct list_head *item, unsigned priority)
61 {
62 /* Since buffers which appear sooner in the relocation list are
63 * likely to be used more often than buffers which appear later
64 * in the list, the sort mustn't change the ordering of buffers
65 * with the same priority, i.e. it must be stable.
66 */
67 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
68 }
69
radeon_cs_buckets_get_list(struct radeon_cs_buckets * b,struct list_head * out_list)70 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
71 struct list_head *out_list)
72 {
73 unsigned i;
74
75 /* Connect the sorted buckets in the output list. */
76 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
77 list_splice(&b->bucket[i], out_list);
78 }
79 }
80
radeon_cs_parser_relocs(struct radeon_cs_parser * p)81 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
82 {
83 struct radeon_cs_chunk *chunk;
84 struct radeon_cs_buckets buckets;
85 unsigned i;
86 bool need_mmap_lock = false;
87 int r;
88
89 if (p->chunk_relocs == NULL) {
90 return 0;
91 }
92 chunk = p->chunk_relocs;
93 p->dma_reloc_idx = 0;
94 /* FIXME: we assume that each relocs use 4 dwords */
95 p->nrelocs = chunk->length_dw / 4;
96 p->relocs = kvzalloc_objs(struct radeon_bo_list, p->nrelocs);
97 if (p->relocs == NULL) {
98 return -ENOMEM;
99 }
100
101 radeon_cs_buckets_init(&buckets);
102
103 for (i = 0; i < p->nrelocs; i++) {
104 struct drm_radeon_cs_reloc *r;
105 struct drm_gem_object *gobj;
106 unsigned priority;
107
108 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
109 gobj = drm_gem_object_lookup(p->filp, r->handle);
110 if (gobj == NULL) {
111 DRM_ERROR("gem object lookup failed 0x%x\n",
112 r->handle);
113 return -ENOENT;
114 }
115 p->relocs[i].robj = gem_to_radeon_bo(gobj);
116
117 /* The userspace buffer priorities are from 0 to 15. A higher
118 * number means the buffer is more important.
119 * Also, the buffers used for write have a higher priority than
120 * the buffers used for read only, which doubles the range
121 * to 0 to 31. 32 is reserved for the kernel driver.
122 */
123 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
124 + !!r->write_domain;
125
126 /* The first reloc of an UVD job is the msg and that must be in
127 * VRAM, the second reloc is the DPB and for WMV that must be in
128 * VRAM as well. Also put everything into VRAM on AGP cards and older
129 * IGP chips to avoid image corruptions
130 */
131 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
132 (i <= 0 || pci_find_capability(p->rdev->pdev, PCI_CAP_ID_AGP) ||
133 p->rdev->family == CHIP_RS780 ||
134 p->rdev->family == CHIP_RS880)) {
135
136 /* TODO: is this still needed for NI+ ? */
137 p->relocs[i].preferred_domains =
138 RADEON_GEM_DOMAIN_VRAM;
139
140 p->relocs[i].allowed_domains =
141 RADEON_GEM_DOMAIN_VRAM;
142
143 /* prioritize this over any other relocation */
144 priority = RADEON_CS_MAX_PRIORITY;
145 } else {
146 uint32_t domain = r->write_domain ?
147 r->write_domain : r->read_domains;
148
149 if (domain & RADEON_GEM_DOMAIN_CPU) {
150 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
151 "for command submission\n");
152 return -EINVAL;
153 }
154
155 p->relocs[i].preferred_domains = domain;
156 if (domain == RADEON_GEM_DOMAIN_VRAM)
157 domain |= RADEON_GEM_DOMAIN_GTT;
158 p->relocs[i].allowed_domains = domain;
159 }
160
161 if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) {
162 uint32_t domain = p->relocs[i].preferred_domains;
163 if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
164 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
165 "allowed for userptr BOs\n");
166 return -EINVAL;
167 }
168 need_mmap_lock = true;
169 domain = RADEON_GEM_DOMAIN_GTT;
170 p->relocs[i].preferred_domains = domain;
171 p->relocs[i].allowed_domains = domain;
172 }
173
174 /* Objects shared as dma-bufs cannot be moved to VRAM */
175 if (p->relocs[i].robj->prime_shared_count) {
176 p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
177 if (!p->relocs[i].allowed_domains) {
178 DRM_ERROR("BO associated with dma-buf cannot "
179 "be moved to VRAM\n");
180 return -EINVAL;
181 }
182 }
183
184 p->relocs[i].shared = !r->write_domain;
185 radeon_cs_buckets_add(&buckets, &p->relocs[i].list, priority);
186 }
187
188 radeon_cs_buckets_get_list(&buckets, &p->validated);
189
190 if (p->cs_flags & RADEON_CS_USE_VM)
191 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
192 &p->validated);
193 if (need_mmap_lock)
194 mmap_read_lock(current->mm);
195
196 r = radeon_bo_list_validate(p->rdev, &p->exec, &p->validated, p->ring);
197
198 if (need_mmap_lock)
199 mmap_read_unlock(current->mm);
200
201 return r;
202 }
203
radeon_cs_get_ring(struct radeon_cs_parser * p,u32 ring,s32 priority)204 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
205 {
206 p->priority = priority;
207
208 switch (ring) {
209 default:
210 DRM_ERROR("unknown ring id: %d\n", ring);
211 return -EINVAL;
212 case RADEON_CS_RING_GFX:
213 p->ring = RADEON_RING_TYPE_GFX_INDEX;
214 break;
215 case RADEON_CS_RING_COMPUTE:
216 if (p->rdev->family >= CHIP_TAHITI) {
217 if (p->priority > 0)
218 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
219 else
220 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
221 } else
222 p->ring = RADEON_RING_TYPE_GFX_INDEX;
223 break;
224 case RADEON_CS_RING_DMA:
225 if (p->rdev->family >= CHIP_CAYMAN) {
226 if (p->priority > 0)
227 p->ring = R600_RING_TYPE_DMA_INDEX;
228 else
229 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
230 } else if (p->rdev->family >= CHIP_RV770) {
231 p->ring = R600_RING_TYPE_DMA_INDEX;
232 } else {
233 return -EINVAL;
234 }
235 break;
236 case RADEON_CS_RING_UVD:
237 p->ring = R600_RING_TYPE_UVD_INDEX;
238 break;
239 case RADEON_CS_RING_VCE:
240 /* TODO: only use the low priority ring for now */
241 p->ring = TN_RING_TYPE_VCE1_INDEX;
242 break;
243 }
244 return 0;
245 }
246
radeon_cs_sync_rings(struct radeon_cs_parser * p)247 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
248 {
249 struct radeon_bo_list *reloc;
250 int r;
251
252 list_for_each_entry(reloc, &p->validated, list) {
253 struct dma_resv *resv;
254
255 resv = reloc->robj->tbo.base.resv;
256 r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, reloc->shared);
257 if (r)
258 return r;
259 }
260 return 0;
261 }
262
263 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
radeon_cs_parser_init(struct radeon_cs_parser * p,void * data)264 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
265 {
266 struct drm_radeon_cs *cs = data;
267 uint64_t *chunk_array_ptr;
268 u64 size;
269 unsigned i;
270 u32 ring = RADEON_CS_RING_GFX;
271 s32 priority = 0;
272
273 INIT_LIST_HEAD(&p->validated);
274 drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
275
276 if (!cs->num_chunks) {
277 return 0;
278 }
279
280 /* get chunks */
281 p->idx = 0;
282 p->ib.sa_bo = NULL;
283 p->const_ib.sa_bo = NULL;
284 p->chunk_ib = NULL;
285 p->chunk_relocs = NULL;
286 p->chunk_flags = NULL;
287 p->chunk_const_ib = NULL;
288 p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
289 if (p->chunks_array == NULL) {
290 return -ENOMEM;
291 }
292 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
293 if (copy_from_user(p->chunks_array, chunk_array_ptr,
294 sizeof(uint64_t)*cs->num_chunks)) {
295 return -EFAULT;
296 }
297 p->cs_flags = 0;
298 p->nchunks = cs->num_chunks;
299 p->chunks = kvzalloc_objs(struct radeon_cs_chunk, p->nchunks);
300 if (p->chunks == NULL) {
301 return -ENOMEM;
302 }
303 for (i = 0; i < p->nchunks; i++) {
304 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
305 struct drm_radeon_cs_chunk user_chunk;
306 uint32_t __user *cdata;
307
308 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
309 if (copy_from_user(&user_chunk, chunk_ptr,
310 sizeof(struct drm_radeon_cs_chunk))) {
311 return -EFAULT;
312 }
313 p->chunks[i].length_dw = user_chunk.length_dw;
314 if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
315 p->chunk_relocs = &p->chunks[i];
316 }
317 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
318 p->chunk_ib = &p->chunks[i];
319 /* zero length IB isn't useful */
320 if (p->chunks[i].length_dw == 0)
321 return -EINVAL;
322 }
323 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
324 p->chunk_const_ib = &p->chunks[i];
325 /* zero length CONST IB isn't useful */
326 if (p->chunks[i].length_dw == 0)
327 return -EINVAL;
328 }
329 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
330 p->chunk_flags = &p->chunks[i];
331 /* zero length flags aren't useful */
332 if (p->chunks[i].length_dw == 0)
333 return -EINVAL;
334 }
335
336 size = p->chunks[i].length_dw;
337 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
338 p->chunks[i].user_ptr = cdata;
339 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
340 continue;
341
342 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
343 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
344 continue;
345 }
346
347 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
348 size *= sizeof(uint32_t);
349 if (p->chunks[i].kdata == NULL) {
350 return -ENOMEM;
351 }
352 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
353 return -EFAULT;
354 }
355 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
356 p->cs_flags = p->chunks[i].kdata[0];
357 if (p->chunks[i].length_dw > 1)
358 ring = p->chunks[i].kdata[1];
359 if (p->chunks[i].length_dw > 2)
360 priority = (s32)p->chunks[i].kdata[2];
361 }
362 }
363
364 /* these are KMS only */
365 if (p->rdev) {
366 if ((p->cs_flags & RADEON_CS_USE_VM) &&
367 !p->rdev->vm_manager.enabled) {
368 DRM_ERROR("VM not active on asic!\n");
369 return -EINVAL;
370 }
371
372 if (radeon_cs_get_ring(p, ring, priority))
373 return -EINVAL;
374
375 /* we only support VM on some SI+ rings */
376 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
377 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
378 DRM_ERROR("Ring %d requires VM!\n", p->ring);
379 return -EINVAL;
380 }
381 } else {
382 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
383 DRM_ERROR("VM not supported on ring %d!\n",
384 p->ring);
385 return -EINVAL;
386 }
387 }
388 }
389
390 return 0;
391 }
392
cmp_size_smaller_first(void * priv,const struct list_head * a,const struct list_head * b)393 static int cmp_size_smaller_first(void *priv, const struct list_head *a,
394 const struct list_head *b)
395 {
396 struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, list);
397 struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, list);
398
399 /* Sort A before B if A is smaller. */
400 if (la->robj->tbo.base.size > lb->robj->tbo.base.size)
401 return 1;
402 if (la->robj->tbo.base.size < lb->robj->tbo.base.size)
403 return -1;
404 return 0;
405 }
406
407 /**
408 * radeon_cs_parser_fini() - clean parser states
409 * @parser: parser structure holding parsing context.
410 * @error: error number
411 *
412 * If error is set than unvalidate buffer, otherwise just free memory
413 * used by parsing context.
414 **/
radeon_cs_parser_fini(struct radeon_cs_parser * parser,int error)415 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
416 {
417 unsigned i;
418
419 if (!error) {
420 struct radeon_bo_list *reloc;
421
422 /* Sort the buffer list from the smallest to largest buffer,
423 * which affects the order of buffers in the LRU list.
424 * This assures that the smallest buffers are added first
425 * to the LRU list, so they are likely to be later evicted
426 * first, instead of large buffers whose eviction is more
427 * expensive.
428 *
429 * This slightly lowers the number of bytes moved by TTM
430 * per frame under memory pressure.
431 */
432 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
433 list_for_each_entry(reloc, &parser->validated, list) {
434 dma_resv_add_fence(reloc->robj->tbo.base.resv,
435 &parser->ib.fence->base,
436 reloc->shared ?
437 DMA_RESV_USAGE_READ :
438 DMA_RESV_USAGE_WRITE);
439 }
440 }
441
442 drm_exec_fini(&parser->exec);
443
444 if (parser->relocs != NULL) {
445 for (i = 0; i < parser->nrelocs; i++) {
446 struct radeon_bo *bo = parser->relocs[i].robj;
447 if (bo == NULL)
448 continue;
449
450 drm_gem_object_put(&bo->tbo.base);
451 }
452 }
453 kfree(parser->track);
454 kvfree(parser->relocs);
455 kvfree(parser->vm_bos);
456 for (i = 0; i < parser->nchunks; i++)
457 kvfree(parser->chunks[i].kdata);
458 kvfree(parser->chunks);
459 kvfree(parser->chunks_array);
460 radeon_ib_free(parser->rdev, &parser->ib);
461 radeon_ib_free(parser->rdev, &parser->const_ib);
462 }
463
radeon_cs_ib_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)464 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
465 struct radeon_cs_parser *parser)
466 {
467 int r;
468
469 if (parser->chunk_ib == NULL)
470 return 0;
471
472 if (parser->cs_flags & RADEON_CS_USE_VM)
473 return 0;
474
475 r = radeon_cs_parse(rdev, parser->ring, parser);
476 if (r || parser->parser_error) {
477 DRM_ERROR("Invalid command stream !\n");
478 return r;
479 }
480
481 r = radeon_cs_sync_rings(parser);
482 if (r) {
483 if (r != -ERESTARTSYS)
484 DRM_ERROR("Failed to sync rings: %i\n", r);
485 return r;
486 }
487
488 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
489 radeon_uvd_note_usage(rdev);
490 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
491 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
492 radeon_vce_note_usage(rdev);
493
494 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
495 if (r) {
496 DRM_ERROR("Failed to schedule IB !\n");
497 }
498 return r;
499 }
500
radeon_bo_vm_update_pte(struct radeon_cs_parser * p,struct radeon_vm * vm)501 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
502 struct radeon_vm *vm)
503 {
504 struct radeon_device *rdev = p->rdev;
505 struct radeon_bo_va *bo_va;
506 int i, r;
507
508 r = radeon_vm_update_page_directory(rdev, vm);
509 if (r)
510 return r;
511
512 r = radeon_vm_clear_freed(rdev, vm);
513 if (r)
514 return r;
515
516 if (vm->ib_bo_va == NULL) {
517 DRM_ERROR("Tmp BO not in VM!\n");
518 return -EINVAL;
519 }
520
521 r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
522 rdev->ring_tmp_bo.bo->tbo.resource);
523 if (r)
524 return r;
525
526 for (i = 0; i < p->nrelocs; i++) {
527 struct radeon_bo *bo;
528
529 bo = p->relocs[i].robj;
530 bo_va = radeon_vm_bo_find(vm, bo);
531 if (bo_va == NULL) {
532 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
533 return -EINVAL;
534 }
535
536 r = radeon_vm_bo_update(rdev, bo_va, bo->tbo.resource);
537 if (r)
538 return r;
539
540 radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
541
542 r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
543 if (r)
544 return r;
545 }
546
547 return radeon_vm_clear_invalids(rdev, vm);
548 }
549
radeon_cs_ib_vm_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)550 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
551 struct radeon_cs_parser *parser)
552 {
553 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
554 struct radeon_vm *vm = &fpriv->vm;
555 int r;
556
557 if (parser->chunk_ib == NULL)
558 return 0;
559 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
560 return 0;
561
562 if (parser->const_ib.length_dw) {
563 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
564 if (r) {
565 return r;
566 }
567 }
568
569 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
570 if (r) {
571 return r;
572 }
573
574 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
575 radeon_uvd_note_usage(rdev);
576
577 mutex_lock(&vm->mutex);
578 r = radeon_bo_vm_update_pte(parser, vm);
579 if (r) {
580 goto out;
581 }
582
583 r = radeon_cs_sync_rings(parser);
584 if (r) {
585 if (r != -ERESTARTSYS)
586 DRM_ERROR("Failed to sync rings: %i\n", r);
587 goto out;
588 }
589
590 if ((rdev->family >= CHIP_TAHITI) &&
591 (parser->chunk_const_ib != NULL)) {
592 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
593 } else {
594 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
595 }
596
597 out:
598 mutex_unlock(&vm->mutex);
599 return r;
600 }
601
radeon_cs_handle_lockup(struct radeon_device * rdev,int r)602 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
603 {
604 if (r == -EDEADLK) {
605 r = radeon_gpu_reset(rdev);
606 if (!r)
607 r = -EAGAIN;
608 }
609 return r;
610 }
611
radeon_cs_ib_fill(struct radeon_device * rdev,struct radeon_cs_parser * parser)612 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
613 {
614 struct radeon_cs_chunk *ib_chunk;
615 struct radeon_vm *vm = NULL;
616 int r;
617
618 if (parser->chunk_ib == NULL)
619 return 0;
620
621 if (parser->cs_flags & RADEON_CS_USE_VM) {
622 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
623 vm = &fpriv->vm;
624
625 if ((rdev->family >= CHIP_TAHITI) &&
626 (parser->chunk_const_ib != NULL)) {
627 ib_chunk = parser->chunk_const_ib;
628 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
629 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
630 return -EINVAL;
631 }
632 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
633 vm, ib_chunk->length_dw * 4);
634 if (r) {
635 DRM_ERROR("Failed to get const ib !\n");
636 return r;
637 }
638 parser->const_ib.is_const_ib = true;
639 parser->const_ib.length_dw = ib_chunk->length_dw;
640 if (copy_from_user(parser->const_ib.ptr,
641 ib_chunk->user_ptr,
642 ib_chunk->length_dw * 4))
643 return -EFAULT;
644 }
645
646 ib_chunk = parser->chunk_ib;
647 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
648 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
649 return -EINVAL;
650 }
651 }
652 ib_chunk = parser->chunk_ib;
653
654 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
655 vm, ib_chunk->length_dw * 4);
656 if (r) {
657 DRM_ERROR("Failed to get ib !\n");
658 return r;
659 }
660 parser->ib.length_dw = ib_chunk->length_dw;
661 if (ib_chunk->kdata)
662 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
663 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
664 return -EFAULT;
665 return 0;
666 }
667
radeon_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)668 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
669 {
670 struct radeon_device *rdev = dev->dev_private;
671 struct radeon_cs_parser parser;
672 int r;
673
674 down_read(&rdev->exclusive_lock);
675 if (!rdev->accel_working) {
676 up_read(&rdev->exclusive_lock);
677 return -EBUSY;
678 }
679 if (rdev->in_reset) {
680 up_read(&rdev->exclusive_lock);
681 r = radeon_gpu_reset(rdev);
682 if (!r)
683 r = -EAGAIN;
684 return r;
685 }
686 /* initialize parser */
687 memset(&parser, 0, sizeof(struct radeon_cs_parser));
688 parser.filp = filp;
689 parser.rdev = rdev;
690 parser.dev = rdev->dev;
691 parser.family = rdev->family;
692 r = radeon_cs_parser_init(&parser, data);
693 if (r) {
694 DRM_ERROR("Failed to initialize parser !\n");
695 radeon_cs_parser_fini(&parser, r);
696 up_read(&rdev->exclusive_lock);
697 r = radeon_cs_handle_lockup(rdev, r);
698 return r;
699 }
700
701 r = radeon_cs_ib_fill(rdev, &parser);
702 if (!r) {
703 r = radeon_cs_parser_relocs(&parser);
704 if (r && r != -ERESTARTSYS)
705 DRM_ERROR("Failed to parse relocation %d!\n", r);
706 }
707
708 if (r) {
709 radeon_cs_parser_fini(&parser, r);
710 up_read(&rdev->exclusive_lock);
711 r = radeon_cs_handle_lockup(rdev, r);
712 return r;
713 }
714
715 trace_radeon_cs(&parser);
716
717 r = radeon_cs_ib_chunk(rdev, &parser);
718 if (r) {
719 goto out;
720 }
721 r = radeon_cs_ib_vm_chunk(rdev, &parser);
722 if (r) {
723 goto out;
724 }
725 out:
726 radeon_cs_parser_fini(&parser, r);
727 up_read(&rdev->exclusive_lock);
728 r = radeon_cs_handle_lockup(rdev, r);
729 return r;
730 }
731
732 /**
733 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
734 * @p: parser structure holding parsing context.
735 * @pkt: where to store packet information
736 * @idx: packet index
737 *
738 * Assume that chunk_ib_index is properly set. Will return -EINVAL
739 * if packet is bigger than remaining ib size. or if packets is unknown.
740 **/
radeon_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)741 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
742 struct radeon_cs_packet *pkt,
743 unsigned idx)
744 {
745 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
746 struct radeon_device *rdev = p->rdev;
747 uint32_t header;
748 int ret = 0, i;
749
750 if (idx >= ib_chunk->length_dw) {
751 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
752 idx, ib_chunk->length_dw);
753 return -EINVAL;
754 }
755 header = radeon_get_ib_value(p, idx);
756 pkt->idx = idx;
757 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
758 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
759 pkt->one_reg_wr = 0;
760 switch (pkt->type) {
761 case RADEON_PACKET_TYPE0:
762 if (rdev->family < CHIP_R600) {
763 pkt->reg = R100_CP_PACKET0_GET_REG(header);
764 pkt->one_reg_wr =
765 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
766 } else
767 pkt->reg = R600_CP_PACKET0_GET_REG(header);
768 break;
769 case RADEON_PACKET_TYPE3:
770 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
771 break;
772 case RADEON_PACKET_TYPE2:
773 pkt->count = -1;
774 break;
775 default:
776 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
777 ret = -EINVAL;
778 goto dump_ib;
779 }
780 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
781 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
782 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
783 ret = -EINVAL;
784 goto dump_ib;
785 }
786 return 0;
787
788 dump_ib:
789 for (i = 0; i < ib_chunk->length_dw; i++) {
790 if (i == idx)
791 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
792 else
793 printk("\t0x%08x\n", radeon_get_ib_value(p, i));
794 }
795 return ret;
796 }
797
798 /**
799 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
800 * @p: structure holding the parser context.
801 *
802 * Check if the next packet is NOP relocation packet3.
803 **/
radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser * p)804 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
805 {
806 struct radeon_cs_packet p3reloc;
807 int r;
808
809 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
810 if (r)
811 return false;
812 if (p3reloc.type != RADEON_PACKET_TYPE3)
813 return false;
814 if (p3reloc.opcode != RADEON_PACKET3_NOP)
815 return false;
816 return true;
817 }
818
819 /**
820 * radeon_cs_dump_packet() - dump raw packet context
821 * @p: structure holding the parser context.
822 * @pkt: structure holding the packet.
823 *
824 * Used mostly for debugging and error reporting.
825 **/
radeon_cs_dump_packet(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)826 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
827 struct radeon_cs_packet *pkt)
828 {
829 volatile uint32_t *ib;
830 unsigned i;
831 unsigned idx;
832
833 ib = p->ib.ptr;
834 idx = pkt->idx;
835 for (i = 0; i <= (pkt->count + 1); i++, idx++)
836 dev_dbg(p->dev, "ib[%d]=0x%08X\n", idx, ib[idx]);
837 }
838
839 /**
840 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
841 * @p: parser structure holding parsing context.
842 * @cs_reloc: reloc informations
843 * @nomm: no memory management for debugging
844 *
845 * Check if next packet is relocation packet3, do bo validation and compute
846 * GPU offset using the provided start.
847 **/
radeon_cs_packet_next_reloc(struct radeon_cs_parser * p,struct radeon_bo_list ** cs_reloc,int nomm)848 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
849 struct radeon_bo_list **cs_reloc,
850 int nomm)
851 {
852 struct radeon_cs_chunk *relocs_chunk;
853 struct radeon_cs_packet p3reloc;
854 unsigned idx;
855 int r;
856
857 if (p->chunk_relocs == NULL) {
858 DRM_ERROR("No relocation chunk !\n");
859 return -EINVAL;
860 }
861 *cs_reloc = NULL;
862 relocs_chunk = p->chunk_relocs;
863 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
864 if (r)
865 return r;
866 p->idx += p3reloc.count + 2;
867 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
868 p3reloc.opcode != RADEON_PACKET3_NOP) {
869 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
870 p3reloc.idx);
871 radeon_cs_dump_packet(p, &p3reloc);
872 return -EINVAL;
873 }
874 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
875 if (idx >= relocs_chunk->length_dw) {
876 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
877 idx, relocs_chunk->length_dw);
878 radeon_cs_dump_packet(p, &p3reloc);
879 return -EINVAL;
880 }
881 /* FIXME: we assume reloc size is 4 dwords */
882 if (nomm) {
883 *cs_reloc = p->relocs;
884 (*cs_reloc)->gpu_offset =
885 (u64)relocs_chunk->kdata[idx + 3] << 32;
886 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
887 } else
888 *cs_reloc = &p->relocs[(idx / 4)];
889 return 0;
890 }
891