1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Author: Conor Dooley <conor.dooley@microchip.com>
4 *
5 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
6 */
7 #include <linux/clk-provider.h>
8 #include <linux/errno.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
13
14 /* address offset of control registers */
15 #define MPFS_CCC_PLL_CR 0x04u
16 #define MPFS_CCC_REF_CR 0x08u
17 #define MPFS_CCC_SSCG_2_CR 0x2Cu
18 #define MPFS_CCC_POSTDIV01_CR 0x10u
19 #define MPFS_CCC_POSTDIV23_CR 0x14u
20
21 #define MPFS_CCC_FBDIV_SHIFT 0x00u
22 #define MPFS_CCC_FBDIV_WIDTH 0x0Cu
23 #define MPFS_CCC_POSTDIV0_SHIFT 0x08u
24 #define MPFS_CCC_POSTDIV1_SHIFT 0x18u
25 #define MPFS_CCC_POSTDIV2_SHIFT MPFS_CCC_POSTDIV0_SHIFT
26 #define MPFS_CCC_POSTDIV3_SHIFT MPFS_CCC_POSTDIV1_SHIFT
27 #define MPFS_CCC_POSTDIV_WIDTH 0x06u
28 #define MPFS_CCC_REFCLK_SEL BIT(6)
29 #define MPFS_CCC_REFDIV_SHIFT 0x08u
30 #define MPFS_CCC_REFDIV_WIDTH 0x06u
31
32 #define MPFS_CCC_FIXED_DIV 4
33 #define MPFS_CCC_OUTPUTS_PER_PLL 4
34 #define MPFS_CCC_REFS_PER_PLL 2
35 #define MPFS_CCC_NUM_CLKS 16
36
37 struct mpfs_ccc_data {
38 void __iomem **pll_base;
39 struct device *dev;
40 struct clk_hw_onecell_data hw_data;
41 };
42
43 struct mpfs_ccc_pll_hw_clock {
44 void __iomem *base;
45 const char *name;
46 const struct clk_parent_data *parents;
47 unsigned int id;
48 u32 reg_offset;
49 u32 shift;
50 u32 width;
51 u32 flags;
52 struct clk_hw hw;
53 struct clk_init_data init;
54 };
55
56 #define to_mpfs_ccc_clk(_hw) container_of(_hw, struct mpfs_ccc_pll_hw_clock, hw)
57
58 /*
59 * mpfs_ccc_lock prevents anything else from writing to a fabric ccc
60 * while a software locked register is being written.
61 */
62 static DEFINE_SPINLOCK(mpfs_ccc_lock);
63
64 static const struct clk_parent_data mpfs_ccc_pll0_refs[] = {
65 { .fw_name = "pll0_ref0" },
66 { .fw_name = "pll0_ref1" },
67 };
68
69 static const struct clk_parent_data mpfs_ccc_pll1_refs[] = {
70 { .fw_name = "pll1_ref0" },
71 { .fw_name = "pll1_ref1" },
72 };
73
mpfs_ccc_pll_recalc_rate(struct clk_hw * hw,unsigned long prate)74 static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
75 {
76 struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
77 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset;
78 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR;
79 u32 mult, ref_div;
80
81 mult = readl_relaxed(mult_addr) >> MPFS_CCC_FBDIV_SHIFT;
82 mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH);
83 ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT;
84 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH);
85
86 return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV);
87 }
88
mpfs_ccc_pll_get_parent(struct clk_hw * hw)89 static u8 mpfs_ccc_pll_get_parent(struct clk_hw *hw)
90 {
91 struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
92 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR;
93
94 return !!(readl_relaxed(pll_cr_addr) & MPFS_CCC_REFCLK_SEL);
95 }
96
97 static const struct clk_ops mpfs_ccc_pll_ops = {
98 .recalc_rate = mpfs_ccc_pll_recalc_rate,
99 .get_parent = mpfs_ccc_pll_get_parent,
100 };
101
102 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \
103 .id = _id, \
104 .shift = _shift, \
105 .width = _width, \
106 .reg_offset = _offset, \
107 .flags = _flags, \
108 .parents = _parents, \
109 }
110
111 static struct mpfs_ccc_pll_hw_clock mpfs_ccc_pll_clks[] = {
112 CLK_CCC_PLL(CLK_CCC_PLL0, mpfs_ccc_pll0_refs, MPFS_CCC_FBDIV_SHIFT,
113 MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
114 CLK_CCC_PLL(CLK_CCC_PLL1, mpfs_ccc_pll1_refs, MPFS_CCC_FBDIV_SHIFT,
115 MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
116 };
117
118 struct mpfs_ccc_out_hw_clock {
119 struct clk_divider divider;
120 struct clk_init_data init;
121 unsigned int id;
122 u32 reg_offset;
123 };
124
125 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \
126 .id = _id, \
127 .divider.shift = _shift, \
128 .divider.width = _width, \
129 .reg_offset = _offset, \
130 .divider.flags = _flags, \
131 .divider.lock = &mpfs_ccc_lock, \
132 }
133
134 static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll0out_clks[] = {
135 CLK_CCC_OUT(CLK_CCC_PLL0_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
136 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
137 CLK_CCC_OUT(CLK_CCC_PLL0_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
138 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
139 CLK_CCC_OUT(CLK_CCC_PLL0_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
140 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
141 CLK_CCC_OUT(CLK_CCC_PLL0_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
142 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
143 };
144
145 static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll1out_clks[] = {
146 CLK_CCC_OUT(CLK_CCC_PLL1_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
148 CLK_CCC_OUT(CLK_CCC_PLL1_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
149 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
150 CLK_CCC_OUT(CLK_CCC_PLL1_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
151 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
152 CLK_CCC_OUT(CLK_CCC_PLL1_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
154 };
155
156 static struct mpfs_ccc_out_hw_clock *mpfs_ccc_pllout_clks[] = {
157 mpfs_ccc_pll0out_clks, mpfs_ccc_pll1out_clks
158 };
159
mpfs_ccc_register_outputs(struct device * dev,struct mpfs_ccc_out_hw_clock * out_hws,unsigned int num_clks,struct mpfs_ccc_data * data,struct mpfs_ccc_pll_hw_clock * parent)160 static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_clock *out_hws,
161 unsigned int num_clks, struct mpfs_ccc_data *data,
162 struct mpfs_ccc_pll_hw_clock *parent)
163 {
164 int ret;
165
166 for (unsigned int i = 0; i < num_clks; i++) {
167 struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
168 char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i);
169
170 if (!name)
171 return -ENOMEM;
172
173 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
174 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
175 out_hw->reg_offset;
176
177 ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
178 if (ret)
179 return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
180 out_hw->id);
181
182 data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
183 }
184
185 return 0;
186 }
187
188 #define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \
189 (&(struct clk_init_data) { \
190 .flags = _flags, \
191 .name = _name, \
192 .parent_data = _parents, \
193 .num_parents = MPFS_CCC_REFS_PER_PLL, \
194 .ops = _ops, \
195 })
196
mpfs_ccc_register_plls(struct device * dev,struct mpfs_ccc_pll_hw_clock * pll_hws,unsigned int num_clks,struct mpfs_ccc_data * data)197 static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clock *pll_hws,
198 unsigned int num_clks, struct mpfs_ccc_data *data)
199 {
200 int ret;
201
202 for (unsigned int i = 0; i < num_clks; i++) {
203 struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
204
205 pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
206 strchrnul(dev->of_node->full_name, '@'), i);
207 if (!pll_hw->name)
208 return -ENOMEM;
209
210 pll_hw->base = data->pll_base[i];
211 pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
212 pll_hw->parents,
213 &mpfs_ccc_pll_ops, 0);
214
215 ret = devm_clk_hw_register(dev, &pll_hw->hw);
216 if (ret)
217 return dev_err_probe(dev, ret, "failed to register ccc id: %d\n",
218 pll_hw->id);
219
220 data->hw_data.hws[pll_hw->id] = &pll_hw->hw;
221
222 ret = mpfs_ccc_register_outputs(dev, mpfs_ccc_pllout_clks[i],
223 MPFS_CCC_OUTPUTS_PER_PLL, data, pll_hw);
224 if (ret)
225 return ret;
226 }
227
228 return 0;
229 }
230
mpfs_ccc_probe(struct platform_device * pdev)231 static int mpfs_ccc_probe(struct platform_device *pdev)
232 {
233 struct mpfs_ccc_data *clk_data;
234 void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)];
235 int ret;
236
237 clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, MPFS_CCC_NUM_CLKS),
238 GFP_KERNEL);
239 if (!clk_data)
240 return -ENOMEM;
241
242 pll_base[0] = devm_platform_ioremap_resource(pdev, 0);
243 if (IS_ERR(pll_base[0]))
244 return PTR_ERR(pll_base[0]);
245
246 pll_base[1] = devm_platform_ioremap_resource(pdev, 1);
247 if (IS_ERR(pll_base[1]))
248 return PTR_ERR(pll_base[1]);
249
250 clk_data->pll_base = pll_base;
251 clk_data->hw_data.num = MPFS_CCC_NUM_CLKS;
252 clk_data->dev = &pdev->dev;
253
254 ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,
255 ARRAY_SIZE(mpfs_ccc_pll_clks), clk_data);
256 if (ret)
257 return ret;
258
259 return devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get,
260 &clk_data->hw_data);
261 }
262
263 static const struct of_device_id mpfs_ccc_of_match_table[] = {
264 { .compatible = "microchip,mpfs-ccc", },
265 {}
266 };
267 MODULE_DEVICE_TABLE(of, mpfs_ccc_of_match_table);
268
269 static struct platform_driver mpfs_ccc_driver = {
270 .probe = mpfs_ccc_probe,
271 .driver = {
272 .name = "microchip-mpfs-ccc",
273 .of_match_table = mpfs_ccc_of_match_table,
274 },
275 };
276
clk_ccc_init(void)277 static int __init clk_ccc_init(void)
278 {
279 return platform_driver_register(&mpfs_ccc_driver);
280 }
281 core_initcall(clk_ccc_init);
282
clk_ccc_exit(void)283 static void __exit clk_ccc_exit(void)
284 {
285 platform_driver_unregister(&mpfs_ccc_driver);
286 }
287 module_exit(clk_ccc_exit);
288
289 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Conditioning Circuitry Driver");
290 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
291