1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Gen3 HDMI PHY
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12
13 #include <drm/bridge/dw_hdmi.h>
14 #include <drm/drm_modes.h>
15
16 #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
17 #define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
18 #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
19
20 struct rcar_hdmi_phy_params {
21 unsigned long mpixelclock;
22 u16 opmode_div; /* Mode of operation and PLL dividers */
23 u16 curr_gmp; /* PLL current and Gmp (conductance) */
24 u16 div; /* PLL dividers */
25 };
26
27 static const struct rcar_hdmi_phy_params rcar_hdmi_phy_params[] = {
28 { 35500000, 0x0003, 0x0344, 0x0328 },
29 { 44900000, 0x0003, 0x0285, 0x0128 },
30 { 71000000, 0x0002, 0x1184, 0x0314 },
31 { 90000000, 0x0002, 0x1144, 0x0114 },
32 { 140250000, 0x0001, 0x20c4, 0x030a },
33 { 182750000, 0x0001, 0x2084, 0x010a },
34 { 281250000, 0x0000, 0x0084, 0x0305 },
35 { 297000000, 0x0000, 0x0084, 0x0105 },
36 { ~0UL, 0x0000, 0x0000, 0x0000 },
37 };
38
39 static enum drm_mode_status
rcar_hdmi_mode_valid(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * info,const struct drm_display_mode * mode)40 rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
41 const struct drm_display_info *info,
42 const struct drm_display_mode *mode)
43 {
44 /*
45 * The maximum supported clock frequency is 297 MHz, as shown in the PHY
46 * parameters table.
47 */
48 if (mode->clock > 297000)
49 return MODE_CLOCK_HIGH;
50
51 return MODE_OK;
52 }
53
rcar_hdmi_phy_configure(struct dw_hdmi * hdmi,void * data,unsigned long mpixelclock)54 static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
55 unsigned long mpixelclock)
56 {
57 const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
58
59 for (; params->mpixelclock != ~0UL; ++params) {
60 if (mpixelclock <= params->mpixelclock)
61 break;
62 }
63
64 if (params->mpixelclock == ~0UL)
65 return -EINVAL;
66
67 dw_hdmi_phy_i2c_write(hdmi, params->opmode_div,
68 RCAR_HDMI_PHY_OPMODE_PLLCFG);
69 dw_hdmi_phy_i2c_write(hdmi, params->curr_gmp,
70 RCAR_HDMI_PHY_PLLCURRGMPCTRL);
71 dw_hdmi_phy_i2c_write(hdmi, params->div, RCAR_HDMI_PHY_PLLDIVCTRL);
72
73 return 0;
74 }
75
76 static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
77 .output_port = 1,
78 .mode_valid = rcar_hdmi_mode_valid,
79 .configure_phy = rcar_hdmi_phy_configure,
80 };
81
rcar_dw_hdmi_probe(struct platform_device * pdev)82 static int rcar_dw_hdmi_probe(struct platform_device *pdev)
83 {
84 struct dw_hdmi *hdmi;
85
86 hdmi = dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data);
87 if (IS_ERR(hdmi))
88 return PTR_ERR(hdmi);
89
90 platform_set_drvdata(pdev, hdmi);
91
92 return 0;
93 }
94
rcar_dw_hdmi_remove(struct platform_device * pdev)95 static void rcar_dw_hdmi_remove(struct platform_device *pdev)
96 {
97 struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
98
99 dw_hdmi_remove(hdmi);
100 }
101
102 static const struct of_device_id rcar_dw_hdmi_of_table[] = {
103 { .compatible = "renesas,rcar-gen3-hdmi" },
104 { /* Sentinel */ },
105 };
106 MODULE_DEVICE_TABLE(of, rcar_dw_hdmi_of_table);
107
108 static struct platform_driver rcar_dw_hdmi_platform_driver = {
109 .probe = rcar_dw_hdmi_probe,
110 .remove = rcar_dw_hdmi_remove,
111 .driver = {
112 .name = "rcar-dw-hdmi",
113 .of_match_table = rcar_dw_hdmi_of_table,
114 },
115 };
116
117 module_platform_driver(rcar_dw_hdmi_platform_driver);
118
119 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
120 MODULE_DESCRIPTION("Renesas R-Car Gen3 HDMI Encoder Driver");
121 MODULE_LICENSE("GPL");
122