1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2026 Analog Devices, Inc.
4 * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
5 */
6
7 #include <linux/array_size.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/crc8.h>
12 #include <linux/delay.h>
13 #include <linux/dev_printk.h>
14 #include <linux/err.h>
15 #include <linux/export.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/types.h>
19 #include <linux/module.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/reset.h>
23 #include <linux/spi/spi.h>
24 #include <linux/time.h>
25 #include <linux/types.h>
26 #include <linux/unaligned.h>
27 #include <linux/units.h>
28
29 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
30
31 #define AD4134_REG_READ_MASK BIT(7)
32 #define AD4134_SPI_MAX_XFER_LEN 3
33
34 #define AD4134_EXT_CLOCK_MHZ (48 * HZ_PER_MHZ)
35
36 #define AD4134_NUM_CHANNELS 4
37 #define AD4134_CHAN_PRECISION_BITS 24
38
39 #define AD4134_IFACE_CONFIG_A_REG 0x00
40 #define AD4134_IFACE_CONFIG_B_REG 0x01
41 #define AD4134_IFACE_CONFIG_B_SINGLE_INSTR BIT(7)
42
43 #define AD4134_DEVICE_CONFIG_REG 0x02
44 #define AD4134_DEVICE_CONFIG_POWER_MODE_MASK BIT(0)
45 #define AD4134_POWER_MODE_HIGH_PERF 0x1
46
47 #define AD4134_SILICON_REV_REG 0x07
48 #define AD4134_SCRATCH_PAD_REG 0x0A
49 #define AD4134_STREAM_MODE_REG 0x0E
50 #define AD4134_SDO_PIN_SRC_SEL_REG 0x10
51 #define AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK BIT(2)
52
53 #define AD4134_DATA_PACKET_CONFIG_REG 0x11
54 #define AD4134_DATA_PACKET_CONFIG_FRAME_MASK GENMASK(5, 4)
55 #define AD4134_DATA_PACKET_24BIT_FRAME 0x2
56
57 #define AD4134_DIG_IF_CFG_REG 0x12
58 #define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0)
59 #define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0
60
61 #define AD4134_PW_DOWN_CTRL_REG 0x13
62 #define AD4134_DEVICE_STATUS_REG 0x15
63 #define AD4134_ODR_VAL_INT_LSB_REG 0x16
64 #define AD4134_CH3_OFFSET_MSB_REG 0x3E
65 #define AD4134_AIN_OR_ERROR_REG 0x48
66
67 /*
68 * AD4134 register map ends at address 0x48 and there is no register for
69 * retrieving ADC sample data. Though, to make use of Linux regmap API both
70 * for register access and sample read, we define one virtual register for each
71 * ADC channel. AD4134_CH_VREG(x) maps a channel number to it's virtual register
72 * address while AD4134_VREG_CH(x) tells which channel given the address.
73 */
74 #define AD4134_CH_VREG(x) ((x) + 0x50)
75 #define AD4134_VREG_CH(x) ((x) - 0x50)
76
77 #define AD4134_SPI_CRC_POLYNOM 0x07
78 #define AD4134_SPI_CRC_INIT_VALUE 0xA5
79 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE];
80
81 #define AD4134_CHANNEL(_index) { \
82 .type = IIO_VOLTAGE, \
83 .indexed = 1, \
84 .channel = (_index), \
85 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
86 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
87 }
88
89 static const struct iio_chan_spec ad4134_chan_set[] = {
90 AD4134_CHANNEL(0),
91 AD4134_CHANNEL(1),
92 AD4134_CHANNEL(2),
93 AD4134_CHANNEL(3),
94 };
95
96 struct ad4134_state {
97 struct spi_device *spi;
98 struct regmap *regmap;
99 unsigned long sys_clk_hz;
100 struct gpio_desc *odr_gpio;
101 int refin_mv;
102 /*
103 * DMA (thus cache coherency maintenance) requires the transfer buffers
104 * to live in their own cache lines.
105 */
106 u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
107 u8 tx_buf[AD4134_SPI_MAX_XFER_LEN];
108 };
109
110 static const struct regmap_range ad4134_regmap_rd_range[] = {
111 regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_SILICON_REV_REG),
112 regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_PW_DOWN_CTRL_REG),
113 regmap_reg_range(AD4134_DEVICE_STATUS_REG, AD4134_AIN_OR_ERROR_REG),
114 regmap_reg_range(AD4134_CH_VREG(0), AD4134_CH_VREG(AD4134_NUM_CHANNELS)),
115 };
116
117 static const struct regmap_range ad4134_regmap_wr_range[] = {
118 regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_DEVICE_CONFIG_REG),
119 regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_SCRATCH_PAD_REG),
120 regmap_reg_range(AD4134_STREAM_MODE_REG, AD4134_PW_DOWN_CTRL_REG),
121 regmap_reg_range(AD4134_ODR_VAL_INT_LSB_REG, AD4134_CH3_OFFSET_MSB_REG),
122 };
123
124 static const struct regmap_access_table ad4134_regmap_rd_table = {
125 .yes_ranges = ad4134_regmap_rd_range,
126 .n_yes_ranges = ARRAY_SIZE(ad4134_regmap_rd_range),
127 };
128
129 static const struct regmap_access_table ad4134_regmap_wr_table = {
130 .yes_ranges = ad4134_regmap_wr_range,
131 .n_yes_ranges = ARRAY_SIZE(ad4134_regmap_wr_range),
132 };
133
ad4134_calc_spi_crc(u8 inst,u8 data)134 static int ad4134_calc_spi_crc(u8 inst, u8 data)
135 {
136 u8 buf[] = { inst, data };
137
138 return crc8(ad4134_spi_crc_table, buf, ARRAY_SIZE(buf),
139 AD4134_SPI_CRC_INIT_VALUE);
140 }
141
ad4134_prepare_spi_tx_buf(u8 inst,u8 data,u8 * buf)142 static void ad4134_prepare_spi_tx_buf(u8 inst, u8 data, u8 *buf)
143 {
144 buf[0] = inst;
145 buf[1] = data;
146 buf[2] = ad4134_calc_spi_crc(inst, data);
147 }
148
ad4134_reg_write(void * context,unsigned int reg,unsigned int val)149 static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
150 {
151 struct ad4134_state *st = context;
152 struct spi_transfer xfer = {
153 .tx_buf = st->tx_buf,
154 .rx_buf = st->rx_buf,
155 .len = AD4134_SPI_MAX_XFER_LEN,
156 };
157 int ret;
158
159 ad4134_prepare_spi_tx_buf(reg, val, st->tx_buf);
160
161 ret = spi_sync_transfer(st->spi, &xfer, 1);
162 if (ret)
163 return ret;
164
165 if (st->rx_buf[2] != st->tx_buf[2])
166 dev_dbg(&st->spi->dev, "reg write CRC check failed\n");
167
168 return 0;
169 }
170
ad4134_data_read(struct ad4134_state * st,unsigned int reg,unsigned int * val)171 static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
172 unsigned int *val)
173 {
174 unsigned int i;
175 int ret;
176
177 /*
178 * To be able to read data from all 4 channels through a single line, we
179 * set DOUTx output format to 0 in the digital interface config register
180 * (0x12). With that, data from all four channels is serialized and
181 * output on DOUT0. During the probe, we also set SDO_PIN_SRC_SEL in
182 * DEVICE_CONFIG_1 register to duplicate DOUT0 on the SDO pin. Combined,
183 * those configurations enable ADC data read through a conventional SPI
184 * interface. Now we read data from all channels but keep only the bits
185 * from the requested one.
186 */
187 for (i = 0; i < ARRAY_SIZE(ad4134_chan_set); i++) {
188 ret = spi_write_then_read(st->spi, NULL, 0, st->rx_buf,
189 BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS));
190 if (ret)
191 return ret;
192
193 /*
194 * AD4134 has a built-in feature that flags when data transfers
195 * don't run enough clock cycles to read the entire data frame.
196 * Clock out data from all channels to avoid that.
197 */
198 if (i == AD4134_VREG_CH(reg))
199 *val = get_unaligned_be24(st->rx_buf);
200 }
201
202 return 0;
203 }
204
ad4134_register_read(struct ad4134_state * st,unsigned int reg,unsigned int * val)205 static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
206 unsigned int *val)
207 {
208 struct spi_transfer xfer = {
209 .tx_buf = st->tx_buf,
210 .rx_buf = st->rx_buf,
211 .len = AD4134_SPI_MAX_XFER_LEN,
212 };
213 unsigned int inst;
214 int ret;
215
216 inst = AD4134_REG_READ_MASK | reg;
217 ad4134_prepare_spi_tx_buf(inst, 0, st->tx_buf);
218
219 ret = spi_sync_transfer(st->spi, &xfer, 1);
220 if (ret)
221 return ret;
222
223 *val = st->rx_buf[1];
224
225 /* Check CRC */
226 if (st->rx_buf[2] != st->tx_buf[2])
227 dev_dbg(&st->spi->dev, "reg read CRC check failed\n");
228
229 return 0;
230 }
231
ad4134_reg_read(void * context,unsigned int reg,unsigned int * val)232 static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *val)
233 {
234 struct ad4134_state *st = context;
235
236 if (reg >= AD4134_CH_VREG(0))
237 return ad4134_data_read(st, reg, val);
238
239 return ad4134_register_read(st, reg, val);
240 }
241
242 static const struct regmap_config ad4134_regmap_config = {
243 .reg_read = ad4134_reg_read,
244 .reg_write = ad4134_reg_write,
245 .rd_table = &ad4134_regmap_rd_table,
246 .wr_table = &ad4134_regmap_wr_table,
247 .max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)),
248 };
249
ad4134_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)250 static int ad4134_read_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
252 int *val, int *val2, long info)
253 {
254 struct ad4134_state *st = iio_priv(indio_dev);
255 int ret;
256
257 switch (info) {
258 case IIO_CHAN_INFO_RAW:
259 gpiod_set_value_cansleep(st->odr_gpio, 1);
260 /*
261 * For slave mode gated DCLK (data sheet page 11), the minimum
262 * ODR high time is 3 * tDIGCLK. The internal digital clock
263 * period is tDIGCLK = 1/fDIGCLK = 2/fSYSCLK.
264 * The System clock frequency (fSYSCLK) is typically 48 MHz.
265 * Thus, ODR high time = 3 * (2 / (48 * HZ_PER_MHZ))
266 * ODR high time = 0.000000125 s = 125 ns
267 * 1 micro second should be more than enough. Not worth it
268 * tweaking for shorter dealy since this is not a fast data path.
269 */
270 fsleep(1);
271 gpiod_set_value_cansleep(st->odr_gpio, 0);
272 ret = regmap_read(st->regmap, AD4134_CH_VREG(chan->channel), val);
273 if (ret)
274 return ret;
275
276 return IIO_VAL_INT;
277 case IIO_CHAN_INFO_SCALE:
278 *val = st->refin_mv;
279 *val2 = AD4134_CHAN_PRECISION_BITS - 1;
280
281 return IIO_VAL_FRACTIONAL_LOG2;
282 default:
283 return -EINVAL;
284 }
285 }
286
ad4134_debugfs_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)287 static int ad4134_debugfs_reg_access(struct iio_dev *indio_dev,
288 unsigned int reg, unsigned int writeval,
289 unsigned int *readval)
290 {
291 struct ad4134_state *st = iio_priv(indio_dev);
292
293 if (readval)
294 return regmap_read(st->regmap, reg, readval);
295
296 return regmap_write(st->regmap, reg, writeval);
297 }
298
ad4134_min_io_mode_setup(struct ad4134_state * st)299 static int ad4134_min_io_mode_setup(struct ad4134_state *st)
300 {
301 struct device *dev = &st->spi->dev;
302 int ret;
303
304 st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
305 if (IS_ERR(st->odr_gpio))
306 return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
307 "failed to get ODR GPIO\n");
308
309 ret = regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
310 AD4134_DIF_IF_CFG_FORMAT_MASK,
311 FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
312 AD4134_DATA_FORMAT_SINGLE_CH_MODE));
313 if (ret)
314 return dev_err_probe(dev, ret,
315 "failed to set single channel mode\n");
316
317 ret = regmap_set_bits(st->regmap, AD4134_SDO_PIN_SRC_SEL_REG,
318 AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK);
319 if (ret)
320 return dev_err_probe(dev, ret,
321 "failed to set SDO source selection\n");
322
323 return regmap_set_bits(st->regmap, AD4134_IFACE_CONFIG_B_REG,
324 AD4134_IFACE_CONFIG_B_SINGLE_INSTR);
325 }
326
327 static const struct iio_info ad4134_info = {
328 .read_raw = ad4134_read_raw,
329 .debugfs_reg_access = ad4134_debugfs_reg_access,
330 };
331
332 static const char * const ad4143_required_regulators[] = {
333 "avdd5", "dvdd5", "iovdd",
334 };
335
336 static const char * const ad4143_optional_regulators[] = {
337 "avdd1v8", "dvdd1v8", "clkvdd",
338 };
339
ad4134_regulator_setup(struct ad4134_state * st)340 static int ad4134_regulator_setup(struct ad4134_state *st)
341 {
342 struct device *dev = &st->spi->dev;
343 int ret;
344
345 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_required_regulators),
346 ad4143_required_regulators);
347 if (ret)
348 return dev_err_probe(dev, ret, "failed to enable power supplies\n");
349
350 /* Required regulator that we need to read the voltage */
351 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
352 if (ret < 0)
353 return dev_err_probe(dev, ret, "failed to get REFIN voltage.\n");
354
355 st->refin_mv = ret / (MICRO / MILLI);
356
357 ret = devm_regulator_get_enable_optional(dev, "ldoin");
358 if (ret < 0 && ret != -ENODEV)
359 return dev_err_probe(dev, ret, "failed to enable ldoin supply\n");
360
361 /* If ldoin was provided, then use the use the internal LDO regulators */
362 if (ret == 0)
363 return 0;
364
365 /*
366 * If ldoin is not provided, then avdd1v8, dvdd1v8, and clkvdd are
367 * required.
368 */
369 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_optional_regulators),
370 ad4143_optional_regulators);
371 if (ret)
372 return dev_err_probe(dev, ret, "failed to enable 1V8 power supplies\n");
373
374 return 0;
375 }
376
ad4134_clock_select(struct ad4134_state * st)377 static int ad4134_clock_select(struct ad4134_state *st)
378 {
379 struct device *dev = &st->spi->dev;
380 struct clk *xtal_clk, *clkin_clk;
381
382 /*
383 * AD4134 requires one external clock source and only one external clock
384 * source can be provided at a time. Try to get a crystal provided clock.
385 * If that fails, try to get a CMOS clock.
386 */
387 xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
388 if (!xtal_clk)
389 xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
390 if (IS_ERR(xtal_clk))
391 return dev_err_probe(dev, PTR_ERR(xtal_clk),
392 "failed to get xtal\n");
393
394 clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
395 if (!clkin_clk)
396 clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
397 if (IS_ERR(clkin_clk))
398 return dev_err_probe(dev, PTR_ERR(clkin_clk),
399 "failed to get clkin\n");
400
401 st->sys_clk_hz = clk_get_rate(xtal_clk) | clk_get_rate(clkin_clk);
402 if (st->sys_clk_hz != AD4134_EXT_CLOCK_MHZ)
403 dev_warn(dev, "invalid external clock frequency %lu\n",
404 st->sys_clk_hz);
405
406 return 0;
407 }
408
ad4134_probe(struct spi_device * spi)409 static int ad4134_probe(struct spi_device *spi)
410 {
411 struct device *dev = &spi->dev;
412 struct reset_control *rst;
413 struct iio_dev *indio_dev;
414 struct ad4134_state *st;
415 int ret;
416
417 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
418 if (!indio_dev)
419 return -ENOMEM;
420
421 st = iio_priv(indio_dev);
422 st->spi = spi;
423
424 indio_dev->name = "ad4134";
425 indio_dev->channels = ad4134_chan_set;
426 indio_dev->num_channels = ARRAY_SIZE(ad4134_chan_set);
427 indio_dev->modes = INDIO_DIRECT_MODE;
428 indio_dev->info = &ad4134_info;
429
430 ret = ad4134_regulator_setup(st);
431 if (ret)
432 return ret;
433
434 ret = ad4134_clock_select(st);
435 if (ret)
436 return ret;
437
438 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
439 if (IS_ERR(rst))
440 return dev_err_probe(dev, PTR_ERR(rst),
441 "failed to get and deassert reset\n");
442
443 crc8_populate_msb(ad4134_spi_crc_table, AD4134_SPI_CRC_POLYNOM);
444
445 st->regmap = devm_regmap_init(dev, NULL, st, &ad4134_regmap_config);
446 if (IS_ERR(st->regmap))
447 return dev_err_probe(dev, PTR_ERR(st->regmap),
448 "failed to initialize regmap");
449
450 ret = ad4134_min_io_mode_setup(st);
451 if (ret)
452 return dev_err_probe(dev, ret,
453 "failed to setup minimum I/O mode\n");
454
455 /* Bump precision to 24-bit */
456 ret = regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG,
457 AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
458 FIELD_PREP(AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
459 AD4134_DATA_PACKET_24BIT_FRAME));
460 if (ret)
461 return ret;
462
463 /* Set high performance power mode */
464 ret = regmap_update_bits(st->regmap, AD4134_DEVICE_CONFIG_REG,
465 AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
466 FIELD_PREP(AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
467 AD4134_POWER_MODE_HIGH_PERF));
468 if (ret)
469 return ret;
470
471 return devm_iio_device_register(dev, indio_dev);
472 }
473
474 static const struct spi_device_id ad4134_id[] = {
475 { .name = "ad4134" },
476 { }
477 };
478 MODULE_DEVICE_TABLE(spi, ad4134_id);
479
480 static const struct of_device_id ad4134_of_match[] = {
481 { .compatible = "adi,ad4134" },
482 { }
483 };
484 MODULE_DEVICE_TABLE(of, ad4134_of_match);
485
486 static struct spi_driver ad4134_driver = {
487 .driver = {
488 .name = "ad4134",
489 .of_match_table = ad4134_of_match,
490 },
491 .probe = ad4134_probe,
492 .id_table = ad4134_id,
493 };
494 module_spi_driver(ad4134_driver);
495
496 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
497 MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver");
498 MODULE_LICENSE("GPL");
499 MODULE_IMPORT_NS("IIO_AD4134");
500