1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_params.h" 23 #include "intel_display_power.h" 24 #include "intel_dmc_wl.h" 25 #include "intel_dpll_mgr.h" 26 #include "intel_fbc.h" 27 #include "intel_global_state.h" 28 #include "intel_gmbus.h" 29 #include "intel_opregion.h" 30 #include "intel_pch.h" 31 #include "intel_wm_types.h" 32 33 struct drm_property; 34 struct drm_property_blob; 35 struct i915_audio_component; 36 struct i915_hdcp_arbiter; 37 struct intel_atomic_state; 38 struct intel_audio_funcs; 39 struct intel_cdclk_funcs; 40 struct intel_cdclk_vals; 41 struct intel_color_funcs; 42 struct intel_crtc; 43 struct intel_crtc_state; 44 struct intel_display_parent_interface; 45 struct intel_dmc; 46 struct intel_dpll_global_funcs; 47 struct intel_dpll_mgr; 48 struct intel_fbdev; 49 struct intel_fdi_funcs; 50 struct intel_hotplug_irq_funcs; 51 struct intel_initial_plane_config; 52 struct intel_opregion; 53 struct intel_overlay; 54 struct task_struct; 55 56 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 57 #define I915_NUM_QGV_POINTS 8 58 59 /* Amount of PSF GV points, BSpec precisely defines this */ 60 #define I915_NUM_PSF_GV_POINTS 3 61 62 struct intel_modeset_funcs { 63 /* 64 * Returns the active state of the crtc, and if the crtc is active, 65 * fills out the pipe-config with the hw state. 66 */ 67 bool (*get_pipe_config)(struct intel_crtc *, 68 struct intel_crtc_state *); 69 void (*get_initial_plane_config)(struct intel_crtc *, 70 struct intel_initial_plane_config *); 71 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 72 const struct intel_initial_plane_config *plane_config); 73 void (*crtc_enable)(struct intel_atomic_state *state, 74 struct intel_crtc *crtc); 75 void (*crtc_disable)(struct intel_atomic_state *state, 76 struct intel_crtc *crtc); 77 void (*commit_modeset_enables)(struct intel_atomic_state *state); 78 }; 79 80 /* functions used for watermark calcs for display. */ 81 struct intel_wm_funcs { 82 /* update_wm is for legacy wm management */ 83 void (*update_wm)(struct intel_display *display); 84 int (*compute_watermarks)(struct intel_atomic_state *state, 85 struct intel_crtc *crtc); 86 void (*initial_watermarks)(struct intel_atomic_state *state, 87 struct intel_crtc *crtc); 88 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 89 struct intel_crtc *crtc); 90 void (*optimize_watermarks)(struct intel_atomic_state *state, 91 struct intel_crtc *crtc); 92 int (*compute_global_watermarks)(struct intel_atomic_state *state); 93 void (*get_hw_state)(struct intel_display *display); 94 void (*sanitize)(struct intel_display *display); 95 }; 96 97 struct intel_audio_state { 98 struct intel_encoder *encoder; 99 u8 eld[MAX_ELD_BYTES]; 100 }; 101 102 struct intel_audio { 103 /* internal display audio functions */ 104 const struct intel_audio_funcs *funcs; 105 106 /* hda/i915 audio component */ 107 struct i915_audio_component *component; 108 bool component_registered; 109 /* mutex for audio/video sync */ 110 struct mutex mutex; 111 int power_refcount; 112 u32 freq_cntrl; 113 114 /* current audio state for the audio component hooks */ 115 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 116 117 /* necessary resource sharing with HDMI LPE audio driver. */ 118 struct { 119 struct platform_device *platdev; 120 int irq; 121 } lpe; 122 }; 123 124 /* 125 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 126 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 127 * dpll, because on some platforms plls share registers. 128 */ 129 struct intel_dpll_global { 130 /* internal dpll functions */ 131 const struct intel_dpll_global_funcs *funcs; 132 133 struct mutex lock; 134 135 int num_dpll; 136 struct intel_dpll dplls[I915_NUM_PLLS]; 137 const struct intel_dpll_mgr *mgr; 138 139 struct { 140 int nssc; 141 int ssc; 142 } ref_clks; 143 144 /* 145 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 146 */ 147 u8 pch_ssc_use; 148 }; 149 150 struct intel_frontbuffer_tracking { 151 /* protects busy_bits */ 152 spinlock_t lock; 153 154 /* 155 * Tracking bits for delayed frontbuffer flushing due to gpu activity. 156 */ 157 unsigned busy_bits; 158 }; 159 160 struct intel_hotplug { 161 /* internal hotplug irq functions */ 162 const struct intel_hotplug_irq_funcs *funcs; 163 164 struct delayed_work hotplug_work; 165 166 const u32 *hpd, *pch_hpd; 167 168 struct { 169 unsigned long last_jiffies; 170 int count; 171 int blocked_count; 172 enum { 173 HPD_ENABLED = 0, 174 HPD_DISABLED = 1, 175 HPD_MARK_DISABLED = 2 176 } state; 177 } stats[HPD_NUM_PINS]; 178 u32 event_bits; 179 u32 retry_bits; 180 struct delayed_work reenable_work; 181 182 u32 long_hpd_pin_mask; 183 u32 short_hpd_pin_mask; 184 struct work_struct dig_port_work; 185 186 struct work_struct poll_init_work; 187 bool poll_enabled; 188 189 /* 190 * Queuing of hotplug_work, reenable_work and poll_init_work is 191 * enabled. Protected by intel_display::irq::lock. 192 */ 193 bool detection_work_enabled; 194 195 unsigned int hpd_storm_threshold; 196 /* Whether or not to count short HPD IRQs in HPD storms */ 197 u8 hpd_short_storm_enabled; 198 199 /* Last state reported by oob_hotplug_event for each encoder */ 200 unsigned long oob_hotplug_last_state; 201 202 /* 203 * if we get a HPD irq from DP and a HPD irq from non-DP 204 * the non-DP HPD could block the workqueue on a mode config 205 * mutex getting, that userspace may have taken. However 206 * userspace is waiting on the DP workqueue to run which is 207 * blocked behind the non-DP one. 208 */ 209 struct workqueue_struct *dp_wq; 210 211 /* 212 * Flag to track if long HPDs need not to be processed 213 * 214 * Some panels generate long HPDs while keep connected to the port. 215 * This can cause issues with CI tests results. In CI systems we 216 * don't expect to disconnect the panels and could ignore the long 217 * HPDs generated from the faulty panels. This flag can be used as 218 * cue to ignore the long HPDs and can be set / unset using debugfs. 219 */ 220 bool ignore_long_hpd; 221 }; 222 223 struct intel_vbt_data { 224 /* bdb version */ 225 u16 version; 226 227 /* Feature bits */ 228 unsigned int int_tv_support:1; 229 unsigned int int_crt_support:1; 230 unsigned int lvds_use_ssc:1; 231 unsigned int int_lvds_support:1; 232 unsigned int display_clock_mode:1; 233 unsigned int fdi_rx_polarity_inverted:1; 234 int lvds_ssc_freq; 235 enum drm_panel_orientation orientation; 236 237 bool override_afc_startup; 238 u8 override_afc_startup_val; 239 240 int crt_ddc_pin; 241 242 struct list_head display_devices; 243 struct list_head bdb_blocks; 244 245 struct sdvo_device_mapping { 246 u8 initialized; 247 u8 dvo_port; 248 u8 target_addr; 249 u8 dvo_wiring; 250 u8 i2c_pin; 251 u8 ddc_pin; 252 } sdvo_mappings[2]; 253 }; 254 255 struct intel_wm { 256 /* internal watermark functions */ 257 const struct intel_wm_funcs *funcs; 258 259 /* 260 * Raw watermark latency values: 261 * in 0.1us units for WM0, 262 * in 0.5us units for WM1+. 263 */ 264 /* primary */ 265 u16 pri_latency[5]; 266 /* sprite */ 267 u16 spr_latency[5]; 268 /* cursor */ 269 u16 cur_latency[5]; 270 /* 271 * Raw watermark memory latency values 272 * for SKL for all 8 levels 273 * in 1us units. 274 */ 275 u16 skl_latency[8]; 276 277 /* current hardware state */ 278 union { 279 struct ilk_wm_values hw; 280 struct vlv_wm_values vlv; 281 struct g4x_wm_values g4x; 282 }; 283 284 u8 num_levels; 285 286 /* 287 * Should be held around atomic WM register writing; also 288 * protects * intel_crtc->wm.active and 289 * crtc_state->wm.need_postvbl_update. 290 */ 291 struct mutex wm_mutex; 292 293 bool ipc_enabled; 294 }; 295 296 struct intel_display { 297 /* drm device backpointer */ 298 struct drm_device *drm; 299 300 /* Platform (and subplatform, if any) identification */ 301 struct intel_display_platforms platform; 302 303 /* Intel PCH: where the south display engine lives */ 304 enum intel_pch pch_type; 305 306 /* Parent, or core, driver functions exposed to display */ 307 const struct intel_display_parent_interface *parent; 308 309 /* list of all intel_crtcs sorted by pipe */ 310 struct list_head pipe_list; 311 312 struct { 313 bool any_task_allowed; 314 struct task_struct *allowed_task; 315 } access; 316 317 struct { 318 /* backlight registers and fields in struct intel_panel */ 319 struct mutex lock; 320 } backlight; 321 322 struct { 323 struct intel_global_obj obj; 324 325 struct intel_bw_info { 326 /* for each QGV point */ 327 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 328 /* for each PSF GV point */ 329 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 330 /* Peak BW for each QGV point */ 331 unsigned int peakbw[I915_NUM_QGV_POINTS]; 332 u8 num_qgv_points; 333 u8 num_psf_gv_points; 334 u8 num_planes; 335 } max[6]; 336 } bw; 337 338 struct { 339 /* Internal CDCLK functions */ 340 const struct intel_cdclk_funcs *funcs; 341 342 /* The current hardware cdclk configuration */ 343 struct intel_cdclk_config hw; 344 345 /* cdclk, divider, and ratio table from bspec */ 346 const struct intel_cdclk_vals *table; 347 348 struct intel_global_obj obj; 349 350 unsigned int max_cdclk_freq; 351 unsigned int max_dotclk_freq; 352 unsigned int skl_preferred_vco_freq; 353 } cdclk; 354 355 struct { 356 /* internal color functions */ 357 const struct intel_color_funcs *funcs; 358 359 struct drm_property_blob *glk_linear_degamma_lut; 360 } color; 361 362 struct { 363 /* The current hardware dbuf configuration */ 364 u8 enabled_slices; 365 366 struct intel_global_obj obj; 367 } dbuf; 368 369 struct { 370 struct intel_global_obj obj; 371 } dbuf_bw; 372 373 struct { 374 /* 375 * dkl.phy_lock protects against concurrent access of the 376 * Dekel TypeC PHYs. 377 */ 378 spinlock_t phy_lock; 379 } dkl; 380 381 struct { 382 struct intel_dmc *dmc; 383 struct ref_tracker *wakeref; 384 } dmc; 385 386 struct { 387 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 388 u32 mmio_base; 389 } dsi; 390 391 struct { 392 const struct dram_info *info; 393 } dram; 394 395 struct { 396 struct intel_fbc *instances[I915_MAX_FBCS]; 397 398 /* xe3p_lpd+: FBC instance utilizing the system cache */ 399 struct sys_cache_cfg { 400 /* Protect concurrecnt access to system cache configuration */ 401 struct mutex lock; 402 enum intel_fbc_id id; 403 } sys_cache; 404 } fbc; 405 406 struct { 407 /* list of fbdev register on this device */ 408 struct intel_fbdev *fbdev; 409 } fbdev; 410 411 struct { 412 /* internal fdi functions */ 413 const struct intel_fdi_funcs *funcs; 414 415 unsigned int pll_freq; 416 u32 rx_config; 417 } fdi; 418 419 struct { 420 struct list_head obj_list; 421 } global; 422 423 struct { 424 /* 425 * Base address of where the gmbus and gpio blocks are located 426 * (either on PCH or on SoC for platforms without PCH). 427 */ 428 u32 mmio_base; 429 430 /* 431 * gmbus.mutex protects against concurrent usage of the single 432 * hw gmbus controller on different i2c buses. 433 */ 434 struct mutex mutex; 435 436 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 437 438 wait_queue_head_t wait_queue; 439 } gmbus; 440 441 struct { 442 struct i915_hdcp_arbiter *arbiter; 443 bool comp_added; 444 445 /* 446 * HDCP message struct for allocation of memory which can be 447 * reused when sending message to gsc cs. 448 * this is only populated post Meteorlake 449 */ 450 struct intel_hdcp_gsc_context *gsc_context; 451 /* Mutex to protect the above hdcp related values. */ 452 struct mutex hdcp_mutex; 453 } hdcp; 454 455 struct { 456 /* 457 * HTI (aka HDPORT) state read during initial hw readout. Most 458 * platforms don't have HTI, so this will just stay 0. Those 459 * that do will use this later to figure out which PLLs and PHYs 460 * are unavailable for driver usage. 461 */ 462 u32 state; 463 } hti; 464 465 struct { 466 /* Access with DISPLAY_INFO() */ 467 const struct intel_display_device_info *__device_info; 468 469 /* Access with DISPLAY_RUNTIME_INFO() */ 470 struct intel_display_runtime_info __runtime_info; 471 } info; 472 473 struct { 474 bool false_color; 475 } ips; 476 477 struct { 478 /* internal display irq functions */ 479 const struct intel_display_irq_funcs *funcs; 480 481 /* protects the irq masks */ 482 spinlock_t lock; 483 484 /* 485 * Most platforms treat the display irq block as an always-on 486 * power domain. vlv/chv can disable it at runtime and need 487 * special care to avoid writing any of the display block 488 * registers outside of the power domain. We defer setting up 489 * the display irqs in this case to the runtime pm. 490 */ 491 bool vlv_display_irqs_enabled; 492 493 /* For i915gm/i945gm vblank irq workaround */ 494 u8 vblank_enabled; 495 496 int vblank_enable_count; 497 bool vblank_status_last_notified; 498 499 struct work_struct vblank_notify_work; 500 501 /* 502 * Cached value of VLV/CHV IMR to avoid reads in updating the 503 * bitfield. 504 */ 505 u32 vlv_imr_mask; 506 /* 507 * Cached value of gen 5-7 DE IMR to avoid reads in updating the 508 * bitfield. 509 */ 510 u32 ilk_de_imr_mask; 511 /* 512 * Cached value of BDW+ DE pipe IMR to avoid reads in updating 513 * the bitfield. 514 */ 515 u32 de_pipe_imr_mask[I915_MAX_PIPES]; 516 u32 pipestat_irq_mask[I915_MAX_PIPES]; 517 } irq; 518 519 struct { 520 /* Top level crtc-ish functions */ 521 const struct intel_modeset_funcs *funcs; 522 } modeset; 523 524 struct { 525 /* protected by wm.wm_mutex */ 526 u16 linetime[I915_MAX_PIPES]; 527 bool disable[I915_MAX_PIPES]; 528 } pkgc; 529 530 struct { 531 wait_queue_head_t waitqueue; 532 533 /* mutex to protect pmdemand programming sequence */ 534 struct mutex lock; 535 536 struct intel_global_obj obj; 537 } pmdemand; 538 539 struct { 540 struct i915_power_domains domains; 541 542 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 543 u32 chv_phy_control; 544 545 /* perform PHY state sanity checks? */ 546 bool chv_phy_assert[2]; 547 } power; 548 549 struct { 550 u32 mmio_base; 551 552 /* protects panel power sequencer state */ 553 struct mutex mutex; 554 } pps; 555 556 struct { 557 struct drm_property *broadcast_rgb; 558 struct drm_property *force_audio; 559 } properties; 560 561 struct { 562 unsigned long mask; 563 } quirks; 564 565 struct { 566 u32 count; 567 } reset; 568 569 struct { 570 /* restore state for suspend/resume and display reset */ 571 struct drm_atomic_commit *modeset_state; 572 struct drm_modeset_acquire_ctx reset_ctx; 573 /* modeset stuck tracking for reset */ 574 u32 saveDSPARB; 575 u32 saveSWF0[16]; 576 u32 saveSWF1[16]; 577 u32 saveSWF3[3]; 578 u16 saveGCDGMBUS; 579 } restore; 580 581 struct { 582 enum { 583 I915_SAGV_UNKNOWN = 0, 584 I915_SAGV_DISABLED, 585 I915_SAGV_ENABLED, 586 I915_SAGV_NOT_CONTROLLED 587 } status; 588 589 u32 block_time_us; 590 } sagv; 591 592 struct { 593 /* LPT/WPT IOSF sideband protection */ 594 struct mutex lock; 595 } sbi; 596 597 struct { 598 /* 599 * DG2: Mask of PHYs that were not calibrated by the firmware 600 * and should not be used. 601 */ 602 u8 phy_failed_calibration; 603 } snps; 604 605 struct { 606 /* 607 * Shadows for CHV DPLL_MD regs to keep the state 608 * checker somewhat working in the presence hardware 609 * crappiness (can't read out DPLL_MD for pipes B & C). 610 */ 611 u32 chv_dpll_md[I915_MAX_PIPES]; 612 u32 bxt_phy_grc; 613 } state; 614 615 struct { 616 unsigned int hpll_freq; 617 unsigned int czclk_freq; 618 } vlv_clock; 619 620 struct { 621 /* ordered wq for modesets */ 622 struct workqueue_struct *modeset; 623 624 /* unbound hipri wq for page flips/plane updates */ 625 struct workqueue_struct *flip; 626 627 /* hipri wq for commit cleanups */ 628 struct workqueue_struct *cleanup; 629 630 /* unordered workqueue for all display unordered work */ 631 struct workqueue_struct *unordered; 632 } wq; 633 634 /* Grouping using named structs. Keep sorted. */ 635 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 636 struct intel_audio audio; 637 struct intel_dpll_global dpll; 638 struct intel_frontbuffer_tracking fb_tracking; 639 struct intel_hotplug hotplug; 640 struct intel_opregion *opregion; 641 struct intel_overlay *overlay; 642 struct intel_display_params params; 643 struct intel_vbt_data vbt; 644 struct intel_dmc_wl wl; 645 struct intel_wm wm; 646 647 struct work_struct psr_dc5_dc6_wa_work; 648 }; 649 650 #endif /* __INTEL_DISPLAY_CORE_H__ */ 651