1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2006-2007 PA Semi, Inc
4 *
5 * Authors: Kip Walker, PA Semi
6 * Olof Johansson, PA Semi
7 *
8 * Maintained by: Olof Johansson <olof@lixom.net>
9 *
10 * Based on arch/powerpc/platforms/maple/setup.c
11 */
12
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/console.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/of.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/gfp.h>
23 #include <linux/irqdomain.h>
24
25 #include <asm/iommu.h>
26 #include <asm/machdep.h>
27 #include <asm/i8259.h>
28 #include <asm/mpic.h>
29 #include <asm/smp.h>
30 #include <asm/time.h>
31 #include <asm/mmu.h>
32 #include <asm/debug.h>
33
34 #include <pcmcia/ss.h>
35 #include <pcmcia/cistpl.h>
36 #include <pcmcia/ds.h>
37
38 #include "pasemi.h"
39
40 /* SDC reset register, must be pre-mapped at reset time */
41 static void __iomem *reset_reg;
42
43 /* Various error status registers, must be pre-mapped at MCE time */
44
45 #define MAX_MCE_REGS 32
46 struct mce_regs {
47 char *name;
48 void __iomem *addr;
49 };
50
51 static struct mce_regs mce_regs[MAX_MCE_REGS];
52 static int num_mce_regs;
53 static int nmi_virq = 0;
54
55
pas_restart(char * cmd)56 static void __noreturn pas_restart(char *cmd)
57 {
58 /* Need to put others cpu in hold loop so they're not sleeping */
59 smp_send_stop();
60 udelay(10000);
61 printk("Restarting...\n");
62 while (1)
63 out_le32(reset_reg, 0x6000000);
64 }
65
66 #ifdef CONFIG_PPC_PASEMI_NEMO
pas_shutdown(void)67 static void pas_shutdown(void)
68 {
69 /* Set the PLD bit that makes the SB600 think the power button is being pressed */
70 void __iomem *pld_map = ioremap(0xf5000000,4096);
71 while (1)
72 out_8(pld_map+7,0x01);
73 }
74
75 /* RTC platform device structure as is not in device tree */
76 static struct resource rtc_resource[] = {{
77 .name = "rtc",
78 .start = 0x70,
79 .end = 0x71,
80 .flags = IORESOURCE_IO,
81 }, {
82 .name = "rtc",
83 .start = 8,
84 .end = 8,
85 .flags = IORESOURCE_IRQ,
86 }};
87
nemo_init_rtc(void)88 static inline void nemo_init_rtc(void)
89 {
90 platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2);
91 }
92
93 #else
94
nemo_init_rtc(void)95 static inline void nemo_init_rtc(void)
96 {
97 }
98 #endif
99
100 #ifdef CONFIG_SMP
101 static arch_spinlock_t timebase_lock;
102 static unsigned long timebase;
103
pas_give_timebase(void)104 static void pas_give_timebase(void)
105 {
106 unsigned long flags;
107
108 local_irq_save(flags);
109 hard_irq_disable();
110 arch_spin_lock(&timebase_lock);
111 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
112 isync();
113 timebase = get_tb();
114 arch_spin_unlock(&timebase_lock);
115
116 while (timebase)
117 barrier();
118 mtspr(SPRN_TBCTL, TBCTL_RESTART);
119 local_irq_restore(flags);
120 }
121
pas_take_timebase(void)122 static void pas_take_timebase(void)
123 {
124 while (!timebase)
125 smp_rmb();
126
127 arch_spin_lock(&timebase_lock);
128 set_tb(timebase >> 32, timebase & 0xffffffff);
129 timebase = 0;
130 arch_spin_unlock(&timebase_lock);
131 }
132
133 static struct smp_ops_t pas_smp_ops = {
134 .probe = smp_mpic_probe,
135 .message_pass = smp_mpic_message_pass,
136 .kick_cpu = smp_generic_kick_cpu,
137 .setup_cpu = smp_mpic_setup_cpu,
138 .give_timebase = pas_give_timebase,
139 .take_timebase = pas_take_timebase,
140 };
141 #endif /* CONFIG_SMP */
142
pas_setup_arch(void)143 static void __init pas_setup_arch(void)
144 {
145 #ifdef CONFIG_SMP
146 /* Setup SMP callback */
147 smp_ops = &pas_smp_ops;
148 #endif
149
150 /* Remap SDC register for doing reset */
151 /* XXXOJN This should maybe come out of the device tree */
152 reset_reg = ioremap(0xfc101100, 4);
153 }
154
pas_setup_mce_regs(void)155 static int __init pas_setup_mce_regs(void)
156 {
157 struct pci_dev *dev;
158 int reg;
159
160 /* Remap various SoC status registers for use by the MCE handler */
161
162 reg = 0;
163
164 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
165 while (dev && reg < MAX_MCE_REGS) {
166 mce_regs[reg].name = kasprintf(GFP_KERNEL,
167 "mc%d_mcdebug_errsta", reg);
168 if (!mce_regs[reg].name)
169 return -ENOMEM;
170 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
171 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
172 reg++;
173 }
174
175 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
176 if (dev && reg+4 < MAX_MCE_REGS) {
177 mce_regs[reg].name = "iobdbg_IntStatus1";
178 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
179 reg++;
180 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
181 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
182 reg++;
183 mce_regs[reg].name = "iobiom_IntStatus";
184 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
185 reg++;
186 mce_regs[reg].name = "iobiom_IntDbgReg";
187 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
188 reg++;
189 }
190
191 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
192 if (dev && reg+2 < MAX_MCE_REGS) {
193 mce_regs[reg].name = "l2csts_IntStatus";
194 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
195 reg++;
196 mce_regs[reg].name = "l2csts_Cnt";
197 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
198 reg++;
199 }
200
201 num_mce_regs = reg;
202
203 return 0;
204 }
205 machine_device_initcall(pasemi, pas_setup_mce_regs);
206
207 #ifdef CONFIG_PPC_PASEMI_NEMO
sb600_8259_cascade(struct irq_desc * desc)208 static void sb600_8259_cascade(struct irq_desc *desc)
209 {
210 struct irq_chip *chip = irq_desc_get_chip(desc);
211 unsigned int cascade_irq = i8259_irq();
212
213 if (cascade_irq)
214 generic_handle_irq(cascade_irq);
215
216 chip->irq_eoi(&desc->irq_data);
217 }
218
nemo_init_IRQ(struct mpic * mpic)219 static void __init nemo_init_IRQ(struct mpic *mpic)
220 {
221 struct device_node *np;
222 int gpio_virq;
223 /* Connect the SB600's legacy i8259 controller */
224 np = of_find_node_by_path("/pxp@0,e0000000");
225 i8259_init(np, 0);
226 of_node_put(np);
227
228 gpio_virq = irq_create_mapping(NULL, 3);
229 irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH);
230 irq_set_chained_handler(gpio_virq, sb600_8259_cascade);
231 mpic_unmask_irq(irq_get_irq_data(gpio_virq));
232
233 irq_set_default_domain(mpic->irqhost);
234 }
235
236 #else
237
nemo_init_IRQ(struct mpic * mpic)238 static inline void nemo_init_IRQ(struct mpic *mpic)
239 {
240 }
241 #endif
242
pas_init_IRQ(void)243 static __init void pas_init_IRQ(void)
244 {
245 struct device_node *np;
246 struct device_node *root, *mpic_node;
247 unsigned long openpic_addr;
248 const unsigned int *opprop;
249 int naddr, opplen;
250 int mpic_flags;
251 const unsigned int *nmiprop;
252 struct mpic *mpic;
253
254 mpic_node = NULL;
255
256 for_each_node_by_type(np, "interrupt-controller")
257 if (of_device_is_compatible(np, "open-pic")) {
258 mpic_node = np;
259 break;
260 }
261 if (!mpic_node)
262 for_each_node_by_type(np, "open-pic") {
263 mpic_node = np;
264 break;
265 }
266 if (!mpic_node) {
267 pr_err("Failed to locate the MPIC interrupt controller\n");
268 return;
269 }
270
271 /* Find address list in /platform-open-pic */
272 root = of_find_node_by_path("/");
273 naddr = of_n_addr_cells(root);
274 opprop = of_get_property(root, "platform-open-pic", &opplen);
275 if (!opprop) {
276 pr_err("No platform-open-pic property.\n");
277 of_node_put(root);
278 return;
279 }
280 openpic_addr = of_read_number(opprop, naddr);
281 pr_debug("OpenPIC addr: %lx\n", openpic_addr);
282
283 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;
284
285 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
286 if (nmiprop)
287 mpic_flags |= MPIC_ENABLE_MCK;
288
289 mpic = mpic_alloc(mpic_node, openpic_addr,
290 mpic_flags, 0, 0, "PASEMI-OPIC");
291 BUG_ON(!mpic);
292
293 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
294 mpic_init(mpic);
295 /* The NMI/MCK source needs to be prio 15 */
296 if (nmiprop) {
297 nmi_virq = irq_create_mapping(NULL, *nmiprop);
298 mpic_irq_set_priority(nmi_virq, 15);
299 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
300 mpic_unmask_irq(irq_get_irq_data(nmi_virq));
301 }
302
303 nemo_init_IRQ(mpic);
304
305 of_node_put(mpic_node);
306 of_node_put(root);
307 }
308
pas_progress(char * s,unsigned short hex)309 static void __init pas_progress(char *s, unsigned short hex)
310 {
311 printk("[%04x] : %s\n", hex, s ? s : "");
312 }
313
314
pas_machine_check_handler(struct pt_regs * regs)315 static int pas_machine_check_handler(struct pt_regs *regs)
316 {
317 int cpu = smp_processor_id();
318 unsigned long srr0, srr1, dsisr;
319 int dump_slb = 0;
320 int i;
321
322 srr0 = regs->nip;
323 srr1 = regs->msr;
324
325 if (nmi_virq && mpic_get_mcirq() == nmi_virq) {
326 pr_err("NMI delivered\n");
327 debugger(regs);
328 mpic_end_irq(irq_get_irq_data(nmi_virq));
329 goto out;
330 }
331
332 dsisr = mfspr(SPRN_DSISR);
333 pr_err("Machine Check on CPU %d\n", cpu);
334 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
335 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
336 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
337 mfspr(SPRN_PA6T_MER));
338 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
339 mfspr(SPRN_PA6T_DER));
340 pr_err("Cause:\n");
341
342 if (srr1 & 0x200000)
343 pr_err("Signalled by SDC\n");
344
345 if (srr1 & 0x100000) {
346 pr_err("Load/Store detected error:\n");
347 if (dsisr & 0x8000)
348 pr_err("D-cache ECC double-bit error or bus error\n");
349 if (dsisr & 0x4000)
350 pr_err("LSU snoop response error\n");
351 if (dsisr & 0x2000) {
352 pr_err("MMU SLB multi-hit or invalid B field\n");
353 dump_slb = 1;
354 }
355 if (dsisr & 0x1000)
356 pr_err("Recoverable Duptags\n");
357 if (dsisr & 0x800)
358 pr_err("Recoverable D-cache parity error count overflow\n");
359 if (dsisr & 0x400)
360 pr_err("TLB parity error count overflow\n");
361 }
362
363 if (srr1 & 0x80000)
364 pr_err("Bus Error\n");
365
366 if (srr1 & 0x40000) {
367 pr_err("I-side SLB multiple hit\n");
368 dump_slb = 1;
369 }
370
371 if (srr1 & 0x20000)
372 pr_err("I-cache parity error hit\n");
373
374 if (num_mce_regs == 0)
375 pr_err("No MCE registers mapped yet, can't dump\n");
376 else
377 pr_err("SoC debug registers:\n");
378
379 for (i = 0; i < num_mce_regs; i++)
380 pr_err("%s: 0x%08x\n", mce_regs[i].name,
381 in_le32(mce_regs[i].addr));
382
383 if (dump_slb) {
384 unsigned long e, v;
385 int i;
386
387 pr_err("slb contents:\n");
388 for (i = 0; i < mmu_slb_size; i++) {
389 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
390 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
391 pr_err("%02d %016lx %016lx\n", i, e, v);
392 }
393 }
394
395 out:
396 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
397 return !!(srr1 & 0x2);
398 }
399
400 static const struct of_device_id pasemi_bus_ids[] = {
401 /* Unfortunately needed for legacy firmwares */
402 { .type = "localbus", },
403 { .type = "sdc", },
404 /* These are the proper entries, which newer firmware uses */
405 { .compatible = "pasemi,localbus", },
406 { .compatible = "pasemi,sdc", },
407 {},
408 };
409
pasemi_publish_devices(void)410 static int __init pasemi_publish_devices(void)
411 {
412 /* Publish OF platform devices for SDC and other non-PCI devices */
413 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
414
415 nemo_init_rtc();
416
417 return 0;
418 }
419 machine_device_initcall(pasemi, pasemi_publish_devices);
420
421
422 /*
423 * Called very early, MMU is off, device-tree isn't unflattened
424 */
pas_probe(void)425 static int __init pas_probe(void)
426 {
427 if (!of_machine_is_compatible("PA6T-1682M") &&
428 !of_machine_is_compatible("pasemi,pwrficient"))
429 return 0;
430
431 #ifdef CONFIG_PPC_PASEMI_NEMO
432 /*
433 * Check for the Nemo motherboard here, if we are running on one
434 * change the machine definition to fit
435 */
436 if (of_machine_is_compatible("pasemi,nemo")) {
437 pm_power_off = pas_shutdown;
438 ppc_md.name = "A-EON Amigaone X1000";
439 }
440 #endif
441
442 iommu_init_early_pasemi();
443
444 return 1;
445 }
446
define_machine(pasemi)447 define_machine(pasemi) {
448 .name = "PA Semi PWRficient",
449 .probe = pas_probe,
450 .setup_arch = pas_setup_arch,
451 .discover_phbs = pas_pci_init,
452 .init_IRQ = pas_init_IRQ,
453 .get_irq = mpic_get_irq,
454 .restart = pas_restart,
455 .get_boot_time = pas_get_boot_time,
456 .progress = pas_progress,
457 .machine_check_exception = pas_machine_check_handler,
458 };
459