1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/seq_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sort.h>
34 #include <linux/string_helpers.h>
35 #include <linux/timekeeping.h>
36 #include <linux/types.h>
37
38 #include <asm/byteorder.h>
39
40 #include <drm/display/drm_dp_helper.h>
41 #include <drm/display/drm_dp_tunnel.h>
42 #include <drm/display/drm_dsc_helper.h>
43 #include <drm/display/drm_hdmi_helper.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_crtc.h>
46 #include <drm/drm_edid.h>
47 #include <drm/drm_fixed.h>
48 #include <drm/drm_probe_helper.h>
49
50 #include "g4x_dp.h"
51 #include "i915_drv.h"
52 #include "i915_irq.h"
53 #include "i915_reg.h"
54 #include "intel_alpm.h"
55 #include "intel_atomic.h"
56 #include "intel_audio.h"
57 #include "intel_backlight.h"
58 #include "intel_combo_phy_regs.h"
59 #include "intel_connector.h"
60 #include "intel_crtc.h"
61 #include "intel_cx0_phy.h"
62 #include "intel_ddi.h"
63 #include "intel_de.h"
64 #include "intel_display_driver.h"
65 #include "intel_display_types.h"
66 #include "intel_dp.h"
67 #include "intel_dp_aux.h"
68 #include "intel_dp_hdcp.h"
69 #include "intel_dp_link_training.h"
70 #include "intel_dp_mst.h"
71 #include "intel_dp_test.h"
72 #include "intel_dp_tunnel.h"
73 #include "intel_dpio_phy.h"
74 #include "intel_dpll.h"
75 #include "intel_drrs.h"
76 #include "intel_encoder.h"
77 #include "intel_fifo_underrun.h"
78 #include "intel_hdcp.h"
79 #include "intel_hdmi.h"
80 #include "intel_hotplug.h"
81 #include "intel_hotplug_irq.h"
82 #include "intel_lspcon.h"
83 #include "intel_lvds.h"
84 #include "intel_modeset_lock.h"
85 #include "intel_panel.h"
86 #include "intel_pch_display.h"
87 #include "intel_pfit.h"
88 #include "intel_pps.h"
89 #include "intel_psr.h"
90 #include "intel_runtime_pm.h"
91 #include "intel_quirks.h"
92 #include "intel_tc.h"
93 #include "intel_vdsc.h"
94 #include "intel_vrr.h"
95 #include "intel_crtc_state_dump.h"
96
97 /* DP DSC throughput values used for slice count calculations KPixels/s */
98 #define DP_DSC_PEAK_PIXEL_RATE 2720000
99 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
100 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
101
102 /* Max DSC line buffer depth supported by HW. */
103 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
104
105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
106 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
107
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
110
111 /*
112 * With Single pipe configuration, HW is capable of supporting maximum of:
113 * 2 slices per line for ICL, BMG
114 * 4 slices per line for other platforms.
115 * For now consider a max of 2 slices per line, which works for all platforms.
116 * With this we can have max of 4 DSC Slices per pipe.
117 *
118 * For higher resolutions where 12 slice support is required with
119 * ultrajoiner, only then each pipe can support 3 slices.
120 *
121 * #TODO Split this better to use 4 slices/dsc engine where supported.
122 */
123 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
124
125 /**
126 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
127 * @intel_dp: DP struct
128 *
129 * If a CPU or PCH DP output is attached to an eDP panel, this function
130 * will return true, and false otherwise.
131 *
132 * This function is not safe to use prior to encoder type being set.
133 */
intel_dp_is_edp(struct intel_dp * intel_dp)134 bool intel_dp_is_edp(struct intel_dp *intel_dp)
135 {
136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
137
138 return dig_port->base.type == INTEL_OUTPUT_EDP;
139 }
140
141 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
142
143 /* Is link rate UHBR and thus 128b/132b? */
intel_dp_is_uhbr(const struct intel_crtc_state * crtc_state)144 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
145 {
146 return drm_dp_is_uhbr_rate(crtc_state->port_clock);
147 }
148
149 /**
150 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
151 * @rate: link rate in 10kbit/s units
152 *
153 * Returns the link symbol size in bits/symbol units depending on the link
154 * rate -> channel coding.
155 */
intel_dp_link_symbol_size(int rate)156 int intel_dp_link_symbol_size(int rate)
157 {
158 return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
159 }
160
161 /**
162 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
163 * @rate: link rate in 10kbit/s units
164 *
165 * Returns the link symbol clock frequency in kHz units depending on the
166 * link rate and channel coding.
167 */
intel_dp_link_symbol_clock(int rate)168 int intel_dp_link_symbol_clock(int rate)
169 {
170 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
171 }
172
max_dprx_rate(struct intel_dp * intel_dp)173 static int max_dprx_rate(struct intel_dp *intel_dp)
174 {
175 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
176 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
177
178 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
179 }
180
max_dprx_lane_count(struct intel_dp * intel_dp)181 static int max_dprx_lane_count(struct intel_dp *intel_dp)
182 {
183 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
184 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
185
186 return drm_dp_max_lane_count(intel_dp->dpcd);
187 }
188
intel_dp_set_default_sink_rates(struct intel_dp * intel_dp)189 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
190 {
191 intel_dp->sink_rates[0] = 162000;
192 intel_dp->num_sink_rates = 1;
193 }
194
195 /* update sink rates from dpcd */
intel_dp_set_dpcd_sink_rates(struct intel_dp * intel_dp)196 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
197 {
198 static const int dp_rates[] = {
199 162000, 270000, 540000, 810000
200 };
201 int i, max_rate;
202 int max_lttpr_rate;
203
204 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
205 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
206 static const int quirk_rates[] = { 162000, 270000, 324000 };
207
208 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
209 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
210
211 return;
212 }
213
214 /*
215 * Sink rates for 8b/10b.
216 */
217 max_rate = max_dprx_rate(intel_dp);
218 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
219 if (max_lttpr_rate)
220 max_rate = min(max_rate, max_lttpr_rate);
221
222 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
223 if (dp_rates[i] > max_rate)
224 break;
225 intel_dp->sink_rates[i] = dp_rates[i];
226 }
227
228 /*
229 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
230 * rates and 10 Gbps.
231 */
232 if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
233 u8 uhbr_rates = 0;
234
235 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
236
237 drm_dp_dpcd_readb(&intel_dp->aux,
238 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
239
240 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
241 /* We have a repeater */
242 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
243 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
244 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
245 DP_PHY_REPEATER_128B132B_SUPPORTED) {
246 /* Repeater supports 128b/132b, valid UHBR rates */
247 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
248 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
249 } else {
250 /* Does not support 128b/132b */
251 uhbr_rates = 0;
252 }
253 }
254
255 if (uhbr_rates & DP_UHBR10)
256 intel_dp->sink_rates[i++] = 1000000;
257 if (uhbr_rates & DP_UHBR13_5)
258 intel_dp->sink_rates[i++] = 1350000;
259 if (uhbr_rates & DP_UHBR20)
260 intel_dp->sink_rates[i++] = 2000000;
261 }
262
263 intel_dp->num_sink_rates = i;
264 }
265
intel_dp_set_sink_rates(struct intel_dp * intel_dp)266 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
267 {
268 struct intel_display *display = to_intel_display(intel_dp);
269 struct intel_connector *connector = intel_dp->attached_connector;
270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
271 struct intel_encoder *encoder = &intel_dig_port->base;
272
273 intel_dp_set_dpcd_sink_rates(intel_dp);
274
275 if (intel_dp->num_sink_rates)
276 return;
277
278 drm_err(display->drm,
279 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
280 connector->base.base.id, connector->base.name,
281 encoder->base.base.id, encoder->base.name);
282
283 intel_dp_set_default_sink_rates(intel_dp);
284 }
285
intel_dp_set_default_max_sink_lane_count(struct intel_dp * intel_dp)286 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
287 {
288 intel_dp->max_sink_lane_count = 1;
289 }
290
intel_dp_set_max_sink_lane_count(struct intel_dp * intel_dp)291 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
292 {
293 struct intel_display *display = to_intel_display(intel_dp);
294 struct intel_connector *connector = intel_dp->attached_connector;
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297
298 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
299
300 switch (intel_dp->max_sink_lane_count) {
301 case 1:
302 case 2:
303 case 4:
304 return;
305 }
306
307 drm_err(display->drm,
308 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
309 connector->base.base.id, connector->base.name,
310 encoder->base.base.id, encoder->base.name,
311 intel_dp->max_sink_lane_count);
312
313 intel_dp_set_default_max_sink_lane_count(intel_dp);
314 }
315
316 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)317 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
318 {
319 int i;
320
321 /* Limit results by potentially reduced max rate */
322 for (i = 0; i < len; i++) {
323 if (rates[len - i - 1] <= max_rate)
324 return len - i;
325 }
326
327 return 0;
328 }
329
330 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)331 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
332 int max_rate)
333 {
334 return intel_dp_rate_limit_len(intel_dp->common_rates,
335 intel_dp->num_common_rates, max_rate);
336 }
337
intel_dp_common_rate(struct intel_dp * intel_dp,int index)338 int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
339 {
340 struct intel_display *display = to_intel_display(intel_dp);
341
342 if (drm_WARN_ON(display->drm,
343 index < 0 || index >= intel_dp->num_common_rates))
344 return 162000;
345
346 return intel_dp->common_rates[index];
347 }
348
349 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)350 int intel_dp_max_common_rate(struct intel_dp *intel_dp)
351 {
352 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
353 }
354
intel_dp_max_source_lane_count(struct intel_digital_port * dig_port)355 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
356 {
357 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
358 int max_lanes = dig_port->max_lanes;
359
360 if (vbt_max_lanes)
361 max_lanes = min(max_lanes, vbt_max_lanes);
362
363 return max_lanes;
364 }
365
366 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)367 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
368 {
369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
370 int source_max = intel_dp_max_source_lane_count(dig_port);
371 int sink_max = intel_dp->max_sink_lane_count;
372 int lane_max = intel_tc_port_max_lane_count(dig_port);
373 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
374
375 if (lttpr_max)
376 sink_max = min(sink_max, lttpr_max);
377
378 return min3(source_max, sink_max, lane_max);
379 }
380
forced_lane_count(struct intel_dp * intel_dp)381 static int forced_lane_count(struct intel_dp *intel_dp)
382 {
383 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
384 }
385
intel_dp_max_lane_count(struct intel_dp * intel_dp)386 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
387 {
388 int lane_count;
389
390 if (intel_dp->link.force_lane_count)
391 lane_count = forced_lane_count(intel_dp);
392 else
393 lane_count = intel_dp->link.max_lane_count;
394
395 switch (lane_count) {
396 case 1:
397 case 2:
398 case 4:
399 return lane_count;
400 default:
401 MISSING_CASE(lane_count);
402 return 1;
403 }
404 }
405
intel_dp_min_lane_count(struct intel_dp * intel_dp)406 static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
407 {
408 if (intel_dp->link.force_lane_count)
409 return forced_lane_count(intel_dp);
410
411 return 1;
412 }
413
414 /*
415 * The required data bandwidth for a mode with given pixel clock and bpp. This
416 * is the required net bandwidth independent of the data bandwidth efficiency.
417 *
418 * TODO: check if callers of this functions should use
419 * intel_dp_effective_data_rate() instead.
420 */
421 int
intel_dp_link_required(int pixel_clock,int bpp)422 intel_dp_link_required(int pixel_clock, int bpp)
423 {
424 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
425 return DIV_ROUND_UP(pixel_clock * bpp, 8);
426 }
427
428 /**
429 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
430 * @pixel_clock: pixel clock in kHz
431 * @bpp_x16: bits per pixel .4 fixed point format
432 * @bw_overhead: BW allocation overhead in 1ppm units
433 *
434 * Return the effective pixel data rate in kB/sec units taking into account
435 * the provided SSC, FEC, DSC BW allocation overhead.
436 */
intel_dp_effective_data_rate(int pixel_clock,int bpp_x16,int bw_overhead)437 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
438 int bw_overhead)
439 {
440 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
441 1000000 * 16 * 8);
442 }
443
444 /**
445 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
446 * @intel_dp: Intel DP object
447 * @max_dprx_rate: Maximum data rate of the DPRX
448 * @max_dprx_lanes: Maximum lane count of the DPRX
449 *
450 * Calculate the maximum data rate for the provided link parameters taking into
451 * account any BW limitations by a DP tunnel attached to @intel_dp.
452 *
453 * Returns the maximum data rate in kBps units.
454 */
intel_dp_max_link_data_rate(struct intel_dp * intel_dp,int max_dprx_rate,int max_dprx_lanes)455 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
456 int max_dprx_rate, int max_dprx_lanes)
457 {
458 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
459
460 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
461 max_rate = min(max_rate,
462 drm_dp_tunnel_available_bw(intel_dp->tunnel));
463
464 return max_rate;
465 }
466
intel_dp_has_joiner(struct intel_dp * intel_dp)467 bool intel_dp_has_joiner(struct intel_dp *intel_dp)
468 {
469 struct intel_display *display = to_intel_display(intel_dp);
470 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
471 struct intel_encoder *encoder = &intel_dig_port->base;
472
473 /* eDP MSO is not compatible with joiner */
474 if (intel_dp->mso_link_count)
475 return false;
476
477 return DISPLAY_VER(display) >= 12 ||
478 (DISPLAY_VER(display) == 11 &&
479 encoder->port != PORT_A);
480 }
481
dg2_max_source_rate(struct intel_dp * intel_dp)482 static int dg2_max_source_rate(struct intel_dp *intel_dp)
483 {
484 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
485 }
486
icl_max_source_rate(struct intel_dp * intel_dp)487 static int icl_max_source_rate(struct intel_dp *intel_dp)
488 {
489 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
490
491 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
492 return 540000;
493
494 return 810000;
495 }
496
ehl_max_source_rate(struct intel_dp * intel_dp)497 static int ehl_max_source_rate(struct intel_dp *intel_dp)
498 {
499 if (intel_dp_is_edp(intel_dp))
500 return 540000;
501
502 return 810000;
503 }
504
mtl_max_source_rate(struct intel_dp * intel_dp)505 static int mtl_max_source_rate(struct intel_dp *intel_dp)
506 {
507 struct intel_display *display = to_intel_display(intel_dp);
508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
509
510 if (intel_encoder_is_c10phy(encoder))
511 return 810000;
512
513 if (DISPLAY_VERx100(display) == 1401)
514 return 1350000;
515
516 return 2000000;
517 }
518
vbt_max_link_rate(struct intel_dp * intel_dp)519 static int vbt_max_link_rate(struct intel_dp *intel_dp)
520 {
521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
522 int max_rate;
523
524 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
525
526 if (intel_dp_is_edp(intel_dp)) {
527 struct intel_connector *connector = intel_dp->attached_connector;
528 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
529
530 if (max_rate && edp_max_rate)
531 max_rate = min(max_rate, edp_max_rate);
532 else if (edp_max_rate)
533 max_rate = edp_max_rate;
534 }
535
536 return max_rate;
537 }
538
539 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)540 intel_dp_set_source_rates(struct intel_dp *intel_dp)
541 {
542 /* The values must be in increasing order */
543 static const int bmg_rates[] = {
544 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
545 810000, 1000000, 1350000,
546 };
547 static const int mtl_rates[] = {
548 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
549 810000, 1000000, 2000000,
550 };
551 static const int icl_rates[] = {
552 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
553 1000000, 1350000,
554 };
555 static const int bxt_rates[] = {
556 162000, 216000, 243000, 270000, 324000, 432000, 540000
557 };
558 static const int skl_rates[] = {
559 162000, 216000, 270000, 324000, 432000, 540000
560 };
561 static const int hsw_rates[] = {
562 162000, 270000, 540000
563 };
564 static const int g4x_rates[] = {
565 162000, 270000
566 };
567 struct intel_display *display = to_intel_display(intel_dp);
568 const int *source_rates;
569 int size, max_rate = 0, vbt_max_rate;
570
571 /* This should only be done once */
572 drm_WARN_ON(display->drm,
573 intel_dp->source_rates || intel_dp->num_source_rates);
574
575 if (DISPLAY_VER(display) >= 14) {
576 if (display->platform.battlemage) {
577 source_rates = bmg_rates;
578 size = ARRAY_SIZE(bmg_rates);
579 } else {
580 source_rates = mtl_rates;
581 size = ARRAY_SIZE(mtl_rates);
582 }
583 max_rate = mtl_max_source_rate(intel_dp);
584 } else if (DISPLAY_VER(display) >= 11) {
585 source_rates = icl_rates;
586 size = ARRAY_SIZE(icl_rates);
587 if (display->platform.dg2)
588 max_rate = dg2_max_source_rate(intel_dp);
589 else if (display->platform.alderlake_p || display->platform.alderlake_s ||
590 display->platform.dg1 || display->platform.rocketlake)
591 max_rate = 810000;
592 else if (display->platform.jasperlake || display->platform.elkhartlake)
593 max_rate = ehl_max_source_rate(intel_dp);
594 else
595 max_rate = icl_max_source_rate(intel_dp);
596 } else if (display->platform.geminilake || display->platform.broxton) {
597 source_rates = bxt_rates;
598 size = ARRAY_SIZE(bxt_rates);
599 } else if (DISPLAY_VER(display) == 9) {
600 source_rates = skl_rates;
601 size = ARRAY_SIZE(skl_rates);
602 } else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
603 display->platform.broadwell) {
604 source_rates = hsw_rates;
605 size = ARRAY_SIZE(hsw_rates);
606 } else {
607 source_rates = g4x_rates;
608 size = ARRAY_SIZE(g4x_rates);
609 }
610
611 vbt_max_rate = vbt_max_link_rate(intel_dp);
612 if (max_rate && vbt_max_rate)
613 max_rate = min(max_rate, vbt_max_rate);
614 else if (vbt_max_rate)
615 max_rate = vbt_max_rate;
616
617 if (max_rate)
618 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
619
620 intel_dp->source_rates = source_rates;
621 intel_dp->num_source_rates = size;
622 }
623
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)624 static int intersect_rates(const int *source_rates, int source_len,
625 const int *sink_rates, int sink_len,
626 int *common_rates)
627 {
628 int i = 0, j = 0, k = 0;
629
630 while (i < source_len && j < sink_len) {
631 if (source_rates[i] == sink_rates[j]) {
632 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
633 return k;
634 common_rates[k] = source_rates[i];
635 ++k;
636 ++i;
637 ++j;
638 } else if (source_rates[i] < sink_rates[j]) {
639 ++i;
640 } else {
641 ++j;
642 }
643 }
644 return k;
645 }
646
647 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)648 int intel_dp_rate_index(const int *rates, int len, int rate)
649 {
650 int i;
651
652 for (i = 0; i < len; i++)
653 if (rate == rates[i])
654 return i;
655
656 return -1;
657 }
658
intel_dp_link_config_rate(struct intel_dp * intel_dp,const struct intel_dp_link_config * lc)659 static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
660 const struct intel_dp_link_config *lc)
661 {
662 return intel_dp_common_rate(intel_dp, lc->link_rate_idx);
663 }
664
intel_dp_link_config_lane_count(const struct intel_dp_link_config * lc)665 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
666 {
667 return 1 << lc->lane_count_exp;
668 }
669
intel_dp_link_config_bw(struct intel_dp * intel_dp,const struct intel_dp_link_config * lc)670 static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
671 const struct intel_dp_link_config *lc)
672 {
673 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),
674 intel_dp_link_config_lane_count(lc));
675 }
676
link_config_cmp_by_bw(const void * a,const void * b,const void * p)677 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
678 {
679 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
680 const struct intel_dp_link_config *lc_a = a;
681 const struct intel_dp_link_config *lc_b = b;
682 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);
683 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);
684
685 if (bw_a != bw_b)
686 return bw_a - bw_b;
687
688 return intel_dp_link_config_rate(intel_dp, lc_a) -
689 intel_dp_link_config_rate(intel_dp, lc_b);
690 }
691
intel_dp_link_config_init(struct intel_dp * intel_dp)692 static void intel_dp_link_config_init(struct intel_dp *intel_dp)
693 {
694 struct intel_display *display = to_intel_display(intel_dp);
695 struct intel_dp_link_config *lc;
696 int num_common_lane_configs;
697 int i;
698 int j;
699
700 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
701 return;
702
703 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
704
705 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
706 ARRAY_SIZE(intel_dp->link.configs)))
707 return;
708
709 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
710
711 lc = &intel_dp->link.configs[0];
712 for (i = 0; i < intel_dp->num_common_rates; i++) {
713 for (j = 0; j < num_common_lane_configs; j++) {
714 lc->lane_count_exp = j;
715 lc->link_rate_idx = i;
716
717 lc++;
718 }
719 }
720
721 sort_r(intel_dp->link.configs, intel_dp->link.num_configs,
722 sizeof(intel_dp->link.configs[0]),
723 link_config_cmp_by_bw, NULL,
724 intel_dp);
725 }
726
intel_dp_link_config_get(struct intel_dp * intel_dp,int idx,int * link_rate,int * lane_count)727 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
728 {
729 struct intel_display *display = to_intel_display(intel_dp);
730 const struct intel_dp_link_config *lc;
731
732 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
733 idx = 0;
734
735 lc = &intel_dp->link.configs[idx];
736
737 *link_rate = intel_dp_link_config_rate(intel_dp, lc);
738 *lane_count = intel_dp_link_config_lane_count(lc);
739 }
740
intel_dp_link_config_index(struct intel_dp * intel_dp,int link_rate,int lane_count)741 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
742 {
743 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,
744 link_rate);
745 int lane_count_exp = ilog2(lane_count);
746 int i;
747
748 for (i = 0; i < intel_dp->link.num_configs; i++) {
749 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
750
751 if (lc->lane_count_exp == lane_count_exp &&
752 lc->link_rate_idx == link_rate_idx)
753 return i;
754 }
755
756 return -1;
757 }
758
intel_dp_set_common_rates(struct intel_dp * intel_dp)759 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
760 {
761 struct intel_display *display = to_intel_display(intel_dp);
762
763 drm_WARN_ON(display->drm,
764 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
765
766 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
767 intel_dp->num_source_rates,
768 intel_dp->sink_rates,
769 intel_dp->num_sink_rates,
770 intel_dp->common_rates);
771
772 /* Paranoia, there should always be something in common. */
773 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
774 intel_dp->common_rates[0] = 162000;
775 intel_dp->num_common_rates = 1;
776 }
777
778 intel_dp_link_config_init(intel_dp);
779 }
780
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)781 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
782 u8 lane_count)
783 {
784 /*
785 * FIXME: we need to synchronize the current link parameters with
786 * hardware readout. Currently fast link training doesn't work on
787 * boot-up.
788 */
789 if (link_rate == 0 ||
790 link_rate > intel_dp->link.max_rate)
791 return false;
792
793 if (lane_count == 0 ||
794 lane_count > intel_dp_max_lane_count(intel_dp))
795 return false;
796
797 return true;
798 }
799
intel_dp_mode_to_fec_clock(u32 mode_clock)800 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
801 {
802 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
803 1000000U);
804 }
805
intel_dp_bw_fec_overhead(bool fec_enabled)806 int intel_dp_bw_fec_overhead(bool fec_enabled)
807 {
808 /*
809 * TODO: Calculate the actual overhead for a given mode.
810 * The hard-coded 1/0.972261=2.853% overhead factor
811 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
812 * 0.453% DSC overhead. This is enough for a 3840 width mode,
813 * which has a DSC overhead of up to ~0.2%, but may not be
814 * enough for a 1024 width mode where this is ~0.8% (on a 4
815 * lane DP link, with 2 DSC slices and 8 bpp color depth).
816 */
817 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
818 }
819
820 static int
small_joiner_ram_size_bits(struct intel_display * display)821 small_joiner_ram_size_bits(struct intel_display *display)
822 {
823 if (DISPLAY_VER(display) >= 13)
824 return 17280 * 8;
825 else if (DISPLAY_VER(display) >= 11)
826 return 7680 * 8;
827 else
828 return 6144 * 8;
829 }
830
intel_dp_dsc_nearest_valid_bpp(struct intel_display * display,u32 bpp,u32 pipe_bpp)831 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
832 {
833 u32 bits_per_pixel = bpp;
834 int i;
835
836 /* Error out if the max bpp is less than smallest allowed valid bpp */
837 if (bits_per_pixel < valid_dsc_bpp[0]) {
838 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
839 bits_per_pixel, valid_dsc_bpp[0]);
840 return 0;
841 }
842
843 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
844 if (DISPLAY_VER(display) >= 13) {
845 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
846
847 /*
848 * According to BSpec, 27 is the max DSC output bpp,
849 * 8 is the min DSC output bpp.
850 * While we can still clamp higher bpp values to 27, saving bandwidth,
851 * if it is required to oompress up to bpp < 8, means we can't do
852 * that and probably means we can't fit the required mode, even with
853 * DSC enabled.
854 */
855 if (bits_per_pixel < 8) {
856 drm_dbg_kms(display->drm,
857 "Unsupported BPP %u, min 8\n",
858 bits_per_pixel);
859 return 0;
860 }
861 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
862 } else {
863 /* Find the nearest match in the array of known BPPs from VESA */
864 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
865 if (bits_per_pixel < valid_dsc_bpp[i + 1])
866 break;
867 }
868 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
869 bits_per_pixel, valid_dsc_bpp[i]);
870
871 bits_per_pixel = valid_dsc_bpp[i];
872 }
873
874 return bits_per_pixel;
875 }
876
bigjoiner_interface_bits(struct intel_display * display)877 static int bigjoiner_interface_bits(struct intel_display *display)
878 {
879 return DISPLAY_VER(display) >= 14 ? 36 : 24;
880 }
881
bigjoiner_bw_max_bpp(struct intel_display * display,u32 mode_clock,int num_joined_pipes)882 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
883 int num_joined_pipes)
884 {
885 u32 max_bpp;
886 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
887 int ppc = 2;
888 int num_big_joiners = num_joined_pipes / 2;
889
890 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
891 intel_dp_mode_to_fec_clock(mode_clock);
892
893 max_bpp *= num_big_joiners;
894
895 return max_bpp;
896
897 }
898
small_joiner_ram_max_bpp(struct intel_display * display,u32 mode_hdisplay,int num_joined_pipes)899 static u32 small_joiner_ram_max_bpp(struct intel_display *display,
900 u32 mode_hdisplay,
901 int num_joined_pipes)
902 {
903 u32 max_bpp;
904
905 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
906 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
907
908 max_bpp *= num_joined_pipes;
909
910 return max_bpp;
911 }
912
ultrajoiner_ram_bits(void)913 static int ultrajoiner_ram_bits(void)
914 {
915 return 4 * 72 * 512;
916 }
917
ultrajoiner_ram_max_bpp(u32 mode_hdisplay)918 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
919 {
920 return ultrajoiner_ram_bits() / mode_hdisplay;
921 }
922
923 static
get_max_compressed_bpp_with_joiner(struct intel_display * display,u32 mode_clock,u32 mode_hdisplay,int num_joined_pipes)924 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
925 u32 mode_clock, u32 mode_hdisplay,
926 int num_joined_pipes)
927 {
928 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
929
930 if (num_joined_pipes > 1)
931 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
932 num_joined_pipes));
933 if (num_joined_pipes == 4)
934 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
935
936 return max_bpp;
937 }
938
intel_dp_dsc_get_max_compressed_bpp(struct intel_display * display,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,int num_joined_pipes,enum intel_output_format output_format,u32 pipe_bpp,u32 timeslots)939 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
940 u32 link_clock, u32 lane_count,
941 u32 mode_clock, u32 mode_hdisplay,
942 int num_joined_pipes,
943 enum intel_output_format output_format,
944 u32 pipe_bpp,
945 u32 timeslots)
946 {
947 u32 bits_per_pixel, joiner_max_bpp;
948
949 /*
950 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
951 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
952 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
953 * for MST -> TimeSlots has to be calculated, based on mode requirements
954 *
955 * Due to FEC overhead, the available bw is reduced to 97.2261%.
956 * To support the given mode:
957 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
958 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
959 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
960 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
961 * (ModeClock / FEC Overhead)
962 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
963 * (ModeClock / FEC Overhead * 8)
964 */
965 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
966 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
967
968 /* Bandwidth required for 420 is half, that of 444 format */
969 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
970 bits_per_pixel *= 2;
971
972 /*
973 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
974 * supported PPS value can be 63.9375 and with the further
975 * mention that for 420, 422 formats, bpp should be programmed double
976 * the target bpp restricting our target bpp to be 31.9375 at max.
977 */
978 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
979 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
980
981 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
982 "total bw %u pixel clock %u\n",
983 bits_per_pixel, timeslots,
984 (link_clock * lane_count * 8),
985 intel_dp_mode_to_fec_clock(mode_clock));
986
987 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
988 mode_hdisplay, num_joined_pipes);
989 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
990
991 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);
992
993 return bits_per_pixel;
994 }
995
intel_dp_dsc_get_slice_count(const struct intel_connector * connector,int mode_clock,int mode_hdisplay,int num_joined_pipes)996 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
997 int mode_clock, int mode_hdisplay,
998 int num_joined_pipes)
999 {
1000 struct intel_display *display = to_intel_display(connector);
1001 u8 min_slice_count, i;
1002 int max_slice_width;
1003
1004 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
1005 min_slice_count = DIV_ROUND_UP(mode_clock,
1006 DP_DSC_MAX_ENC_THROUGHPUT_0);
1007 else
1008 min_slice_count = DIV_ROUND_UP(mode_clock,
1009 DP_DSC_MAX_ENC_THROUGHPUT_1);
1010
1011 /*
1012 * Due to some DSC engine BW limitations, we need to enable second
1013 * slice and VDSC engine, whenever we approach close enough to max CDCLK
1014 */
1015 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1016 min_slice_count = max_t(u8, min_slice_count, 2);
1017
1018 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1019 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1020 drm_dbg_kms(display->drm,
1021 "Unsupported slice width %d by DP DSC Sink device\n",
1022 max_slice_width);
1023 return 0;
1024 }
1025 /* Also take into account max slice width */
1026 min_slice_count = max_t(u8, min_slice_count,
1027 DIV_ROUND_UP(mode_hdisplay,
1028 max_slice_width));
1029
1030 /* Find the closest match to the valid slice count values */
1031 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1032 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1033
1034 /*
1035 * 3 DSC Slices per pipe need 3 DSC engines,
1036 * which is supported only with Ultrajoiner.
1037 */
1038 if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4)
1039 continue;
1040
1041 if (test_slice_count >
1042 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
1043 break;
1044
1045 /*
1046 * Bigjoiner needs small joiner to be enabled.
1047 * So there should be at least 2 dsc slices per pipe,
1048 * whenever bigjoiner is enabled.
1049 */
1050 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1051 continue;
1052
1053 if (mode_hdisplay % test_slice_count)
1054 continue;
1055
1056 if (min_slice_count <= test_slice_count)
1057 return test_slice_count;
1058 }
1059
1060 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1061 min_slice_count);
1062 return 0;
1063 }
1064
source_can_output(struct intel_dp * intel_dp,enum intel_output_format format)1065 static bool source_can_output(struct intel_dp *intel_dp,
1066 enum intel_output_format format)
1067 {
1068 struct intel_display *display = to_intel_display(intel_dp);
1069
1070 switch (format) {
1071 case INTEL_OUTPUT_FORMAT_RGB:
1072 return true;
1073
1074 case INTEL_OUTPUT_FORMAT_YCBCR444:
1075 /*
1076 * No YCbCr output support on gmch platforms.
1077 * Also, ILK doesn't seem capable of DP YCbCr output.
1078 * The displayed image is severly corrupted. SNB+ is fine.
1079 */
1080 return !HAS_GMCH(display) && !display->platform.ironlake;
1081
1082 case INTEL_OUTPUT_FORMAT_YCBCR420:
1083 /* Platform < Gen 11 cannot output YCbCr420 format */
1084 return DISPLAY_VER(display) >= 11;
1085
1086 default:
1087 MISSING_CASE(format);
1088 return false;
1089 }
1090 }
1091
1092 static bool
dfp_can_convert_from_rgb(struct intel_dp * intel_dp,enum intel_output_format sink_format)1093 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1094 enum intel_output_format sink_format)
1095 {
1096 if (!drm_dp_is_branch(intel_dp->dpcd))
1097 return false;
1098
1099 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1100 return intel_dp->dfp.rgb_to_ycbcr;
1101
1102 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1103 return intel_dp->dfp.rgb_to_ycbcr &&
1104 intel_dp->dfp.ycbcr_444_to_420;
1105
1106 return false;
1107 }
1108
1109 static bool
dfp_can_convert_from_ycbcr444(struct intel_dp * intel_dp,enum intel_output_format sink_format)1110 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1111 enum intel_output_format sink_format)
1112 {
1113 if (!drm_dp_is_branch(intel_dp->dpcd))
1114 return false;
1115
1116 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1117 return intel_dp->dfp.ycbcr_444_to_420;
1118
1119 return false;
1120 }
1121
1122 static bool
dfp_can_convert(struct intel_dp * intel_dp,enum intel_output_format output_format,enum intel_output_format sink_format)1123 dfp_can_convert(struct intel_dp *intel_dp,
1124 enum intel_output_format output_format,
1125 enum intel_output_format sink_format)
1126 {
1127 switch (output_format) {
1128 case INTEL_OUTPUT_FORMAT_RGB:
1129 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1130 case INTEL_OUTPUT_FORMAT_YCBCR444:
1131 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1132 default:
1133 MISSING_CASE(output_format);
1134 return false;
1135 }
1136
1137 return false;
1138 }
1139
1140 static enum intel_output_format
intel_dp_output_format(struct intel_connector * connector,enum intel_output_format sink_format)1141 intel_dp_output_format(struct intel_connector *connector,
1142 enum intel_output_format sink_format)
1143 {
1144 struct intel_display *display = to_intel_display(connector);
1145 struct intel_dp *intel_dp = intel_attached_dp(connector);
1146 enum intel_output_format force_dsc_output_format =
1147 intel_dp->force_dsc_output_format;
1148 enum intel_output_format output_format;
1149 if (force_dsc_output_format) {
1150 if (source_can_output(intel_dp, force_dsc_output_format) &&
1151 (!drm_dp_is_branch(intel_dp->dpcd) ||
1152 sink_format != force_dsc_output_format ||
1153 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1154 return force_dsc_output_format;
1155
1156 drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1157 }
1158
1159 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1160 dfp_can_convert_from_rgb(intel_dp, sink_format))
1161 output_format = INTEL_OUTPUT_FORMAT_RGB;
1162
1163 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1164 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1165 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1166
1167 else
1168 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1169
1170 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1171
1172 return output_format;
1173 }
1174
intel_dp_min_bpp(enum intel_output_format output_format)1175 int intel_dp_min_bpp(enum intel_output_format output_format)
1176 {
1177 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1178 return 6 * 3;
1179 else
1180 return 8 * 3;
1181 }
1182
intel_dp_output_bpp(enum intel_output_format output_format,int bpp)1183 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1184 {
1185 /*
1186 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1187 * format of the number of bytes per pixel will be half the number
1188 * of bytes of RGB pixel.
1189 */
1190 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1191 bpp /= 2;
1192
1193 return bpp;
1194 }
1195
1196 static enum intel_output_format
intel_dp_sink_format(struct intel_connector * connector,const struct drm_display_mode * mode)1197 intel_dp_sink_format(struct intel_connector *connector,
1198 const struct drm_display_mode *mode)
1199 {
1200 const struct drm_display_info *info = &connector->base.display_info;
1201
1202 if (drm_mode_is_420_only(info, mode))
1203 return INTEL_OUTPUT_FORMAT_YCBCR420;
1204
1205 return INTEL_OUTPUT_FORMAT_RGB;
1206 }
1207
1208 static int
intel_dp_mode_min_output_bpp(struct intel_connector * connector,const struct drm_display_mode * mode)1209 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1210 const struct drm_display_mode *mode)
1211 {
1212 enum intel_output_format output_format, sink_format;
1213
1214 sink_format = intel_dp_sink_format(connector, mode);
1215
1216 output_format = intel_dp_output_format(connector, sink_format);
1217
1218 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1219 }
1220
intel_dp_hdisplay_bad(struct intel_display * display,int hdisplay)1221 static bool intel_dp_hdisplay_bad(struct intel_display *display,
1222 int hdisplay)
1223 {
1224 /*
1225 * Older platforms don't like hdisplay==4096 with DP.
1226 *
1227 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1228 * and frame counter increment), but we don't get vblank interrupts,
1229 * and the pipe underruns immediately. The link also doesn't seem
1230 * to get trained properly.
1231 *
1232 * On CHV the vblank interrupts don't seem to disappear but
1233 * otherwise the symptoms are similar.
1234 *
1235 * TODO: confirm the behaviour on HSW+
1236 */
1237 return hdisplay == 4096 && !HAS_DDI(display);
1238 }
1239
intel_dp_max_tmds_clock(struct intel_dp * intel_dp)1240 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1241 {
1242 struct intel_connector *connector = intel_dp->attached_connector;
1243 const struct drm_display_info *info = &connector->base.display_info;
1244 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1245
1246 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1247 if (max_tmds_clock && info->max_tmds_clock)
1248 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1249
1250 return max_tmds_clock;
1251 }
1252
1253 static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp * intel_dp,int clock,int bpc,enum intel_output_format sink_format,bool respect_downstream_limits)1254 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1255 int clock, int bpc,
1256 enum intel_output_format sink_format,
1257 bool respect_downstream_limits)
1258 {
1259 int tmds_clock, min_tmds_clock, max_tmds_clock;
1260
1261 if (!respect_downstream_limits)
1262 return MODE_OK;
1263
1264 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1265
1266 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1267 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1268
1269 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1270 return MODE_CLOCK_LOW;
1271
1272 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1273 return MODE_CLOCK_HIGH;
1274
1275 return MODE_OK;
1276 }
1277
1278 static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector * connector,const struct drm_display_mode * mode,int target_clock)1279 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1280 const struct drm_display_mode *mode,
1281 int target_clock)
1282 {
1283 struct intel_dp *intel_dp = intel_attached_dp(connector);
1284 const struct drm_display_info *info = &connector->base.display_info;
1285 enum drm_mode_status status;
1286 enum intel_output_format sink_format;
1287
1288 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1289 if (intel_dp->dfp.pcon_max_frl_bw) {
1290 int target_bw;
1291 int max_frl_bw;
1292 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1293
1294 target_bw = bpp * target_clock;
1295
1296 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1297
1298 /* converting bw from Gbps to Kbps*/
1299 max_frl_bw = max_frl_bw * 1000000;
1300
1301 if (target_bw > max_frl_bw)
1302 return MODE_CLOCK_HIGH;
1303
1304 return MODE_OK;
1305 }
1306
1307 if (intel_dp->dfp.max_dotclock &&
1308 target_clock > intel_dp->dfp.max_dotclock)
1309 return MODE_CLOCK_HIGH;
1310
1311 sink_format = intel_dp_sink_format(connector, mode);
1312
1313 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1314 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1315 8, sink_format, true);
1316
1317 if (status != MODE_OK) {
1318 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1319 !connector->base.ycbcr_420_allowed ||
1320 !drm_mode_is_420_also(info, mode))
1321 return status;
1322 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1323 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1324 8, sink_format, true);
1325 if (status != MODE_OK)
1326 return status;
1327 }
1328
1329 return MODE_OK;
1330 }
1331
1332 static
intel_dp_needs_joiner(struct intel_dp * intel_dp,struct intel_connector * connector,int hdisplay,int clock,int num_joined_pipes)1333 bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1334 struct intel_connector *connector,
1335 int hdisplay, int clock,
1336 int num_joined_pipes)
1337 {
1338 struct intel_display *display = to_intel_display(intel_dp);
1339 int hdisplay_limit;
1340
1341 if (!intel_dp_has_joiner(intel_dp))
1342 return false;
1343
1344 num_joined_pipes /= 2;
1345
1346 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1347
1348 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1349 hdisplay > num_joined_pipes * hdisplay_limit;
1350 }
1351
intel_dp_num_joined_pipes(struct intel_dp * intel_dp,struct intel_connector * connector,int hdisplay,int clock)1352 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1353 struct intel_connector *connector,
1354 int hdisplay, int clock)
1355 {
1356 struct intel_display *display = to_intel_display(intel_dp);
1357
1358 if (connector->force_joined_pipes)
1359 return connector->force_joined_pipes;
1360
1361 if (HAS_ULTRAJOINER(display) &&
1362 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))
1363 return 4;
1364
1365 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&
1366 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))
1367 return 2;
1368
1369 return 1;
1370 }
1371
intel_dp_has_dsc(const struct intel_connector * connector)1372 bool intel_dp_has_dsc(const struct intel_connector *connector)
1373 {
1374 struct intel_display *display = to_intel_display(connector);
1375
1376 if (!HAS_DSC(display))
1377 return false;
1378
1379 if (connector->mst_port && !HAS_DSC_MST(display))
1380 return false;
1381
1382 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1383 connector->panel.vbt.edp.dsc_disable)
1384 return false;
1385
1386 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
1387 return false;
1388
1389 return true;
1390 }
1391
1392 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * _connector,struct drm_display_mode * mode)1393 intel_dp_mode_valid(struct drm_connector *_connector,
1394 struct drm_display_mode *mode)
1395 {
1396 struct intel_display *display = to_intel_display(_connector->dev);
1397 struct intel_connector *connector = to_intel_connector(_connector);
1398 struct intel_dp *intel_dp = intel_attached_dp(connector);
1399 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1400 const struct drm_display_mode *fixed_mode;
1401 int target_clock = mode->clock;
1402 int max_rate, mode_rate, max_lanes, max_link_clock;
1403 int max_dotclk = display->cdclk.max_dotclk_freq;
1404 u16 dsc_max_compressed_bpp = 0;
1405 u8 dsc_slice_count = 0;
1406 enum drm_mode_status status;
1407 bool dsc = false;
1408 int num_joined_pipes;
1409
1410 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1411 if (status != MODE_OK)
1412 return status;
1413
1414 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1415 return MODE_H_ILLEGAL;
1416
1417 if (mode->clock < 10000)
1418 return MODE_CLOCK_LOW;
1419
1420 fixed_mode = intel_panel_fixed_mode(connector, mode);
1421 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1422 status = intel_panel_mode_valid(connector, mode);
1423 if (status != MODE_OK)
1424 return status;
1425
1426 target_clock = fixed_mode->clock;
1427 }
1428
1429 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1430 mode->hdisplay, target_clock);
1431 max_dotclk *= num_joined_pipes;
1432
1433 if (target_clock > max_dotclk)
1434 return MODE_CLOCK_HIGH;
1435
1436 if (intel_dp_hdisplay_bad(display, mode->hdisplay))
1437 return MODE_H_ILLEGAL;
1438
1439 max_link_clock = intel_dp_max_link_rate(intel_dp);
1440 max_lanes = intel_dp_max_lane_count(intel_dp);
1441
1442 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1443
1444 mode_rate = intel_dp_link_required(target_clock,
1445 intel_dp_mode_min_output_bpp(connector, mode));
1446
1447 if (intel_dp_has_dsc(connector)) {
1448 enum intel_output_format sink_format, output_format;
1449 int pipe_bpp;
1450
1451 sink_format = intel_dp_sink_format(connector, mode);
1452 output_format = intel_dp_output_format(connector, sink_format);
1453 /*
1454 * TBD pass the connector BPC,
1455 * for now U8_MAX so that max BPC on that platform would be picked
1456 */
1457 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1458
1459 /*
1460 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1461 * integer value since we support only integer values of bpp.
1462 */
1463 if (intel_dp_is_edp(intel_dp)) {
1464 dsc_max_compressed_bpp =
1465 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1466 dsc_slice_count =
1467 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1468 true);
1469 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1470 dsc_max_compressed_bpp =
1471 intel_dp_dsc_get_max_compressed_bpp(display,
1472 max_link_clock,
1473 max_lanes,
1474 target_clock,
1475 mode->hdisplay,
1476 num_joined_pipes,
1477 output_format,
1478 pipe_bpp, 64);
1479 dsc_slice_count =
1480 intel_dp_dsc_get_slice_count(connector,
1481 target_clock,
1482 mode->hdisplay,
1483 num_joined_pipes);
1484 }
1485
1486 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1487 }
1488
1489 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1490 return MODE_CLOCK_HIGH;
1491
1492 if (mode_rate > max_rate && !dsc)
1493 return MODE_CLOCK_HIGH;
1494
1495 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1496 if (status != MODE_OK)
1497 return status;
1498
1499 return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
1500 }
1501
intel_dp_source_supports_tps3(struct intel_display * display)1502 bool intel_dp_source_supports_tps3(struct intel_display *display)
1503 {
1504 return DISPLAY_VER(display) >= 9 ||
1505 display->platform.broadwell || display->platform.haswell;
1506 }
1507
intel_dp_source_supports_tps4(struct intel_display * display)1508 bool intel_dp_source_supports_tps4(struct intel_display *display)
1509 {
1510 return DISPLAY_VER(display) >= 10;
1511 }
1512
seq_buf_print_array(struct seq_buf * s,const int * array,int nelem)1513 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
1514 {
1515 int i;
1516
1517 for (i = 0; i < nelem; i++)
1518 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]);
1519 }
1520
intel_dp_print_rates(struct intel_dp * intel_dp)1521 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1522 {
1523 struct intel_display *display = to_intel_display(intel_dp);
1524 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */
1525
1526 if (!drm_debug_enabled(DRM_UT_KMS))
1527 return;
1528
1529 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);
1530 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));
1531
1532 seq_buf_clear(&s);
1533 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);
1534 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));
1535
1536 seq_buf_clear(&s);
1537 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);
1538 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
1539 }
1540
forced_link_rate(struct intel_dp * intel_dp)1541 static int forced_link_rate(struct intel_dp *intel_dp)
1542 {
1543 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);
1544
1545 if (len == 0)
1546 return intel_dp_common_rate(intel_dp, 0);
1547
1548 return intel_dp_common_rate(intel_dp, len - 1);
1549 }
1550
1551 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)1552 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1553 {
1554 int len;
1555
1556 if (intel_dp->link.force_rate)
1557 return forced_link_rate(intel_dp);
1558
1559 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
1560
1561 return intel_dp_common_rate(intel_dp, len - 1);
1562 }
1563
1564 static int
intel_dp_min_link_rate(struct intel_dp * intel_dp)1565 intel_dp_min_link_rate(struct intel_dp *intel_dp)
1566 {
1567 if (intel_dp->link.force_rate)
1568 return forced_link_rate(intel_dp);
1569
1570 return intel_dp_common_rate(intel_dp, 0);
1571 }
1572
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)1573 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1574 {
1575 struct intel_display *display = to_intel_display(intel_dp);
1576 int i = intel_dp_rate_index(intel_dp->sink_rates,
1577 intel_dp->num_sink_rates, rate);
1578
1579 if (drm_WARN_ON(display->drm, i < 0))
1580 i = 0;
1581
1582 return i;
1583 }
1584
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)1585 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1586 u8 *link_bw, u8 *rate_select)
1587 {
1588 /* eDP 1.4 rate select method. */
1589 if (intel_dp->use_rate_select) {
1590 *link_bw = 0;
1591 *rate_select =
1592 intel_dp_rate_select(intel_dp, port_clock);
1593 } else {
1594 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1595 *rate_select = 0;
1596 }
1597 }
1598
intel_dp_has_hdmi_sink(struct intel_dp * intel_dp)1599 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1600 {
1601 struct intel_connector *connector = intel_dp->attached_connector;
1602
1603 return connector->base.display_info.is_hdmi;
1604 }
1605
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1606 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1607 const struct intel_crtc_state *pipe_config)
1608 {
1609 struct intel_display *display = to_intel_display(intel_dp);
1610 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1611
1612 if (DISPLAY_VER(display) >= 12)
1613 return true;
1614
1615 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1616 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1617 return true;
1618
1619 return false;
1620 }
1621
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * pipe_config)1622 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1623 const struct intel_connector *connector,
1624 const struct intel_crtc_state *pipe_config)
1625 {
1626 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1627 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1628 }
1629
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * crtc_state)1630 bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1631 const struct intel_connector *connector,
1632 const struct intel_crtc_state *crtc_state)
1633 {
1634 if (!intel_dp_has_dsc(connector))
1635 return false;
1636
1637 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
1638 !intel_dp_supports_fec(intel_dp, connector, crtc_state))
1639 return false;
1640
1641 return intel_dsc_source_support(crtc_state);
1642 }
1643
intel_dp_hdmi_compute_bpc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc,bool respect_downstream_limits)1644 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1645 const struct intel_crtc_state *crtc_state,
1646 int bpc, bool respect_downstream_limits)
1647 {
1648 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1649
1650 /*
1651 * Current bpc could already be below 8bpc due to
1652 * FDI bandwidth constraints or other limits.
1653 * HDMI minimum is 8bpc however.
1654 */
1655 bpc = max(bpc, 8);
1656
1657 /*
1658 * We will never exceed downstream TMDS clock limits while
1659 * attempting deep color. If the user insists on forcing an
1660 * out of spec mode they will have to be satisfied with 8bpc.
1661 */
1662 if (!respect_downstream_limits)
1663 bpc = 8;
1664
1665 for (; bpc >= 8; bpc -= 2) {
1666 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1667 intel_dp_has_hdmi_sink(intel_dp)) &&
1668 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1669 respect_downstream_limits) == MODE_OK)
1670 return bpc;
1671 }
1672
1673 return -EINVAL;
1674 }
1675
intel_dp_max_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool respect_downstream_limits)1676 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1677 const struct intel_crtc_state *crtc_state,
1678 bool respect_downstream_limits)
1679 {
1680 struct intel_display *display = to_intel_display(intel_dp);
1681 struct intel_connector *connector = intel_dp->attached_connector;
1682 int bpp, bpc;
1683
1684 bpc = crtc_state->pipe_bpp / 3;
1685
1686 if (intel_dp->dfp.max_bpc)
1687 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1688
1689 if (intel_dp->dfp.min_tmds_clock) {
1690 int max_hdmi_bpc;
1691
1692 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1693 respect_downstream_limits);
1694 if (max_hdmi_bpc < 0)
1695 return 0;
1696
1697 bpc = min(bpc, max_hdmi_bpc);
1698 }
1699
1700 bpp = bpc * 3;
1701 if (intel_dp_is_edp(intel_dp)) {
1702 /* Get bpp from vbt only for panels that dont have bpp in edid */
1703 if (connector->base.display_info.bpc == 0 &&
1704 connector->panel.vbt.edp.bpp &&
1705 connector->panel.vbt.edp.bpp < bpp) {
1706 drm_dbg_kms(display->drm,
1707 "clamping bpp for eDP panel to BIOS-provided %i\n",
1708 connector->panel.vbt.edp.bpp);
1709 bpp = connector->panel.vbt.edp.bpp;
1710 }
1711 }
1712
1713 return bpp;
1714 }
1715
has_seamless_m_n(struct intel_connector * connector)1716 static bool has_seamless_m_n(struct intel_connector *connector)
1717 {
1718 struct intel_display *display = to_intel_display(connector);
1719
1720 /*
1721 * Seamless M/N reprogramming only implemented
1722 * for BDW+ double buffered M/N registers so far.
1723 */
1724 return HAS_DOUBLE_BUFFERED_M_N(display) &&
1725 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1726 }
1727
intel_dp_mode_clock(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1728 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1729 const struct drm_connector_state *conn_state)
1730 {
1731 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1732 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1733
1734 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1735 if (has_seamless_m_n(connector))
1736 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1737 else
1738 return adjusted_mode->crtc_clock;
1739 }
1740
1741 /* Optimize link config in order: max bpp, min clock, min lanes */
1742 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state,const struct link_config_limits * limits)1743 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1744 struct intel_crtc_state *pipe_config,
1745 const struct drm_connector_state *conn_state,
1746 const struct link_config_limits *limits)
1747 {
1748 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1749 int mode_rate, link_rate, link_avail;
1750
1751 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
1752 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
1753 bpp -= 2 * 3) {
1754 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1755
1756 mode_rate = intel_dp_link_required(clock, link_bpp);
1757
1758 for (i = 0; i < intel_dp->num_common_rates; i++) {
1759 link_rate = intel_dp_common_rate(intel_dp, i);
1760 if (link_rate < limits->min_rate ||
1761 link_rate > limits->max_rate)
1762 continue;
1763
1764 for (lane_count = limits->min_lane_count;
1765 lane_count <= limits->max_lane_count;
1766 lane_count <<= 1) {
1767 link_avail = intel_dp_max_link_data_rate(intel_dp,
1768 link_rate,
1769 lane_count);
1770
1771
1772 if (mode_rate <= link_avail) {
1773 pipe_config->lane_count = lane_count;
1774 pipe_config->pipe_bpp = bpp;
1775 pipe_config->port_clock = link_rate;
1776
1777 return 0;
1778 }
1779 }
1780 }
1781 }
1782
1783 return -EINVAL;
1784 }
1785
intel_dp_dsc_max_src_input_bpc(struct intel_display * display)1786 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1787 {
1788 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1789 if (DISPLAY_VER(display) >= 12)
1790 return 12;
1791 if (DISPLAY_VER(display) == 11)
1792 return 10;
1793
1794 return intel_dp_dsc_min_src_input_bpc();
1795 }
1796
intel_dp_dsc_compute_max_bpp(const struct intel_connector * connector,u8 max_req_bpc)1797 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1798 u8 max_req_bpc)
1799 {
1800 struct intel_display *display = to_intel_display(connector);
1801 int i, num_bpc;
1802 u8 dsc_bpc[3] = {};
1803 int dsc_max_bpc;
1804
1805 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1806
1807 if (!dsc_max_bpc)
1808 return dsc_max_bpc;
1809
1810 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
1811
1812 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1813 dsc_bpc);
1814 for (i = 0; i < num_bpc; i++) {
1815 if (dsc_max_bpc >= dsc_bpc[i])
1816 return dsc_bpc[i] * 3;
1817 }
1818
1819 return 0;
1820 }
1821
intel_dp_source_dsc_version_minor(struct intel_display * display)1822 static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1823 {
1824 return DISPLAY_VER(display) >= 14 ? 2 : 1;
1825 }
1826
intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1827 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1828 {
1829 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1830 DP_DSC_MINOR_SHIFT;
1831 }
1832
intel_dp_get_slice_height(int vactive)1833 static int intel_dp_get_slice_height(int vactive)
1834 {
1835 int slice_height;
1836
1837 /*
1838 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1839 * lines is an optimal slice height, but any size can be used as long as
1840 * vertical active integer multiple and maximum vertical slice count
1841 * requirements are met.
1842 */
1843 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1844 if (vactive % slice_height == 0)
1845 return slice_height;
1846
1847 /*
1848 * Highly unlikely we reach here as most of the resolutions will end up
1849 * finding appropriate slice_height in above loop but returning
1850 * slice_height as 2 here as it should work with all resolutions.
1851 */
1852 return 2;
1853 }
1854
intel_dp_dsc_compute_params(const struct intel_connector * connector,struct intel_crtc_state * crtc_state)1855 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1856 struct intel_crtc_state *crtc_state)
1857 {
1858 struct intel_display *display = to_intel_display(connector);
1859 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1860 int ret;
1861
1862 /*
1863 * RC_MODEL_SIZE is currently a constant across all configurations.
1864 *
1865 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1866 * DP_DSC_RC_BUF_SIZE for this.
1867 */
1868 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1869 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1870
1871 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1872
1873 ret = intel_dsc_compute_params(crtc_state);
1874 if (ret)
1875 return ret;
1876
1877 vdsc_cfg->dsc_version_major =
1878 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1879 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1880 vdsc_cfg->dsc_version_minor =
1881 min(intel_dp_source_dsc_version_minor(display),
1882 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1883 if (vdsc_cfg->convert_rgb)
1884 vdsc_cfg->convert_rgb =
1885 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1886 DP_DSC_RGB;
1887
1888 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1889 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1890 if (!vdsc_cfg->line_buf_depth) {
1891 drm_dbg_kms(display->drm,
1892 "DSC Sink Line Buffer Depth invalid\n");
1893 return -EINVAL;
1894 }
1895
1896 vdsc_cfg->block_pred_enable =
1897 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1898 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1899
1900 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1901 }
1902
intel_dp_dsc_supports_format(const struct intel_connector * connector,enum intel_output_format output_format)1903 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1904 enum intel_output_format output_format)
1905 {
1906 struct intel_display *display = to_intel_display(connector);
1907 u8 sink_dsc_format;
1908
1909 switch (output_format) {
1910 case INTEL_OUTPUT_FORMAT_RGB:
1911 sink_dsc_format = DP_DSC_RGB;
1912 break;
1913 case INTEL_OUTPUT_FORMAT_YCBCR444:
1914 sink_dsc_format = DP_DSC_YCbCr444;
1915 break;
1916 case INTEL_OUTPUT_FORMAT_YCBCR420:
1917 if (min(intel_dp_source_dsc_version_minor(display),
1918 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1919 return false;
1920 sink_dsc_format = DP_DSC_YCbCr420_Native;
1921 break;
1922 default:
1923 return false;
1924 }
1925
1926 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1927 }
1928
is_bw_sufficient_for_dsc_config(u16 compressed_bppx16,u32 link_clock,u32 lane_count,u32 mode_clock,enum intel_output_format output_format,int timeslots)1929 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
1930 u32 lane_count, u32 mode_clock,
1931 enum intel_output_format output_format,
1932 int timeslots)
1933 {
1934 u32 available_bw, required_bw;
1935
1936 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1937 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
1938
1939 return available_bw > required_bw;
1940 }
1941
dsc_compute_link_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits,u16 compressed_bppx16,int timeslots)1942 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1943 struct intel_crtc_state *pipe_config,
1944 struct link_config_limits *limits,
1945 u16 compressed_bppx16,
1946 int timeslots)
1947 {
1948 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1949 int link_rate, lane_count;
1950 int i;
1951
1952 for (i = 0; i < intel_dp->num_common_rates; i++) {
1953 link_rate = intel_dp_common_rate(intel_dp, i);
1954 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1955 continue;
1956
1957 for (lane_count = limits->min_lane_count;
1958 lane_count <= limits->max_lane_count;
1959 lane_count <<= 1) {
1960 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
1961 lane_count, adjusted_mode->clock,
1962 pipe_config->output_format,
1963 timeslots))
1964 continue;
1965
1966 pipe_config->lane_count = lane_count;
1967 pipe_config->port_clock = link_rate;
1968
1969 return 0;
1970 }
1971 }
1972
1973 return -EINVAL;
1974 }
1975
1976 static
intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector * connector,const struct intel_crtc_state * pipe_config,int bpc)1977 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1978 const struct intel_crtc_state *pipe_config,
1979 int bpc)
1980 {
1981 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1982
1983 if (max_bppx16)
1984 return max_bppx16;
1985 /*
1986 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1987 * values as given in spec Table 2-157 DP v2.0
1988 */
1989 switch (pipe_config->output_format) {
1990 case INTEL_OUTPUT_FORMAT_RGB:
1991 case INTEL_OUTPUT_FORMAT_YCBCR444:
1992 return (3 * bpc) << 4;
1993 case INTEL_OUTPUT_FORMAT_YCBCR420:
1994 return (3 * (bpc / 2)) << 4;
1995 default:
1996 MISSING_CASE(pipe_config->output_format);
1997 break;
1998 }
1999
2000 return 0;
2001 }
2002
intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state * pipe_config)2003 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
2004 {
2005 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
2006 switch (pipe_config->output_format) {
2007 case INTEL_OUTPUT_FORMAT_RGB:
2008 case INTEL_OUTPUT_FORMAT_YCBCR444:
2009 return 8;
2010 case INTEL_OUTPUT_FORMAT_YCBCR420:
2011 return 6;
2012 default:
2013 MISSING_CASE(pipe_config->output_format);
2014 break;
2015 }
2016
2017 return 0;
2018 }
2019
intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector * connector,const struct intel_crtc_state * pipe_config,int bpc)2020 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2021 const struct intel_crtc_state *pipe_config,
2022 int bpc)
2023 {
2024 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2025 pipe_config, bpc) >> 4;
2026 }
2027
dsc_src_min_compressed_bpp(void)2028 static int dsc_src_min_compressed_bpp(void)
2029 {
2030 /* Min Compressed bpp supported by source is 8 */
2031 return 8;
2032 }
2033
dsc_src_max_compressed_bpp(struct intel_dp * intel_dp)2034 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2035 {
2036 struct intel_display *display = to_intel_display(intel_dp);
2037
2038 /*
2039 * Forcing DSC and using the platform's max compressed bpp is seen to cause
2040 * underruns. Since DSC isn't needed in these cases, limit the
2041 * max compressed bpp to 18, which is a safe value across platforms with different
2042 * pipe bpps.
2043 */
2044 if (intel_dp->force_dsc_en)
2045 return 18;
2046
2047 /*
2048 * Max Compressed bpp for Gen 13+ is 27bpp.
2049 * For earlier platform is 23bpp. (Bspec:49259).
2050 */
2051 if (DISPLAY_VER(display) < 13)
2052 return 23;
2053 else
2054 return 27;
2055 }
2056
2057 /*
2058 * From a list of valid compressed bpps try different compressed bpp and find a
2059 * suitable link configuration that can support it.
2060 */
2061 static int
icl_dsc_compute_link_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct link_config_limits * limits,int dsc_max_bpp,int dsc_min_bpp,int pipe_bpp,int timeslots)2062 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
2063 struct intel_crtc_state *pipe_config,
2064 struct link_config_limits *limits,
2065 int dsc_max_bpp,
2066 int dsc_min_bpp,
2067 int pipe_bpp,
2068 int timeslots)
2069 {
2070 int i, ret;
2071
2072 /* Compressed BPP should be less than the Input DSC bpp */
2073 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2074
2075 for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) {
2076 if (valid_dsc_bpp[i] < dsc_min_bpp ||
2077 valid_dsc_bpp[i] > dsc_max_bpp)
2078 continue;
2079
2080 ret = dsc_compute_link_config(intel_dp,
2081 pipe_config,
2082 limits,
2083 valid_dsc_bpp[i] << 4,
2084 timeslots);
2085 if (ret == 0) {
2086 pipe_config->dsc.compressed_bpp_x16 =
2087 fxp_q4_from_int(valid_dsc_bpp[i]);
2088 return 0;
2089 }
2090 }
2091
2092 return -EINVAL;
2093 }
2094
2095 /*
2096 * From XE_LPD onwards we supports compression bpps in steps of 1 up to
2097 * uncompressed bpp-1. So we start from max compressed bpp and see if any
2098 * link configuration is able to support that compressed bpp, if not we
2099 * step down and check for lower compressed bpp.
2100 */
2101 static int
xelpd_dsc_compute_link_config(struct intel_dp * intel_dp,const struct intel_connector * connector,struct intel_crtc_state * pipe_config,struct link_config_limits * limits,int dsc_max_bpp,int dsc_min_bpp,int pipe_bpp,int timeslots)2102 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
2103 const struct intel_connector *connector,
2104 struct intel_crtc_state *pipe_config,
2105 struct link_config_limits *limits,
2106 int dsc_max_bpp,
2107 int dsc_min_bpp,
2108 int pipe_bpp,
2109 int timeslots)
2110 {
2111 struct intel_display *display = to_intel_display(intel_dp);
2112 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2113 u16 compressed_bppx16;
2114 u8 bppx16_step;
2115 int ret;
2116
2117 if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1)
2118 bppx16_step = 16;
2119 else
2120 bppx16_step = 16 / bppx16_incr;
2121
2122 /* Compressed BPP should be less than the Input DSC bpp */
2123 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
2124 dsc_min_bpp = dsc_min_bpp << 4;
2125
2126 for (compressed_bppx16 = dsc_max_bpp;
2127 compressed_bppx16 >= dsc_min_bpp;
2128 compressed_bppx16 -= bppx16_step) {
2129 if (intel_dp->force_dsc_fractional_bpp_en &&
2130 !fxp_q4_to_frac(compressed_bppx16))
2131 continue;
2132 ret = dsc_compute_link_config(intel_dp,
2133 pipe_config,
2134 limits,
2135 compressed_bppx16,
2136 timeslots);
2137 if (ret == 0) {
2138 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
2139 if (intel_dp->force_dsc_fractional_bpp_en &&
2140 fxp_q4_to_frac(compressed_bppx16))
2141 drm_dbg_kms(display->drm,
2142 "Forcing DSC fractional bpp\n");
2143
2144 return 0;
2145 }
2146 }
2147 return -EINVAL;
2148 }
2149
dsc_compute_compressed_bpp(struct intel_dp * intel_dp,const struct intel_connector * connector,struct intel_crtc_state * pipe_config,struct link_config_limits * limits,int pipe_bpp,int timeslots)2150 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2151 const struct intel_connector *connector,
2152 struct intel_crtc_state *pipe_config,
2153 struct link_config_limits *limits,
2154 int pipe_bpp,
2155 int timeslots)
2156 {
2157 struct intel_display *display = to_intel_display(intel_dp);
2158 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2159 int dsc_min_bpp;
2160 int dsc_max_bpp;
2161 int dsc_joiner_max_bpp;
2162 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2163
2164 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2165
2166 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,
2167 adjusted_mode->hdisplay,
2168 num_joined_pipes);
2169 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2170
2171 if (DISPLAY_VER(display) >= 13)
2172 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
2173 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2174 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
2175 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
2176 }
2177
intel_dp_dsc_min_src_input_bpc(void)2178 int intel_dp_dsc_min_src_input_bpc(void)
2179 {
2180 /* Min DSC Input BPC for ICL+ is 8 */
2181 return 8;
2182 }
2183
2184 static
is_dsc_pipe_bpp_sufficient(struct link_config_limits * limits,int pipe_bpp)2185 bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
2186 int pipe_bpp)
2187 {
2188 return pipe_bpp >= limits->pipe.min_bpp &&
2189 pipe_bpp <= limits->pipe.max_bpp;
2190 }
2191
2192 static
intel_dp_force_dsc_pipe_bpp(struct intel_dp * intel_dp,struct link_config_limits * limits)2193 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2194 struct link_config_limits *limits)
2195 {
2196 struct intel_display *display = to_intel_display(intel_dp);
2197 int forced_bpp;
2198
2199 if (!intel_dp->force_dsc_bpc)
2200 return 0;
2201
2202 forced_bpp = intel_dp->force_dsc_bpc * 3;
2203
2204 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
2205 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2206 intel_dp->force_dsc_bpc);
2207 return forced_bpp;
2208 }
2209
2210 drm_dbg_kms(display->drm,
2211 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2212 intel_dp->force_dsc_bpc);
2213
2214 return 0;
2215 }
2216
intel_dp_dsc_compute_pipe_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits,int timeslots)2217 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2218 struct intel_crtc_state *pipe_config,
2219 struct drm_connector_state *conn_state,
2220 struct link_config_limits *limits,
2221 int timeslots)
2222 {
2223 const struct intel_connector *connector =
2224 to_intel_connector(conn_state->connector);
2225 int dsc_max_bpp;
2226 int dsc_min_bpp;
2227 u8 dsc_bpc[3] = {};
2228 int forced_bpp, pipe_bpp;
2229 int num_bpc, i, ret;
2230
2231 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2232
2233 if (forced_bpp) {
2234 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2235 limits, forced_bpp, timeslots);
2236 if (ret == 0) {
2237 pipe_config->pipe_bpp = forced_bpp;
2238 return 0;
2239 }
2240 }
2241
2242 dsc_max_bpp = limits->pipe.max_bpp;
2243 dsc_min_bpp = limits->pipe.min_bpp;
2244
2245 /*
2246 * Get the maximum DSC bpc that will be supported by any valid
2247 * link configuration and compressed bpp.
2248 */
2249 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2250 for (i = 0; i < num_bpc; i++) {
2251 pipe_bpp = dsc_bpc[i] * 3;
2252 if (pipe_bpp < dsc_min_bpp)
2253 break;
2254 if (pipe_bpp > dsc_max_bpp)
2255 continue;
2256 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2257 limits, pipe_bpp, timeslots);
2258 if (ret == 0) {
2259 pipe_config->pipe_bpp = pipe_bpp;
2260 return 0;
2261 }
2262 }
2263
2264 return -EINVAL;
2265 }
2266
intel_edp_dsc_compute_pipe_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits)2267 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2268 struct intel_crtc_state *pipe_config,
2269 struct drm_connector_state *conn_state,
2270 struct link_config_limits *limits)
2271 {
2272 struct intel_display *display = to_intel_display(intel_dp);
2273 struct intel_connector *connector =
2274 to_intel_connector(conn_state->connector);
2275 int pipe_bpp, forced_bpp;
2276 int dsc_min_bpp;
2277 int dsc_max_bpp;
2278
2279 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2280
2281 if (forced_bpp) {
2282 pipe_bpp = forced_bpp;
2283 } else {
2284 int max_bpc = limits->pipe.max_bpp / 3;
2285
2286 /* For eDP use max bpp that can be supported with DSC. */
2287 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2288 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
2289 drm_dbg_kms(display->drm,
2290 "Computed BPC is not in DSC BPC limits\n");
2291 return -EINVAL;
2292 }
2293 }
2294 pipe_config->port_clock = limits->max_rate;
2295 pipe_config->lane_count = limits->max_lane_count;
2296
2297 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2298
2299 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
2300
2301 /* Compressed BPP should be less than the Input DSC bpp */
2302 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2303
2304 pipe_config->dsc.compressed_bpp_x16 =
2305 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2306
2307 pipe_config->pipe_bpp = pipe_bpp;
2308
2309 return 0;
2310 }
2311
intel_dp_fec_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)2312 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
2313 struct intel_crtc_state *crtc_state)
2314 {
2315 if (crtc_state->fec_enable)
2316 return;
2317
2318 /*
2319 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2320 * Since, FEC is a bandwidth overhead, continue to not enable it for
2321 * eDP. Until, there is a good reason to do so.
2322 */
2323 if (intel_dp_is_edp(intel_dp))
2324 return;
2325
2326 if (intel_dp_is_uhbr(crtc_state))
2327 return;
2328
2329 crtc_state->fec_enable = true;
2330 }
2331
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,struct link_config_limits * limits,int timeslots,bool compute_pipe_bpp)2332 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2333 struct intel_crtc_state *pipe_config,
2334 struct drm_connector_state *conn_state,
2335 struct link_config_limits *limits,
2336 int timeslots,
2337 bool compute_pipe_bpp)
2338 {
2339 struct intel_display *display = to_intel_display(intel_dp);
2340 const struct intel_connector *connector =
2341 to_intel_connector(conn_state->connector);
2342 const struct drm_display_mode *adjusted_mode =
2343 &pipe_config->hw.adjusted_mode;
2344 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2345 int ret;
2346
2347 intel_dp_fec_compute_config(intel_dp, pipe_config);
2348
2349 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2350 return -EINVAL;
2351
2352 /*
2353 * compute pipe bpp is set to false for DP MST DSC case
2354 * and compressed_bpp is calculated same time once
2355 * vpci timeslots are allocated, because overall bpp
2356 * calculation procedure is bit different for MST case.
2357 */
2358 if (compute_pipe_bpp) {
2359 if (intel_dp_is_edp(intel_dp))
2360 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2361 conn_state, limits);
2362 else
2363 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2364 conn_state, limits, timeslots);
2365 if (ret) {
2366 drm_dbg_kms(display->drm,
2367 "No Valid pipe bpp for given mode ret = %d\n", ret);
2368 return ret;
2369 }
2370 }
2371
2372 /* Calculate Slice count */
2373 if (intel_dp_is_edp(intel_dp)) {
2374 pipe_config->dsc.slice_count =
2375 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2376 true);
2377 if (!pipe_config->dsc.slice_count) {
2378 drm_dbg_kms(display->drm,
2379 "Unsupported Slice Count %d\n",
2380 pipe_config->dsc.slice_count);
2381 return -EINVAL;
2382 }
2383 } else {
2384 u8 dsc_dp_slice_count;
2385
2386 dsc_dp_slice_count =
2387 intel_dp_dsc_get_slice_count(connector,
2388 adjusted_mode->crtc_clock,
2389 adjusted_mode->crtc_hdisplay,
2390 num_joined_pipes);
2391 if (!dsc_dp_slice_count) {
2392 drm_dbg_kms(display->drm,
2393 "Compressed Slice Count not supported\n");
2394 return -EINVAL;
2395 }
2396
2397 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2398 }
2399 /*
2400 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2401 * is greater than the maximum Cdclock and if slice count is even
2402 * then we need to use 2 VDSC instances.
2403 * In case of Ultrajoiner along with 12 slices we need to use 3
2404 * VDSC instances.
2405 */
2406 if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
2407 pipe_config->dsc.slice_count == 12)
2408 pipe_config->dsc.num_streams = 3;
2409 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2410 pipe_config->dsc.num_streams = 2;
2411 else
2412 pipe_config->dsc.num_streams = 1;
2413
2414 ret = intel_dp_dsc_compute_params(connector, pipe_config);
2415 if (ret < 0) {
2416 drm_dbg_kms(display->drm,
2417 "Cannot compute valid DSC parameters for Input Bpp = %d"
2418 "Compressed BPP = " FXP_Q4_FMT "\n",
2419 pipe_config->pipe_bpp,
2420 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2421 return ret;
2422 }
2423
2424 pipe_config->dsc.compression_enable = true;
2425 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2426 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2427 pipe_config->pipe_bpp,
2428 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2429 pipe_config->dsc.slice_count);
2430
2431 return 0;
2432 }
2433
2434 /*
2435 * Calculate the output link min, max bpp values in limits based on the pipe bpp
2436 * range, crtc_state and dsc mode. Return true on success.
2437 */
2438 static bool
intel_dp_compute_config_link_bpp_limits(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * crtc_state,bool dsc,struct link_config_limits * limits)2439 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2440 const struct intel_connector *connector,
2441 const struct intel_crtc_state *crtc_state,
2442 bool dsc,
2443 struct link_config_limits *limits)
2444 {
2445 struct intel_display *display = to_intel_display(intel_dp);
2446 const struct drm_display_mode *adjusted_mode =
2447 &crtc_state->hw.adjusted_mode;
2448 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2449 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2450 int max_link_bpp_x16;
2451
2452 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2453 fxp_q4_from_int(limits->pipe.max_bpp));
2454
2455 if (!dsc) {
2456 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2457
2458 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
2459 return false;
2460
2461 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
2462 } else {
2463 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2464 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2465
2466 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2467 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
2468 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2469 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
2470
2471 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2472 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2473 crtc_state,
2474 limits->pipe.max_bpp / 3);
2475 dsc_max_bpp = dsc_sink_max_bpp ?
2476 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2477
2478 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2479 }
2480
2481 limits->link.max_bpp_x16 = max_link_bpp_x16;
2482
2483 drm_dbg_kms(display->drm,
2484 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2485 encoder->base.base.id, encoder->base.name,
2486 crtc->base.base.id, crtc->base.name,
2487 adjusted_mode->crtc_clock,
2488 str_on_off(dsc),
2489 limits->max_lane_count,
2490 limits->max_rate,
2491 limits->pipe.max_bpp,
2492 FXP_Q4_ARGS(limits->link.max_bpp_x16));
2493
2494 return true;
2495 }
2496
2497 static void
intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp * intel_dp,struct link_config_limits * limits)2498 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp,
2499 struct link_config_limits *limits)
2500 {
2501 struct intel_display *display = to_intel_display(intel_dp);
2502 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc();
2503 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2504
2505 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2506 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2507 }
2508
2509 bool
intel_dp_compute_config_limits(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,bool respect_downstream_limits,bool dsc,struct link_config_limits * limits)2510 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2511 struct intel_crtc_state *crtc_state,
2512 bool respect_downstream_limits,
2513 bool dsc,
2514 struct link_config_limits *limits)
2515 {
2516 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2517
2518 limits->min_rate = intel_dp_min_link_rate(intel_dp);
2519 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2520
2521 /* FIXME 128b/132b SST+DSC support missing */
2522 if (!is_mst && dsc)
2523 limits->max_rate = min(limits->max_rate, 810000);
2524 limits->min_rate = min(limits->min_rate, limits->max_rate);
2525
2526 limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2527 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2528
2529 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2530 if (is_mst) {
2531 /*
2532 * FIXME: If all the streams can't fit into the link with their
2533 * current pipe_bpp we should reduce pipe_bpp across the board
2534 * until things start to fit. Until then we limit to <= 8bpc
2535 * since that's what was hardcoded for all MST streams
2536 * previously. This hack should be removed once we have the
2537 * proper retry logic in place.
2538 */
2539 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
2540 } else {
2541 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2542 respect_downstream_limits);
2543 }
2544
2545 if (dsc)
2546 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits);
2547
2548 if (is_mst || intel_dp->use_max_params) {
2549 /*
2550 * For MST we always configure max link bw - the spec doesn't
2551 * seem to suggest we should do otherwise.
2552 *
2553 * Use the maximum clock and number of lanes the eDP panel
2554 * advertizes being capable of in case the initial fast
2555 * optimal params failed us. The panels are generally
2556 * designed to support only a single clock and lane
2557 * configuration, and typically on older panels these
2558 * values correspond to the native resolution of the panel.
2559 */
2560 limits->min_lane_count = limits->max_lane_count;
2561 limits->min_rate = limits->max_rate;
2562 }
2563
2564 intel_dp_test_compute_config(intel_dp, crtc_state, limits);
2565
2566 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2567 intel_dp->attached_connector,
2568 crtc_state,
2569 dsc,
2570 limits);
2571 }
2572
intel_dp_config_required_rate(const struct intel_crtc_state * crtc_state)2573 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2574 {
2575 const struct drm_display_mode *adjusted_mode =
2576 &crtc_state->hw.adjusted_mode;
2577 int bpp = crtc_state->dsc.compression_enable ?
2578 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2579 crtc_state->pipe_bpp;
2580
2581 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2582 }
2583
intel_dp_joiner_needs_dsc(struct intel_display * display,int num_joined_pipes)2584 bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2585 int num_joined_pipes)
2586 {
2587 /*
2588 * Pipe joiner needs compression up to display 12 due to bandwidth
2589 * limitation. DG2 onwards pipe joiner can be enabled without
2590 * compression.
2591 * Ultrajoiner always needs compression.
2592 */
2593 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2594 num_joined_pipes == 4;
2595 }
2596
2597 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,bool respect_downstream_limits)2598 intel_dp_compute_link_config(struct intel_encoder *encoder,
2599 struct intel_crtc_state *pipe_config,
2600 struct drm_connector_state *conn_state,
2601 bool respect_downstream_limits)
2602 {
2603 struct intel_display *display = to_intel_display(encoder);
2604 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2605 struct intel_connector *connector =
2606 to_intel_connector(conn_state->connector);
2607 const struct drm_display_mode *adjusted_mode =
2608 &pipe_config->hw.adjusted_mode;
2609 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2610 struct link_config_limits limits;
2611 bool dsc_needed, joiner_needs_dsc;
2612 int num_joined_pipes;
2613 int ret = 0;
2614
2615 if (pipe_config->fec_enable &&
2616 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2617 return -EINVAL;
2618
2619 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2620 adjusted_mode->crtc_hdisplay,
2621 adjusted_mode->crtc_clock);
2622 if (num_joined_pipes > 1)
2623 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2624
2625 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2626
2627 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2628 !intel_dp_compute_config_limits(intel_dp, pipe_config,
2629 respect_downstream_limits,
2630 false,
2631 &limits);
2632
2633 if (!dsc_needed) {
2634 /*
2635 * Optimize for slow and wide for everything, because there are some
2636 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2637 */
2638 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2639 conn_state, &limits);
2640 if (!ret && intel_dp_is_uhbr(pipe_config))
2641 ret = intel_dp_mtp_tu_compute_config(intel_dp,
2642 pipe_config,
2643 pipe_config->pipe_bpp,
2644 pipe_config->pipe_bpp,
2645 conn_state,
2646 0, false);
2647 if (ret)
2648 dsc_needed = true;
2649 }
2650
2651 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {
2652 drm_dbg_kms(display->drm, "DSC required but not available\n");
2653 return -EINVAL;
2654 }
2655
2656 if (dsc_needed) {
2657 drm_dbg_kms(display->drm,
2658 "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2659 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2660 str_yes_no(intel_dp->force_dsc_en));
2661
2662 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2663 respect_downstream_limits,
2664 true,
2665 &limits))
2666 return -EINVAL;
2667
2668 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2669 conn_state, &limits, 64, true);
2670 if (ret < 0)
2671 return ret;
2672 }
2673
2674 drm_dbg_kms(display->drm,
2675 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2676 pipe_config->lane_count, pipe_config->port_clock,
2677 pipe_config->pipe_bpp,
2678 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2679 intel_dp_config_required_rate(pipe_config),
2680 intel_dp_max_link_data_rate(intel_dp,
2681 pipe_config->port_clock,
2682 pipe_config->lane_count));
2683
2684 return 0;
2685 }
2686
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2687 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2688 const struct drm_connector_state *conn_state)
2689 {
2690 const struct intel_digital_connector_state *intel_conn_state =
2691 to_intel_digital_connector_state(conn_state);
2692 const struct drm_display_mode *adjusted_mode =
2693 &crtc_state->hw.adjusted_mode;
2694
2695 /*
2696 * Our YCbCr output is always limited range.
2697 * crtc_state->limited_color_range only applies to RGB,
2698 * and it must never be set for YCbCr or we risk setting
2699 * some conflicting bits in TRANSCONF which will mess up
2700 * the colors on the monitor.
2701 */
2702 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2703 return false;
2704
2705 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2706 /*
2707 * See:
2708 * CEA-861-E - 5.1 Default Encoding Parameters
2709 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2710 */
2711 return crtc_state->pipe_bpp != 18 &&
2712 drm_default_rgb_quant_range(adjusted_mode) ==
2713 HDMI_QUANTIZATION_RANGE_LIMITED;
2714 } else {
2715 return intel_conn_state->broadcast_rgb ==
2716 INTEL_BROADCAST_RGB_LIMITED;
2717 }
2718 }
2719
intel_dp_port_has_audio(struct intel_display * display,enum port port)2720 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2721 {
2722 if (display->platform.g4x)
2723 return false;
2724 if (DISPLAY_VER(display) < 12 && port == PORT_A)
2725 return false;
2726
2727 return true;
2728 }
2729
intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)2730 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2731 const struct drm_connector_state *conn_state,
2732 struct drm_dp_vsc_sdp *vsc)
2733 {
2734 struct intel_display *display = to_intel_display(crtc_state);
2735
2736 if (crtc_state->has_panel_replay) {
2737 /*
2738 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2739 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2740 * Encoding/Colorimetry Format indication.
2741 */
2742 vsc->revision = 0x7;
2743 } else {
2744 /*
2745 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2746 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2747 * Colorimetry Format indication.
2748 */
2749 vsc->revision = 0x5;
2750 }
2751
2752 vsc->length = 0x13;
2753
2754 /* DP 1.4a spec, Table 2-120 */
2755 switch (crtc_state->output_format) {
2756 case INTEL_OUTPUT_FORMAT_YCBCR444:
2757 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2758 break;
2759 case INTEL_OUTPUT_FORMAT_YCBCR420:
2760 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2761 break;
2762 case INTEL_OUTPUT_FORMAT_RGB:
2763 default:
2764 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2765 }
2766
2767 switch (conn_state->colorspace) {
2768 case DRM_MODE_COLORIMETRY_BT709_YCC:
2769 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2770 break;
2771 case DRM_MODE_COLORIMETRY_XVYCC_601:
2772 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2773 break;
2774 case DRM_MODE_COLORIMETRY_XVYCC_709:
2775 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2776 break;
2777 case DRM_MODE_COLORIMETRY_SYCC_601:
2778 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2779 break;
2780 case DRM_MODE_COLORIMETRY_OPYCC_601:
2781 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2782 break;
2783 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2784 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2785 break;
2786 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2787 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2788 break;
2789 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2790 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2791 break;
2792 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2793 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2794 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2795 break;
2796 default:
2797 /*
2798 * RGB->YCBCR color conversion uses the BT.709
2799 * color space.
2800 */
2801 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2802 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2803 else
2804 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2805 break;
2806 }
2807
2808 vsc->bpc = crtc_state->pipe_bpp / 3;
2809
2810 /* only RGB pixelformat supports 6 bpc */
2811 drm_WARN_ON(display->drm,
2812 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2813
2814 /* all YCbCr are always limited range */
2815 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2816 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2817 }
2818
intel_dp_compute_as_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)2819 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2820 struct intel_crtc_state *crtc_state)
2821 {
2822 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2823 const struct drm_display_mode *adjusted_mode =
2824 &crtc_state->hw.adjusted_mode;
2825
2826 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2827 return;
2828
2829 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2830
2831 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2832 as_sdp->length = 0x9;
2833 as_sdp->duration_incr_ms = 0;
2834
2835 if (crtc_state->cmrr.enable) {
2836 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2837 as_sdp->vtotal = adjusted_mode->vtotal;
2838 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
2839 as_sdp->target_rr_divider = true;
2840 } else {
2841 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2842 as_sdp->vtotal = adjusted_mode->vtotal;
2843 as_sdp->target_rr = 0;
2844 }
2845 }
2846
intel_dp_compute_vsc_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2847 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2848 struct intel_crtc_state *crtc_state,
2849 const struct drm_connector_state *conn_state)
2850 {
2851 struct drm_dp_vsc_sdp *vsc;
2852
2853 if ((!intel_dp->colorimetry_support ||
2854 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2855 !crtc_state->has_psr)
2856 return;
2857
2858 vsc = &crtc_state->infoframes.vsc;
2859
2860 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2861 vsc->sdp_type = DP_SDP_VSC;
2862
2863 /* Needs colorimetry */
2864 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2865 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2866 vsc);
2867 } else if (crtc_state->has_panel_replay) {
2868 /*
2869 * [Panel Replay without colorimetry info]
2870 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2871 * VSC SDP supporting 3D stereo + Panel Replay.
2872 */
2873 vsc->revision = 0x6;
2874 vsc->length = 0x10;
2875 } else if (crtc_state->has_sel_update) {
2876 /*
2877 * [PSR2 without colorimetry]
2878 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2879 * 3D stereo + PSR/PSR2 + Y-coordinate.
2880 */
2881 vsc->revision = 0x4;
2882 vsc->length = 0xe;
2883 } else {
2884 /*
2885 * [PSR1]
2886 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2887 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2888 * higher).
2889 */
2890 vsc->revision = 0x2;
2891 vsc->length = 0x8;
2892 }
2893 }
2894
2895 static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2896 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2897 struct intel_crtc_state *crtc_state,
2898 const struct drm_connector_state *conn_state)
2899 {
2900 struct intel_display *display = to_intel_display(intel_dp);
2901 int ret;
2902 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2903
2904 if (!conn_state->hdr_output_metadata)
2905 return;
2906
2907 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2908
2909 if (ret) {
2910 drm_dbg_kms(display->drm,
2911 "couldn't set HDR metadata in infoframe\n");
2912 return;
2913 }
2914
2915 crtc_state->infoframes.enable |=
2916 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2917 }
2918
can_enable_drrs(struct intel_connector * connector,const struct intel_crtc_state * pipe_config,const struct drm_display_mode * downclock_mode)2919 static bool can_enable_drrs(struct intel_connector *connector,
2920 const struct intel_crtc_state *pipe_config,
2921 const struct drm_display_mode *downclock_mode)
2922 {
2923 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2924
2925 if (pipe_config->vrr.enable)
2926 return false;
2927
2928 /*
2929 * DRRS and PSR can't be enable together, so giving preference to PSR
2930 * as it allows more power-savings by complete shutting down display,
2931 * so to guarantee this, intel_drrs_compute_config() must be called
2932 * after intel_psr_compute_config().
2933 */
2934 if (pipe_config->has_psr)
2935 return false;
2936
2937 /* FIXME missing FDI M2/N2 etc. */
2938 if (pipe_config->has_pch_encoder)
2939 return false;
2940
2941 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2942 return false;
2943
2944 return downclock_mode &&
2945 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2946 }
2947
2948 static void
intel_dp_drrs_compute_config(struct intel_connector * connector,struct intel_crtc_state * pipe_config,int link_bpp_x16)2949 intel_dp_drrs_compute_config(struct intel_connector *connector,
2950 struct intel_crtc_state *pipe_config,
2951 int link_bpp_x16)
2952 {
2953 struct intel_display *display = to_intel_display(connector);
2954 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2955 const struct drm_display_mode *downclock_mode =
2956 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2957 int pixel_clock;
2958
2959 /*
2960 * FIXME all joined pipes share the same transcoder.
2961 * Need to account for that when updating M/N live.
2962 */
2963 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
2964 pipe_config->update_m_n = true;
2965
2966 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2967 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2968 intel_zero_m_n(&pipe_config->dp_m2_n2);
2969 return;
2970 }
2971
2972 if (display->platform.ironlake || display->platform.sandybridge ||
2973 display->platform.ivybridge)
2974 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2975
2976 pipe_config->has_drrs = true;
2977
2978 pixel_clock = downclock_mode->clock;
2979 if (pipe_config->splitter.enable)
2980 pixel_clock /= pipe_config->splitter.link_count;
2981
2982 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2983 pipe_config->port_clock,
2984 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2985 &pipe_config->dp_m2_n2);
2986
2987 /* FIXME: abstract this better */
2988 if (pipe_config->splitter.enable)
2989 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2990 }
2991
intel_dp_has_audio(struct intel_encoder * encoder,const struct drm_connector_state * conn_state)2992 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2993 const struct drm_connector_state *conn_state)
2994 {
2995 struct intel_display *display = to_intel_display(encoder);
2996 const struct intel_digital_connector_state *intel_conn_state =
2997 to_intel_digital_connector_state(conn_state);
2998 struct intel_connector *connector =
2999 to_intel_connector(conn_state->connector);
3000
3001 if (!intel_dp_port_has_audio(display, encoder->port))
3002 return false;
3003
3004 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
3005 return connector->base.display_info.has_audio;
3006 else
3007 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
3008 }
3009
3010 static int
intel_dp_compute_output_format(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state,bool respect_downstream_limits)3011 intel_dp_compute_output_format(struct intel_encoder *encoder,
3012 struct intel_crtc_state *crtc_state,
3013 struct drm_connector_state *conn_state,
3014 bool respect_downstream_limits)
3015 {
3016 struct intel_display *display = to_intel_display(encoder);
3017 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3018 struct intel_connector *connector = intel_dp->attached_connector;
3019 const struct drm_display_info *info = &connector->base.display_info;
3020 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3021 bool ycbcr_420_only;
3022 int ret;
3023
3024 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
3025
3026 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3027 drm_dbg_kms(display->drm,
3028 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3029 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3030 } else {
3031 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
3032 }
3033
3034 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
3035
3036 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
3037 respect_downstream_limits);
3038 if (ret) {
3039 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3040 !connector->base.ycbcr_420_allowed ||
3041 !drm_mode_is_420_also(info, adjusted_mode))
3042 return ret;
3043
3044 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
3045 crtc_state->output_format = intel_dp_output_format(connector,
3046 crtc_state->sink_format);
3047 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
3048 respect_downstream_limits);
3049 }
3050
3051 return ret;
3052 }
3053
3054 void
intel_dp_audio_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3055 intel_dp_audio_compute_config(struct intel_encoder *encoder,
3056 struct intel_crtc_state *pipe_config,
3057 struct drm_connector_state *conn_state)
3058 {
3059 pipe_config->has_audio =
3060 intel_dp_has_audio(encoder, conn_state) &&
3061 intel_audio_compute_config(encoder, pipe_config, conn_state);
3062
3063 pipe_config->sdp_split_enable = pipe_config->has_audio &&
3064 intel_dp_is_uhbr(pipe_config);
3065 }
3066
intel_dp_queue_modeset_retry_work(struct intel_connector * connector)3067 static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
3068 {
3069 struct drm_i915_private *i915 = to_i915(connector->base.dev);
3070
3071 drm_connector_get(&connector->base);
3072 if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))
3073 drm_connector_put(&connector->base);
3074 }
3075
3076 void
intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3077 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3078 struct intel_encoder *encoder,
3079 const struct intel_crtc_state *crtc_state)
3080 {
3081 struct intel_connector *connector;
3082 struct intel_digital_connector_state *conn_state;
3083 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3084 int i;
3085
3086 if (intel_dp->needs_modeset_retry)
3087 return;
3088
3089 intel_dp->needs_modeset_retry = true;
3090
3091 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3092 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);
3093
3094 return;
3095 }
3096
3097 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3098 if (!conn_state->base.crtc)
3099 continue;
3100
3101 if (connector->mst_port == intel_dp)
3102 intel_dp_queue_modeset_retry_work(connector);
3103 }
3104 }
3105
3106 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3107 intel_dp_compute_config(struct intel_encoder *encoder,
3108 struct intel_crtc_state *pipe_config,
3109 struct drm_connector_state *conn_state)
3110 {
3111 struct intel_display *display = to_intel_display(encoder);
3112 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3113 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3114 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3115 const struct drm_display_mode *fixed_mode;
3116 struct intel_connector *connector = intel_dp->attached_connector;
3117 int ret = 0, link_bpp_x16;
3118
3119 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
3120 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3121 ret = intel_panel_compute_config(connector, adjusted_mode);
3122 if (ret)
3123 return ret;
3124 }
3125
3126 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3127 return -EINVAL;
3128
3129 if (!connector->base.interlace_allowed &&
3130 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3131 return -EINVAL;
3132
3133 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3134 return -EINVAL;
3135
3136 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))
3137 return -EINVAL;
3138
3139 /*
3140 * Try to respect downstream TMDS clock limits first, if
3141 * that fails assume the user might know something we don't.
3142 */
3143 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
3144 if (ret)
3145 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
3146 if (ret)
3147 return ret;
3148
3149 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3150 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3151 ret = intel_panel_fitting(pipe_config, conn_state);
3152 if (ret)
3153 return ret;
3154 }
3155
3156 pipe_config->limited_color_range =
3157 intel_dp_limited_color_range(pipe_config, conn_state);
3158
3159 if (intel_dp_is_uhbr(pipe_config)) {
3160 /* 128b/132b SST also needs this */
3161 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
3162 } else {
3163 pipe_config->enhanced_framing =
3164 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3165 }
3166
3167 if (pipe_config->dsc.compression_enable)
3168 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3169 else
3170 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
3171 pipe_config->pipe_bpp));
3172
3173 if (intel_dp->mso_link_count) {
3174 int n = intel_dp->mso_link_count;
3175 int overlap = intel_dp->mso_pixel_overlap;
3176
3177 pipe_config->splitter.enable = true;
3178 pipe_config->splitter.link_count = n;
3179 pipe_config->splitter.pixel_overlap = overlap;
3180
3181 drm_dbg_kms(display->drm,
3182 "MSO link count %d, pixel overlap %d\n",
3183 n, overlap);
3184
3185 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3186 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3187 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3188 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3189 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3190 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3191 adjusted_mode->crtc_clock /= n;
3192 }
3193
3194 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3195
3196 if (!intel_dp_is_uhbr(pipe_config)) {
3197 intel_link_compute_m_n(link_bpp_x16,
3198 pipe_config->lane_count,
3199 adjusted_mode->crtc_clock,
3200 pipe_config->port_clock,
3201 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3202 &pipe_config->dp_m_n);
3203 }
3204
3205 /* FIXME: abstract this better */
3206 if (pipe_config->splitter.enable)
3207 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3208
3209 intel_vrr_compute_config(pipe_config, conn_state);
3210 intel_dp_compute_as_sdp(intel_dp, pipe_config);
3211 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
3212 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
3213 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3214 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
3215 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
3216
3217 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3218 pipe_config);
3219 }
3220
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count)3221 void intel_dp_set_link_params(struct intel_dp *intel_dp,
3222 int link_rate, int lane_count)
3223 {
3224 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3225 intel_dp->link_trained = false;
3226 intel_dp->needs_modeset_retry = false;
3227 intel_dp->link_rate = link_rate;
3228 intel_dp->lane_count = lane_count;
3229 }
3230
intel_dp_reset_link_params(struct intel_dp * intel_dp)3231 void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3232 {
3233 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3234 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3235 intel_dp->link.mst_probed_lane_count = 0;
3236 intel_dp->link.mst_probed_rate = 0;
3237 intel_dp->link.retrain_disabled = false;
3238 intel_dp->link.seq_train_failures = 0;
3239 }
3240
3241 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3242 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3243 const struct drm_connector_state *conn_state)
3244 {
3245 struct intel_display *display = to_intel_display(crtc_state);
3246 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3247
3248 if (!intel_dp_is_edp(intel_dp))
3249 return;
3250
3251 drm_dbg_kms(display->drm, "\n");
3252
3253 intel_backlight_enable(crtc_state, conn_state);
3254 intel_pps_backlight_on(intel_dp);
3255 }
3256
3257 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)3258 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3259 {
3260 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3261 struct intel_display *display = to_intel_display(intel_dp);
3262
3263 if (!intel_dp_is_edp(intel_dp))
3264 return;
3265
3266 drm_dbg_kms(display->drm, "\n");
3267
3268 intel_pps_backlight_off(intel_dp);
3269 intel_backlight_disable(old_conn_state);
3270 }
3271
downstream_hpd_needs_d0(struct intel_dp * intel_dp)3272 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3273 {
3274 /*
3275 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3276 * be capable of signalling downstream hpd with a long pulse.
3277 * Whether or not that means D3 is safe to use is not clear,
3278 * but let's assume so until proven otherwise.
3279 *
3280 * FIXME should really check all downstream ports...
3281 */
3282 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3283 drm_dp_is_branch(intel_dp->dpcd) &&
3284 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3285 }
3286
3287 static int
write_dsc_decompression_flag(struct drm_dp_aux * aux,u8 flag,bool set)3288 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3289 {
3290 int err;
3291 u8 val;
3292
3293 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3294 if (err < 0)
3295 return err;
3296
3297 if (set)
3298 val |= flag;
3299 else
3300 val &= ~flag;
3301
3302 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3303 }
3304
3305 static void
intel_dp_sink_set_dsc_decompression(struct intel_connector * connector,bool enable)3306 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3307 bool enable)
3308 {
3309 struct intel_display *display = to_intel_display(connector);
3310
3311 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3312 DP_DECOMPRESSION_EN, enable) < 0)
3313 drm_dbg_kms(display->drm,
3314 "Failed to %s sink decompression state\n",
3315 str_enable_disable(enable));
3316 }
3317
3318 static void
intel_dp_sink_set_dsc_passthrough(const struct intel_connector * connector,bool enable)3319 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3320 bool enable)
3321 {
3322 struct intel_display *display = to_intel_display(connector);
3323 struct drm_dp_aux *aux = connector->port ?
3324 connector->port->passthrough_aux : NULL;
3325
3326 if (!aux)
3327 return;
3328
3329 if (write_dsc_decompression_flag(aux,
3330 DP_DSC_PASSTHROUGH_EN, enable) < 0)
3331 drm_dbg_kms(display->drm,
3332 "Failed to %s sink compression passthrough state\n",
3333 str_enable_disable(enable));
3334 }
3335
intel_dp_dsc_aux_ref_count(struct intel_atomic_state * state,const struct intel_connector * connector,bool for_get_ref)3336 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3337 const struct intel_connector *connector,
3338 bool for_get_ref)
3339 {
3340 struct intel_display *display = to_intel_display(state);
3341 struct drm_connector *_connector_iter;
3342 struct drm_connector_state *old_conn_state;
3343 struct drm_connector_state *new_conn_state;
3344 int ref_count = 0;
3345 int i;
3346
3347 /*
3348 * On SST the decompression AUX device won't be shared, each connector
3349 * uses for this its own AUX targeting the sink device.
3350 */
3351 if (!connector->mst_port)
3352 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3353
3354 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3355 old_conn_state, new_conn_state, i) {
3356 const struct intel_connector *
3357 connector_iter = to_intel_connector(_connector_iter);
3358
3359 if (connector_iter->mst_port != connector->mst_port)
3360 continue;
3361
3362 if (!connector_iter->dp.dsc_decompression_enabled)
3363 continue;
3364
3365 drm_WARN_ON(display->drm,
3366 (for_get_ref && !new_conn_state->crtc) ||
3367 (!for_get_ref && !old_conn_state->crtc));
3368
3369 if (connector_iter->dp.dsc_decompression_aux ==
3370 connector->dp.dsc_decompression_aux)
3371 ref_count++;
3372 }
3373
3374 return ref_count;
3375 }
3376
intel_dp_dsc_aux_get_ref(struct intel_atomic_state * state,struct intel_connector * connector)3377 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3378 struct intel_connector *connector)
3379 {
3380 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3381
3382 connector->dp.dsc_decompression_enabled = true;
3383
3384 return ret;
3385 }
3386
intel_dp_dsc_aux_put_ref(struct intel_atomic_state * state,struct intel_connector * connector)3387 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3388 struct intel_connector *connector)
3389 {
3390 connector->dp.dsc_decompression_enabled = false;
3391
3392 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3393 }
3394
3395 /**
3396 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3397 * @state: atomic state
3398 * @connector: connector to enable the decompression for
3399 * @new_crtc_state: new state for the CRTC driving @connector
3400 *
3401 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3402 * register of the appropriate sink/branch device. On SST this is always the
3403 * sink device, whereas on MST based on each device's DSC capabilities it's
3404 * either the last branch device (enabling decompression in it) or both the
3405 * last branch device (enabling passthrough in it) and the sink device
3406 * (enabling decompression in it).
3407 */
intel_dp_sink_enable_decompression(struct intel_atomic_state * state,struct intel_connector * connector,const struct intel_crtc_state * new_crtc_state)3408 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3409 struct intel_connector *connector,
3410 const struct intel_crtc_state *new_crtc_state)
3411 {
3412 struct intel_display *display = to_intel_display(state);
3413
3414 if (!new_crtc_state->dsc.compression_enable)
3415 return;
3416
3417 if (drm_WARN_ON(display->drm,
3418 !connector->dp.dsc_decompression_aux ||
3419 connector->dp.dsc_decompression_enabled))
3420 return;
3421
3422 if (!intel_dp_dsc_aux_get_ref(state, connector))
3423 return;
3424
3425 intel_dp_sink_set_dsc_passthrough(connector, true);
3426 intel_dp_sink_set_dsc_decompression(connector, true);
3427 }
3428
3429 /**
3430 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3431 * @state: atomic state
3432 * @connector: connector to disable the decompression for
3433 * @old_crtc_state: old state for the CRTC driving @connector
3434 *
3435 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3436 * register of the appropriate sink/branch device, corresponding to the
3437 * sequence in intel_dp_sink_enable_decompression().
3438 */
intel_dp_sink_disable_decompression(struct intel_atomic_state * state,struct intel_connector * connector,const struct intel_crtc_state * old_crtc_state)3439 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3440 struct intel_connector *connector,
3441 const struct intel_crtc_state *old_crtc_state)
3442 {
3443 struct intel_display *display = to_intel_display(state);
3444
3445 if (!old_crtc_state->dsc.compression_enable)
3446 return;
3447
3448 if (drm_WARN_ON(display->drm,
3449 !connector->dp.dsc_decompression_aux ||
3450 !connector->dp.dsc_decompression_enabled))
3451 return;
3452
3453 if (!intel_dp_dsc_aux_put_ref(state, connector))
3454 return;
3455
3456 intel_dp_sink_set_dsc_decompression(connector, false);
3457 intel_dp_sink_set_dsc_passthrough(connector, false);
3458 }
3459
3460 static void
intel_dp_init_source_oui(struct intel_dp * intel_dp)3461 intel_dp_init_source_oui(struct intel_dp *intel_dp)
3462 {
3463 struct intel_display *display = to_intel_display(intel_dp);
3464 u8 oui[] = { 0x00, 0xaa, 0x01 };
3465 u8 buf[3] = {};
3466
3467 if (READ_ONCE(intel_dp->oui_valid))
3468 return;
3469
3470 WRITE_ONCE(intel_dp->oui_valid, true);
3471
3472 /*
3473 * During driver init, we want to be careful and avoid changing the source OUI if it's
3474 * already set to what we want, so as to avoid clearing any state by accident
3475 */
3476 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3477 drm_dbg_kms(display->drm, "Failed to read source OUI\n");
3478
3479 if (memcmp(oui, buf, sizeof(oui)) == 0) {
3480 /* Assume the OUI was written now. */
3481 intel_dp->last_oui_write = jiffies;
3482 return;
3483 }
3484
3485 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {
3486 drm_dbg_kms(display->drm, "Failed to write source OUI\n");
3487 WRITE_ONCE(intel_dp->oui_valid, false);
3488 }
3489
3490 intel_dp->last_oui_write = jiffies;
3491 }
3492
intel_dp_invalidate_source_oui(struct intel_dp * intel_dp)3493 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3494 {
3495 WRITE_ONCE(intel_dp->oui_valid, false);
3496 }
3497
intel_dp_wait_source_oui(struct intel_dp * intel_dp)3498 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3499 {
3500 struct intel_display *display = to_intel_display(intel_dp);
3501 struct intel_connector *connector = intel_dp->attached_connector;
3502
3503 drm_dbg_kms(display->drm,
3504 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3505 connector->base.base.id, connector->base.name,
3506 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3507
3508 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3509 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3510 }
3511
3512 /* If the device supports it, try to set the power state appropriately */
intel_dp_set_power(struct intel_dp * intel_dp,u8 mode)3513 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3514 {
3515 struct intel_display *display = to_intel_display(intel_dp);
3516 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3517 int ret, i;
3518
3519 /* Should have a valid DPCD by this point */
3520 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3521 return;
3522
3523 if (mode != DP_SET_POWER_D0) {
3524 if (downstream_hpd_needs_d0(intel_dp))
3525 return;
3526
3527 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3528 } else {
3529 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3530
3531 lspcon_resume(dp_to_dig_port(intel_dp));
3532
3533 /* Write the source OUI as early as possible */
3534 intel_dp_init_source_oui(intel_dp);
3535
3536 /*
3537 * When turning on, we need to retry for 1ms to give the sink
3538 * time to wake up.
3539 */
3540 for (i = 0; i < 3; i++) {
3541 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3542 if (ret == 1)
3543 break;
3544 msleep(1);
3545 }
3546
3547 if (ret == 1 && lspcon->active)
3548 lspcon_wait_pcon_mode(lspcon);
3549 }
3550
3551 if (ret != 1)
3552 drm_dbg_kms(display->drm,
3553 "[ENCODER:%d:%s] Set power to %s failed\n",
3554 encoder->base.base.id, encoder->base.name,
3555 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3556 }
3557
3558 static bool
3559 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3560
3561 /**
3562 * intel_dp_sync_state - sync the encoder state during init/resume
3563 * @encoder: intel encoder to sync
3564 * @crtc_state: state for the CRTC connected to the encoder
3565 *
3566 * Sync any state stored in the encoder wrt. HW state during driver init
3567 * and system resume.
3568 */
intel_dp_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3569 void intel_dp_sync_state(struct intel_encoder *encoder,
3570 const struct intel_crtc_state *crtc_state)
3571 {
3572 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3573 bool dpcd_updated = false;
3574
3575 /*
3576 * Don't clobber DPCD if it's been already read out during output
3577 * setup (eDP) or detect.
3578 */
3579 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3580 intel_dp_get_dpcd(intel_dp);
3581 dpcd_updated = true;
3582 }
3583
3584 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3585
3586 if (crtc_state) {
3587 intel_dp_reset_link_params(intel_dp);
3588 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
3589 intel_dp->link_trained = true;
3590 }
3591 }
3592
intel_dp_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3593 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3594 struct intel_crtc_state *crtc_state)
3595 {
3596 struct intel_display *display = to_intel_display(encoder);
3597 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3598 bool fastset = true;
3599
3600 /*
3601 * If BIOS has set an unsupported or non-standard link rate for some
3602 * reason force an encoder recompute and full modeset.
3603 */
3604 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3605 crtc_state->port_clock) < 0) {
3606 drm_dbg_kms(display->drm,
3607 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3608 encoder->base.base.id, encoder->base.name);
3609 crtc_state->uapi.connectors_changed = true;
3610 fastset = false;
3611 }
3612
3613 /*
3614 * FIXME hack to force full modeset when DSC is being used.
3615 *
3616 * As long as we do not have full state readout and config comparison
3617 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3618 * Remove once we have readout for DSC.
3619 */
3620 if (crtc_state->dsc.compression_enable) {
3621 drm_dbg_kms(display->drm,
3622 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3623 encoder->base.base.id, encoder->base.name);
3624 crtc_state->uapi.mode_changed = true;
3625 fastset = false;
3626 }
3627
3628 if (CAN_PANEL_REPLAY(intel_dp)) {
3629 drm_dbg_kms(display->drm,
3630 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3631 encoder->base.base.id, encoder->base.name);
3632 crtc_state->uapi.mode_changed = true;
3633 fastset = false;
3634 }
3635
3636 return fastset;
3637 }
3638
intel_dp_get_pcon_dsc_cap(struct intel_dp * intel_dp)3639 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3640 {
3641 struct intel_display *display = to_intel_display(intel_dp);
3642
3643 /* Clear the cached register set to avoid using stale values */
3644
3645 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3646
3647 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3648 intel_dp->pcon_dsc_dpcd,
3649 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3650 drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3651 DP_PCON_DSC_ENCODER);
3652
3653 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3654 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3655 }
3656
intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)3657 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3658 {
3659 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3660 int i;
3661
3662 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3663 if (frl_bw_mask & (1 << i))
3664 return bw_gbps[i];
3665 }
3666 return 0;
3667 }
3668
intel_dp_pcon_set_frl_mask(int max_frl)3669 static int intel_dp_pcon_set_frl_mask(int max_frl)
3670 {
3671 switch (max_frl) {
3672 case 48:
3673 return DP_PCON_FRL_BW_MASK_48GBPS;
3674 case 40:
3675 return DP_PCON_FRL_BW_MASK_40GBPS;
3676 case 32:
3677 return DP_PCON_FRL_BW_MASK_32GBPS;
3678 case 24:
3679 return DP_PCON_FRL_BW_MASK_24GBPS;
3680 case 18:
3681 return DP_PCON_FRL_BW_MASK_18GBPS;
3682 case 9:
3683 return DP_PCON_FRL_BW_MASK_9GBPS;
3684 }
3685
3686 return 0;
3687 }
3688
intel_dp_hdmi_sink_max_frl(struct intel_dp * intel_dp)3689 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3690 {
3691 struct intel_connector *connector = intel_dp->attached_connector;
3692 const struct drm_display_info *info = &connector->base.display_info;
3693 int max_frl_rate;
3694 int max_lanes, rate_per_lane;
3695 int max_dsc_lanes, dsc_rate_per_lane;
3696
3697 max_lanes = info->hdmi.max_lanes;
3698 rate_per_lane = info->hdmi.max_frl_rate_per_lane;
3699 max_frl_rate = max_lanes * rate_per_lane;
3700
3701 if (info->hdmi.dsc_cap.v_1p2) {
3702 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
3703 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
3704 if (max_dsc_lanes && dsc_rate_per_lane)
3705 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3706 }
3707
3708 return max_frl_rate;
3709 }
3710
3711 static bool
intel_dp_pcon_is_frl_trained(struct intel_dp * intel_dp,u8 max_frl_bw_mask,u8 * frl_trained_mask)3712 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3713 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3714 {
3715 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3716 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3717 *frl_trained_mask >= max_frl_bw_mask)
3718 return true;
3719
3720 return false;
3721 }
3722
intel_dp_pcon_start_frl_training(struct intel_dp * intel_dp)3723 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3724 {
3725 struct intel_display *display = to_intel_display(intel_dp);
3726 #define TIMEOUT_FRL_READY_MS 500
3727 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3728 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3729 u8 max_frl_bw_mask = 0, frl_trained_mask;
3730 bool is_active;
3731
3732 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3733 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3734
3735 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3736 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3737 max_edid_frl_bw);
3738
3739 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3740
3741 if (max_frl_bw <= 0)
3742 return -EINVAL;
3743
3744 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3745 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3746
3747 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3748 goto frl_trained;
3749
3750 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3751 if (ret < 0)
3752 return ret;
3753 /* Wait for PCON to be FRL Ready */
3754 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3755
3756 if (!is_active)
3757 return -ETIMEDOUT;
3758
3759 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3760 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3761 if (ret < 0)
3762 return ret;
3763 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3764 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3765 if (ret < 0)
3766 return ret;
3767 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3768 if (ret < 0)
3769 return ret;
3770 /*
3771 * Wait for FRL to be completed
3772 * Check if the HDMI Link is up and active.
3773 */
3774 wait_for(is_active =
3775 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3776 TIMEOUT_HDMI_LINK_ACTIVE_MS);
3777
3778 if (!is_active)
3779 return -ETIMEDOUT;
3780
3781 frl_trained:
3782 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3783 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3784 intel_dp->frl.is_trained = true;
3785 drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3786 intel_dp->frl.trained_rate_gbps);
3787
3788 return 0;
3789 }
3790
intel_dp_is_hdmi_2_1_sink(struct intel_dp * intel_dp)3791 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3792 {
3793 if (drm_dp_is_branch(intel_dp->dpcd) &&
3794 intel_dp_has_hdmi_sink(intel_dp) &&
3795 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3796 return true;
3797
3798 return false;
3799 }
3800
3801 static
intel_dp_pcon_set_tmds_mode(struct intel_dp * intel_dp)3802 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3803 {
3804 int ret;
3805 u8 buf = 0;
3806
3807 /* Set PCON source control mode */
3808 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3809
3810 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3811 if (ret < 0)
3812 return ret;
3813
3814 /* Set HDMI LINK ENABLE */
3815 buf |= DP_PCON_ENABLE_HDMI_LINK;
3816 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3817 if (ret < 0)
3818 return ret;
3819
3820 return 0;
3821 }
3822
intel_dp_check_frl_training(struct intel_dp * intel_dp)3823 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3824 {
3825 struct intel_display *display = to_intel_display(intel_dp);
3826
3827 /*
3828 * Always go for FRL training if:
3829 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3830 * -sink is HDMI2.1
3831 */
3832 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3833 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3834 intel_dp->frl.is_trained)
3835 return;
3836
3837 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3838 int ret, mode;
3839
3840 drm_dbg(display->drm,
3841 "Couldn't set FRL mode, continuing with TMDS mode\n");
3842 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3843 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3844
3845 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3846 drm_dbg(display->drm,
3847 "Issue with PCON, cannot set TMDS mode\n");
3848 } else {
3849 drm_dbg(display->drm, "FRL training Completed\n");
3850 }
3851 }
3852
3853 static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state * crtc_state)3854 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3855 {
3856 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3857
3858 return intel_hdmi_dsc_get_slice_height(vactive);
3859 }
3860
3861 static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3862 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3863 const struct intel_crtc_state *crtc_state)
3864 {
3865 struct intel_connector *connector = intel_dp->attached_connector;
3866 const struct drm_display_info *info = &connector->base.display_info;
3867 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;
3868 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;
3869 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3870 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3871
3872 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3873 pcon_max_slice_width,
3874 hdmi_max_slices, hdmi_throughput);
3875 }
3876
3877 static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int num_slices,int slice_width)3878 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3879 const struct intel_crtc_state *crtc_state,
3880 int num_slices, int slice_width)
3881 {
3882 struct intel_connector *connector = intel_dp->attached_connector;
3883 const struct drm_display_info *info = &connector->base.display_info;
3884 int output_format = crtc_state->output_format;
3885 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
3886 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3887 int hdmi_max_chunk_bytes =
3888 info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
3889
3890 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3891 num_slices, output_format, hdmi_all_bpp,
3892 hdmi_max_chunk_bytes);
3893 }
3894
3895 void
intel_dp_pcon_dsc_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3896 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3897 const struct intel_crtc_state *crtc_state)
3898 {
3899 struct intel_display *display = to_intel_display(intel_dp);
3900 struct intel_connector *connector = intel_dp->attached_connector;
3901 const struct drm_display_info *info;
3902 u8 pps_param[6];
3903 int slice_height;
3904 int slice_width;
3905 int num_slices;
3906 int bits_per_pixel;
3907 int ret;
3908 bool hdmi_is_dsc_1_2;
3909
3910 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3911 return;
3912
3913 if (!connector)
3914 return;
3915
3916 info = &connector->base.display_info;
3917
3918 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;
3919
3920 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3921 !hdmi_is_dsc_1_2)
3922 return;
3923
3924 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3925 if (!slice_height)
3926 return;
3927
3928 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3929 if (!num_slices)
3930 return;
3931
3932 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3933 num_slices);
3934
3935 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3936 num_slices, slice_width);
3937 if (!bits_per_pixel)
3938 return;
3939
3940 pps_param[0] = slice_height & 0xFF;
3941 pps_param[1] = slice_height >> 8;
3942 pps_param[2] = slice_width & 0xFF;
3943 pps_param[3] = slice_width >> 8;
3944 pps_param[4] = bits_per_pixel & 0xFF;
3945 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3946
3947 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3948 if (ret < 0)
3949 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
3950 }
3951
intel_dp_configure_protocol_converter(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3952 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3953 const struct intel_crtc_state *crtc_state)
3954 {
3955 struct intel_display *display = to_intel_display(intel_dp);
3956 bool ycbcr444_to_420 = false;
3957 bool rgb_to_ycbcr = false;
3958 u8 tmp;
3959
3960 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3961 return;
3962
3963 if (!drm_dp_is_branch(intel_dp->dpcd))
3964 return;
3965
3966 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3967
3968 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3969 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3970 drm_dbg_kms(display->drm,
3971 "Failed to %s protocol converter HDMI mode\n",
3972 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3973
3974 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3975 switch (crtc_state->output_format) {
3976 case INTEL_OUTPUT_FORMAT_YCBCR420:
3977 break;
3978 case INTEL_OUTPUT_FORMAT_YCBCR444:
3979 ycbcr444_to_420 = true;
3980 break;
3981 case INTEL_OUTPUT_FORMAT_RGB:
3982 rgb_to_ycbcr = true;
3983 ycbcr444_to_420 = true;
3984 break;
3985 default:
3986 MISSING_CASE(crtc_state->output_format);
3987 break;
3988 }
3989 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3990 switch (crtc_state->output_format) {
3991 case INTEL_OUTPUT_FORMAT_YCBCR444:
3992 break;
3993 case INTEL_OUTPUT_FORMAT_RGB:
3994 rgb_to_ycbcr = true;
3995 break;
3996 default:
3997 MISSING_CASE(crtc_state->output_format);
3998 break;
3999 }
4000 }
4001
4002 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4003
4004 if (drm_dp_dpcd_writeb(&intel_dp->aux,
4005 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4006 drm_dbg_kms(display->drm,
4007 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4008 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4009
4010 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4011
4012 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
4013 drm_dbg_kms(display->drm,
4014 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4015 str_enable_disable(tmp));
4016 }
4017
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)4018 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4019 {
4020 u8 dprx = 0;
4021
4022 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4023 &dprx) != 1)
4024 return false;
4025 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4026 }
4027
intel_dp_read_dsc_dpcd(struct drm_dp_aux * aux,u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])4028 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
4029 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
4030 {
4031 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
4032 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
4033 drm_err(aux->drm_dev,
4034 "Failed to read DPCD register 0x%x\n",
4035 DP_DSC_SUPPORT);
4036 return;
4037 }
4038
4039 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
4040 DP_DSC_RECEIVER_CAP_SIZE,
4041 dsc_dpcd);
4042 }
4043
intel_dp_get_dsc_sink_cap(u8 dpcd_rev,struct intel_connector * connector)4044 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
4045 {
4046 struct intel_display *display = to_intel_display(connector);
4047
4048 /*
4049 * Clear the cached register set to avoid using stale values
4050 * for the sinks that do not support DSC.
4051 */
4052 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
4053
4054 /* Clear fec_capable to avoid using stale values */
4055 connector->dp.fec_capability = 0;
4056
4057 if (dpcd_rev < DP_DPCD_REV_14)
4058 return;
4059
4060 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
4061 connector->dp.dsc_dpcd);
4062
4063 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4064 &connector->dp.fec_capability) < 0) {
4065 drm_err(display->drm, "Failed to read FEC DPCD register\n");
4066 return;
4067 }
4068
4069 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4070 connector->dp.fec_capability);
4071 }
4072
intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev,struct intel_connector * connector)4073 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4074 {
4075 if (edp_dpcd_rev < DP_EDP_14)
4076 return;
4077
4078 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
4079 }
4080
4081 static void
intel_dp_detect_dsc_caps(struct intel_dp * intel_dp,struct intel_connector * connector)4082 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4083 {
4084 struct intel_display *display = to_intel_display(intel_dp);
4085
4086 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4087 if (!HAS_DSC(display))
4088 return;
4089
4090 if (intel_dp_is_edp(intel_dp))
4091 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4092 connector);
4093 else
4094 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
4095 connector);
4096 }
4097
intel_edp_mso_mode_fixup(struct intel_connector * connector,struct drm_display_mode * mode)4098 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4099 struct drm_display_mode *mode)
4100 {
4101 struct intel_display *display = to_intel_display(connector);
4102 struct intel_dp *intel_dp = intel_attached_dp(connector);
4103 int n = intel_dp->mso_link_count;
4104 int overlap = intel_dp->mso_pixel_overlap;
4105
4106 if (!mode || !n)
4107 return;
4108
4109 mode->hdisplay = (mode->hdisplay - overlap) * n;
4110 mode->hsync_start = (mode->hsync_start - overlap) * n;
4111 mode->hsync_end = (mode->hsync_end - overlap) * n;
4112 mode->htotal = (mode->htotal - overlap) * n;
4113 mode->clock *= n;
4114
4115 drm_mode_set_name(mode);
4116
4117 drm_dbg_kms(display->drm,
4118 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4119 connector->base.base.id, connector->base.name,
4120 DRM_MODE_ARG(mode));
4121 }
4122
intel_edp_fixup_vbt_bpp(struct intel_encoder * encoder,int pipe_bpp)4123 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4124 {
4125 struct intel_display *display = to_intel_display(encoder);
4126 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4127 struct intel_connector *connector = intel_dp->attached_connector;
4128
4129 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4130 /*
4131 * This is a big fat ugly hack.
4132 *
4133 * Some machines in UEFI boot mode provide us a VBT that has 18
4134 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4135 * unknown we fail to light up. Yet the same BIOS boots up with
4136 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4137 * max, not what it tells us to use.
4138 *
4139 * Note: This will still be broken if the eDP panel is not lit
4140 * up by the BIOS, and thus we can't get the mode at module
4141 * load.
4142 */
4143 drm_dbg_kms(display->drm,
4144 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4145 pipe_bpp, connector->panel.vbt.edp.bpp);
4146 connector->panel.vbt.edp.bpp = pipe_bpp;
4147 }
4148 }
4149
intel_edp_mso_init(struct intel_dp * intel_dp)4150 static void intel_edp_mso_init(struct intel_dp *intel_dp)
4151 {
4152 struct intel_display *display = to_intel_display(intel_dp);
4153 struct intel_connector *connector = intel_dp->attached_connector;
4154 struct drm_display_info *info = &connector->base.display_info;
4155 u8 mso;
4156
4157 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4158 return;
4159
4160 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4161 drm_err(display->drm, "Failed to read MSO cap\n");
4162 return;
4163 }
4164
4165 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4166 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4167 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4168 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4169 mso = 0;
4170 }
4171
4172 if (mso) {
4173 drm_dbg_kms(display->drm,
4174 "Sink MSO %ux%u configuration, pixel overlap %u\n",
4175 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4176 info->mso_pixel_overlap);
4177 if (!HAS_MSO(display)) {
4178 drm_err(display->drm,
4179 "No source MSO support, disabling\n");
4180 mso = 0;
4181 }
4182 }
4183
4184 intel_dp->mso_link_count = mso;
4185 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4186 }
4187
4188 static void
intel_edp_set_sink_rates(struct intel_dp * intel_dp)4189 intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4190 {
4191 intel_dp->num_sink_rates = 0;
4192
4193 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4194 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4195 int i;
4196
4197 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4198 sink_rates, sizeof(sink_rates));
4199
4200 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4201 int val = le16_to_cpu(sink_rates[i]);
4202
4203 if (val == 0)
4204 break;
4205
4206 /* Value read multiplied by 200kHz gives the per-lane
4207 * link rate in kHz. The source rates are, however,
4208 * stored in terms of LS_Clk kHz. The full conversion
4209 * back to symbols is
4210 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4211 */
4212 intel_dp->sink_rates[i] = (val * 200) / 10;
4213 }
4214 intel_dp->num_sink_rates = i;
4215 }
4216
4217 /*
4218 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4219 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4220 */
4221 if (intel_dp->num_sink_rates)
4222 intel_dp->use_rate_select = true;
4223 else
4224 intel_dp_set_sink_rates(intel_dp);
4225 }
4226
4227 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp,struct intel_connector * connector)4228 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4229 {
4230 struct intel_display *display = to_intel_display(intel_dp);
4231
4232 /* this function is meant to be called only once */
4233 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4234
4235 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4236 return false;
4237
4238 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4239 drm_dp_is_branch(intel_dp->dpcd));
4240 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4241
4242 intel_dp->colorimetry_support =
4243 intel_dp_get_colorimetry_status(intel_dp);
4244
4245 /*
4246 * Read the eDP display control registers.
4247 *
4248 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4249 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4250 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4251 * method). The display control registers should read zero if they're
4252 * not supported anyway.
4253 */
4254 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4255 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4256 sizeof(intel_dp->edp_dpcd)) {
4257 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4258 (int)sizeof(intel_dp->edp_dpcd),
4259 intel_dp->edp_dpcd);
4260
4261 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4262 }
4263
4264 /*
4265 * If needed, program our source OUI so we can make various Intel-specific AUX services
4266 * available (such as HDR backlight controls)
4267 */
4268 intel_dp_init_source_oui(intel_dp);
4269
4270 /*
4271 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4272 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4273 */
4274 intel_psr_init_dpcd(intel_dp);
4275
4276 intel_edp_set_sink_rates(intel_dp);
4277 intel_dp_set_max_sink_lane_count(intel_dp);
4278
4279 /* Read the eDP DSC DPCD registers */
4280 intel_dp_detect_dsc_caps(intel_dp, connector);
4281
4282 return true;
4283 }
4284
4285 static bool
intel_dp_has_sink_count(struct intel_dp * intel_dp)4286 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4287 {
4288 if (!intel_dp->attached_connector)
4289 return false;
4290
4291 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4292 intel_dp->dpcd,
4293 &intel_dp->desc);
4294 }
4295
intel_dp_update_sink_caps(struct intel_dp * intel_dp)4296 void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4297 {
4298 intel_dp_set_sink_rates(intel_dp);
4299 intel_dp_set_max_sink_lane_count(intel_dp);
4300 intel_dp_set_common_rates(intel_dp);
4301 }
4302
4303 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)4304 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4305 {
4306 int ret;
4307
4308 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4309 return false;
4310
4311 /*
4312 * Don't clobber cached eDP rates. Also skip re-reading
4313 * the OUI/ID since we know it won't change.
4314 */
4315 if (!intel_dp_is_edp(intel_dp)) {
4316 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4317 drm_dp_is_branch(intel_dp->dpcd));
4318
4319 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4320
4321 intel_dp->colorimetry_support =
4322 intel_dp_get_colorimetry_status(intel_dp);
4323
4324 intel_dp_update_sink_caps(intel_dp);
4325 }
4326
4327 if (intel_dp_has_sink_count(intel_dp)) {
4328 ret = drm_dp_read_sink_count(&intel_dp->aux);
4329 if (ret < 0)
4330 return false;
4331
4332 /*
4333 * Sink count can change between short pulse hpd hence
4334 * a member variable in intel_dp will track any changes
4335 * between short pulse interrupts.
4336 */
4337 intel_dp->sink_count = ret;
4338
4339 /*
4340 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4341 * a dongle is present but no display. Unless we require to know
4342 * if a dongle is present or not, we don't need to update
4343 * downstream port information. So, an early return here saves
4344 * time from performing other operations which are not required.
4345 */
4346 if (!intel_dp->sink_count)
4347 return false;
4348 }
4349
4350 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4351 intel_dp->downstream_ports) == 0;
4352 }
4353
intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)4354 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4355 {
4356 if (mst_mode == DRM_DP_MST)
4357 return "MST";
4358 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4359 return "SST w/ sideband messaging";
4360 else
4361 return "SST";
4362 }
4363
4364 static enum drm_dp_mst_mode
intel_dp_mst_mode_choose(struct intel_dp * intel_dp,enum drm_dp_mst_mode sink_mst_mode)4365 intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4366 enum drm_dp_mst_mode sink_mst_mode)
4367 {
4368 struct intel_display *display = to_intel_display(intel_dp);
4369
4370 if (!display->params.enable_dp_mst)
4371 return DRM_DP_SST;
4372
4373 if (!intel_dp_mst_source_support(intel_dp))
4374 return DRM_DP_SST;
4375
4376 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4377 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4378 return DRM_DP_SST;
4379
4380 return sink_mst_mode;
4381 }
4382
4383 static enum drm_dp_mst_mode
intel_dp_mst_detect(struct intel_dp * intel_dp)4384 intel_dp_mst_detect(struct intel_dp *intel_dp)
4385 {
4386 struct intel_display *display = to_intel_display(intel_dp);
4387 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4388 enum drm_dp_mst_mode sink_mst_mode;
4389 enum drm_dp_mst_mode mst_detect;
4390
4391 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4392
4393 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4394
4395 drm_dbg_kms(display->drm,
4396 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4397 encoder->base.base.id, encoder->base.name,
4398 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4399 intel_dp_mst_mode_str(sink_mst_mode),
4400 str_yes_no(display->params.enable_dp_mst),
4401 intel_dp_mst_mode_str(mst_detect));
4402
4403 return mst_detect;
4404 }
4405
4406 static void
intel_dp_mst_configure(struct intel_dp * intel_dp)4407 intel_dp_mst_configure(struct intel_dp *intel_dp)
4408 {
4409 if (!intel_dp_mst_source_support(intel_dp))
4410 return;
4411
4412 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4413
4414 if (intel_dp->is_mst)
4415 intel_dp_mst_prepare_probe(intel_dp);
4416
4417 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4418
4419 /* Avoid stale info on the next detect cycle. */
4420 intel_dp->mst_detect = DRM_DP_SST;
4421 }
4422
4423 static void
intel_dp_mst_disconnect(struct intel_dp * intel_dp)4424 intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4425 {
4426 struct intel_display *display = to_intel_display(intel_dp);
4427
4428 if (!intel_dp->is_mst)
4429 return;
4430
4431 drm_dbg_kms(display->drm,
4432 "MST device may have disappeared %d vs %d\n",
4433 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4434 intel_dp->is_mst = false;
4435 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4436 }
4437
4438 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * esi)4439 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4440 {
4441 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4442 }
4443
intel_dp_ack_sink_irq_esi(struct intel_dp * intel_dp,u8 esi[4])4444 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4445 {
4446 int retry;
4447
4448 for (retry = 0; retry < 3; retry++) {
4449 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4450 &esi[1], 3) == 3)
4451 return true;
4452 }
4453
4454 return false;
4455 }
4456
4457 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4458 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4459 const struct drm_connector_state *conn_state)
4460 {
4461 /*
4462 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4463 * of Color Encoding Format and Content Color Gamut], in order to
4464 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4465 */
4466 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4467 return true;
4468
4469 switch (conn_state->colorspace) {
4470 case DRM_MODE_COLORIMETRY_SYCC_601:
4471 case DRM_MODE_COLORIMETRY_OPYCC_601:
4472 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4473 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4474 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4475 return true;
4476 default:
4477 break;
4478 }
4479
4480 return false;
4481 }
4482
intel_dp_as_sdp_pack(const struct drm_dp_as_sdp * as_sdp,struct dp_sdp * sdp,size_t size)4483 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4484 struct dp_sdp *sdp, size_t size)
4485 {
4486 size_t length = sizeof(struct dp_sdp);
4487
4488 if (size < length)
4489 return -ENOSPC;
4490
4491 memset(sdp, 0, size);
4492
4493 /* Prepare AS (Adaptive Sync) SDP Header */
4494 sdp->sdp_header.HB0 = 0;
4495 sdp->sdp_header.HB1 = as_sdp->sdp_type;
4496 sdp->sdp_header.HB2 = 0x02;
4497 sdp->sdp_header.HB3 = as_sdp->length;
4498
4499 /* Fill AS (Adaptive Sync) SDP Payload */
4500 sdp->db[0] = as_sdp->mode;
4501 sdp->db[1] = as_sdp->vtotal & 0xFF;
4502 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4503 sdp->db[3] = as_sdp->target_rr & 0xFF;
4504 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4505
4506 if (as_sdp->target_rr_divider)
4507 sdp->db[4] |= 0x20;
4508
4509 return length;
4510 }
4511
4512 static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display * display,const struct hdmi_drm_infoframe * drm_infoframe,struct dp_sdp * sdp,size_t size)4513 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4514 const struct hdmi_drm_infoframe *drm_infoframe,
4515 struct dp_sdp *sdp,
4516 size_t size)
4517 {
4518 size_t length = sizeof(struct dp_sdp);
4519 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4520 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4521 ssize_t len;
4522
4523 if (size < length)
4524 return -ENOSPC;
4525
4526 memset(sdp, 0, size);
4527
4528 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4529 if (len < 0) {
4530 drm_dbg_kms(display->drm,
4531 "buffer size is smaller than hdr metadata infoframe\n");
4532 return -ENOSPC;
4533 }
4534
4535 if (len != infoframe_size) {
4536 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4537 return -ENOSPC;
4538 }
4539
4540 /*
4541 * Set up the infoframe sdp packet for HDR static metadata.
4542 * Prepare VSC Header for SU as per DP 1.4a spec,
4543 * Table 2-100 and Table 2-101
4544 */
4545
4546 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4547 sdp->sdp_header.HB0 = 0;
4548 /*
4549 * Packet Type 80h + Non-audio INFOFRAME Type value
4550 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4551 * - 80h + Non-audio INFOFRAME Type value
4552 * - InfoFrame Type: 0x07
4553 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4554 */
4555 sdp->sdp_header.HB1 = drm_infoframe->type;
4556 /*
4557 * Least Significant Eight Bits of (Data Byte Count – 1)
4558 * infoframe_size - 1
4559 */
4560 sdp->sdp_header.HB2 = 0x1D;
4561 /* INFOFRAME SDP Version Number */
4562 sdp->sdp_header.HB3 = (0x13 << 2);
4563 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4564 sdp->db[0] = drm_infoframe->version;
4565 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4566 sdp->db[1] = drm_infoframe->length;
4567 /*
4568 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4569 * HDMI_INFOFRAME_HEADER_SIZE
4570 */
4571 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4572 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4573 HDMI_DRM_INFOFRAME_SIZE);
4574
4575 /*
4576 * Size of DP infoframe sdp packet for HDR static metadata consists of
4577 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4578 * - Two Data Blocks: 2 bytes
4579 * CTA Header Byte2 (INFOFRAME Version Number)
4580 * CTA Header Byte3 (Length of INFOFRAME)
4581 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4582 *
4583 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4584 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4585 * will pad rest of the size.
4586 */
4587 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4588 }
4589
intel_write_dp_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type)4590 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4591 const struct intel_crtc_state *crtc_state,
4592 unsigned int type)
4593 {
4594 struct intel_display *display = to_intel_display(encoder);
4595 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4596 struct dp_sdp sdp = {};
4597 ssize_t len;
4598
4599 if ((crtc_state->infoframes.enable &
4600 intel_hdmi_infoframe_enable(type)) == 0)
4601 return;
4602
4603 switch (type) {
4604 case DP_SDP_VSC:
4605 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4606 break;
4607 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4608 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4609 &crtc_state->infoframes.drm.drm,
4610 &sdp, sizeof(sdp));
4611 break;
4612 case DP_SDP_ADAPTIVE_SYNC:
4613 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
4614 sizeof(sdp));
4615 break;
4616 default:
4617 MISSING_CASE(type);
4618 return;
4619 }
4620
4621 if (drm_WARN_ON(display->drm, len < 0))
4622 return;
4623
4624 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4625 }
4626
intel_dp_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4627 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4628 bool enable,
4629 const struct intel_crtc_state *crtc_state,
4630 const struct drm_connector_state *conn_state)
4631 {
4632 struct intel_display *display = to_intel_display(encoder);
4633 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4634 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4635 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4636 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4637
4638 if (HAS_AS_SDP(display))
4639 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4640
4641 u32 val = intel_de_read(display, reg) & ~dip_enable;
4642
4643 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4644 if (!enable && HAS_DSC(display))
4645 val &= ~VDIP_ENABLE_PPS;
4646
4647 /*
4648 * This routine disables VSC DIP if the function is called
4649 * to disable SDP or if it does not have PSR
4650 */
4651 if (!enable || !crtc_state->has_psr)
4652 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4653
4654 intel_de_write(display, reg, val);
4655 intel_de_posting_read(display, reg);
4656
4657 if (!enable)
4658 return;
4659
4660 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4661 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4662
4663 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4664 }
4665
4666 static
intel_dp_as_sdp_unpack(struct drm_dp_as_sdp * as_sdp,const void * buffer,size_t size)4667 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4668 const void *buffer, size_t size)
4669 {
4670 const struct dp_sdp *sdp = buffer;
4671
4672 if (size < sizeof(struct dp_sdp))
4673 return -EINVAL;
4674
4675 memset(as_sdp, 0, sizeof(*as_sdp));
4676
4677 if (sdp->sdp_header.HB0 != 0)
4678 return -EINVAL;
4679
4680 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4681 return -EINVAL;
4682
4683 if (sdp->sdp_header.HB2 != 0x02)
4684 return -EINVAL;
4685
4686 if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4687 return -EINVAL;
4688
4689 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4690 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4691 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4692 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4693 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
4694
4695 return 0;
4696 }
4697
intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp * vsc,const void * buffer,size_t size)4698 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4699 const void *buffer, size_t size)
4700 {
4701 const struct dp_sdp *sdp = buffer;
4702
4703 if (size < sizeof(struct dp_sdp))
4704 return -EINVAL;
4705
4706 memset(vsc, 0, sizeof(*vsc));
4707
4708 if (sdp->sdp_header.HB0 != 0)
4709 return -EINVAL;
4710
4711 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4712 return -EINVAL;
4713
4714 vsc->sdp_type = sdp->sdp_header.HB1;
4715 vsc->revision = sdp->sdp_header.HB2;
4716 vsc->length = sdp->sdp_header.HB3;
4717
4718 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4719 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
4720 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
4721 /*
4722 * - HB2 = 0x2, HB3 = 0x8
4723 * VSC SDP supporting 3D stereo + PSR
4724 * - HB2 = 0x4, HB3 = 0xe
4725 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4726 * first scan line of the SU region (applies to eDP v1.4b
4727 * and higher).
4728 * - HB2 = 0x6, HB3 = 0x10
4729 * VSC SDP supporting 3D stereo + Panel Replay.
4730 */
4731 return 0;
4732 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4733 /*
4734 * - HB2 = 0x5, HB3 = 0x13
4735 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4736 * Format.
4737 */
4738 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4739 vsc->colorimetry = sdp->db[16] & 0xf;
4740 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4741
4742 switch (sdp->db[17] & 0x7) {
4743 case 0x0:
4744 vsc->bpc = 6;
4745 break;
4746 case 0x1:
4747 vsc->bpc = 8;
4748 break;
4749 case 0x2:
4750 vsc->bpc = 10;
4751 break;
4752 case 0x3:
4753 vsc->bpc = 12;
4754 break;
4755 case 0x4:
4756 vsc->bpc = 16;
4757 break;
4758 default:
4759 MISSING_CASE(sdp->db[17] & 0x7);
4760 return -EINVAL;
4761 }
4762
4763 vsc->content_type = sdp->db[18] & 0x7;
4764 } else {
4765 return -EINVAL;
4766 }
4767
4768 return 0;
4769 }
4770
4771 static void
intel_read_dp_as_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_as_sdp * as_sdp)4772 intel_read_dp_as_sdp(struct intel_encoder *encoder,
4773 struct intel_crtc_state *crtc_state,
4774 struct drm_dp_as_sdp *as_sdp)
4775 {
4776 struct intel_display *display = to_intel_display(encoder);
4777 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4778 unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4779 struct dp_sdp sdp = {};
4780 int ret;
4781
4782 if ((crtc_state->infoframes.enable &
4783 intel_hdmi_infoframe_enable(type)) == 0)
4784 return;
4785
4786 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4787 sizeof(sdp));
4788
4789 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4790 if (ret)
4791 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
4792 }
4793
4794 static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe * drm_infoframe,const void * buffer,size_t size)4795 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4796 const void *buffer, size_t size)
4797 {
4798 int ret;
4799
4800 const struct dp_sdp *sdp = buffer;
4801
4802 if (size < sizeof(struct dp_sdp))
4803 return -EINVAL;
4804
4805 if (sdp->sdp_header.HB0 != 0)
4806 return -EINVAL;
4807
4808 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4809 return -EINVAL;
4810
4811 /*
4812 * Least Significant Eight Bits of (Data Byte Count – 1)
4813 * 1Dh (i.e., Data Byte Count = 30 bytes).
4814 */
4815 if (sdp->sdp_header.HB2 != 0x1D)
4816 return -EINVAL;
4817
4818 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4819 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4820 return -EINVAL;
4821
4822 /* INFOFRAME SDP Version Number */
4823 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4824 return -EINVAL;
4825
4826 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4827 if (sdp->db[0] != 1)
4828 return -EINVAL;
4829
4830 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4831 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4832 return -EINVAL;
4833
4834 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4835 HDMI_DRM_INFOFRAME_SIZE);
4836
4837 return ret;
4838 }
4839
intel_read_dp_vsc_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)4840 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4841 struct intel_crtc_state *crtc_state,
4842 struct drm_dp_vsc_sdp *vsc)
4843 {
4844 struct intel_display *display = to_intel_display(encoder);
4845 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4846 unsigned int type = DP_SDP_VSC;
4847 struct dp_sdp sdp = {};
4848 int ret;
4849
4850 if ((crtc_state->infoframes.enable &
4851 intel_hdmi_infoframe_enable(type)) == 0)
4852 return;
4853
4854 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4855
4856 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4857
4858 if (ret)
4859 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
4860 }
4861
intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct hdmi_drm_infoframe * drm_infoframe)4862 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4863 struct intel_crtc_state *crtc_state,
4864 struct hdmi_drm_infoframe *drm_infoframe)
4865 {
4866 struct intel_display *display = to_intel_display(encoder);
4867 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4868 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4869 struct dp_sdp sdp = {};
4870 int ret;
4871
4872 if ((crtc_state->infoframes.enable &
4873 intel_hdmi_infoframe_enable(type)) == 0)
4874 return;
4875
4876 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4877 sizeof(sdp));
4878
4879 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4880 sizeof(sdp));
4881
4882 if (ret)
4883 drm_dbg_kms(display->drm,
4884 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4885 }
4886
intel_read_dp_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,unsigned int type)4887 void intel_read_dp_sdp(struct intel_encoder *encoder,
4888 struct intel_crtc_state *crtc_state,
4889 unsigned int type)
4890 {
4891 switch (type) {
4892 case DP_SDP_VSC:
4893 intel_read_dp_vsc_sdp(encoder, crtc_state,
4894 &crtc_state->infoframes.vsc);
4895 break;
4896 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4897 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4898 &crtc_state->infoframes.drm.drm);
4899 break;
4900 case DP_SDP_ADAPTIVE_SYNC:
4901 intel_read_dp_as_sdp(encoder, crtc_state,
4902 &crtc_state->infoframes.as_sdp);
4903 break;
4904 default:
4905 MISSING_CASE(type);
4906 break;
4907 }
4908 }
4909
intel_dp_link_ok(struct intel_dp * intel_dp,u8 link_status[DP_LINK_STATUS_SIZE])4910 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4911 u8 link_status[DP_LINK_STATUS_SIZE])
4912 {
4913 struct intel_display *display = to_intel_display(intel_dp);
4914 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4915 bool uhbr = intel_dp->link_rate >= 1000000;
4916 bool ok;
4917
4918 if (uhbr)
4919 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4920 intel_dp->lane_count);
4921 else
4922 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4923
4924 if (ok)
4925 return true;
4926
4927 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4928 drm_dbg_kms(display->drm,
4929 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4930 encoder->base.base.id, encoder->base.name,
4931 uhbr ? "128b/132b" : "8b/10b");
4932
4933 return false;
4934 }
4935
4936 static void
intel_dp_mst_hpd_irq(struct intel_dp * intel_dp,u8 * esi,u8 * ack)4937 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4938 {
4939 bool handled = false;
4940
4941 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4942
4943 if (esi[1] & DP_CP_IRQ) {
4944 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4945 ack[1] |= DP_CP_IRQ;
4946 }
4947 }
4948
intel_dp_mst_link_status(struct intel_dp * intel_dp)4949 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4950 {
4951 struct intel_display *display = to_intel_display(intel_dp);
4952 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4953 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4954 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4955
4956 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4957 esi_link_status_size) != esi_link_status_size) {
4958 drm_err(display->drm,
4959 "[ENCODER:%d:%s] Failed to read link status\n",
4960 encoder->base.base.id, encoder->base.name);
4961 return false;
4962 }
4963
4964 return intel_dp_link_ok(intel_dp, link_status);
4965 }
4966
4967 /**
4968 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4969 * @intel_dp: Intel DP struct
4970 *
4971 * Read any pending MST interrupts, call MST core to handle these and ack the
4972 * interrupts. Check if the main and AUX link state is ok.
4973 *
4974 * Returns:
4975 * - %true if pending interrupts were serviced (or no interrupts were
4976 * pending) w/o detecting an error condition.
4977 * - %false if an error condition - like AUX failure or a loss of link - is
4978 * detected, or another condition - like a DP tunnel BW state change - needs
4979 * servicing from the hotplug work.
4980 */
4981 static bool
intel_dp_check_mst_status(struct intel_dp * intel_dp)4982 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4983 {
4984 struct intel_display *display = to_intel_display(intel_dp);
4985 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4986 struct intel_encoder *encoder = &dig_port->base;
4987 bool link_ok = true;
4988 bool reprobe_needed = false;
4989
4990 drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0);
4991
4992 for (;;) {
4993 u8 esi[4] = {};
4994 u8 ack[4] = {};
4995
4996 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4997 drm_dbg_kms(display->drm,
4998 "failed to get ESI - device may have failed\n");
4999 link_ok = false;
5000
5001 break;
5002 }
5003
5004 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
5005
5006 if (intel_dp->active_mst_links > 0 && link_ok &&
5007 esi[3] & LINK_STATUS_CHANGED) {
5008 if (!intel_dp_mst_link_status(intel_dp))
5009 link_ok = false;
5010 ack[3] |= LINK_STATUS_CHANGED;
5011 }
5012
5013 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5014
5015 if (esi[3] & DP_TUNNELING_IRQ) {
5016 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5017 &intel_dp->aux))
5018 reprobe_needed = true;
5019 ack[3] |= DP_TUNNELING_IRQ;
5020 }
5021
5022 if (mem_is_zero(ack, sizeof(ack)))
5023 break;
5024
5025 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
5026 drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5027
5028 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5029 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
5030 }
5031
5032 if (!link_ok || intel_dp->link.force_retrain)
5033 intel_encoder_link_check_queue_work(encoder, 0);
5034
5035 return !reprobe_needed;
5036 }
5037
5038 static void
intel_dp_handle_hdmi_link_status_change(struct intel_dp * intel_dp)5039 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
5040 {
5041 bool is_active;
5042 u8 buf = 0;
5043
5044 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
5045 if (intel_dp->frl.is_trained && !is_active) {
5046 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
5047 return;
5048
5049 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
5050 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
5051 return;
5052
5053 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
5054
5055 intel_dp->frl.is_trained = false;
5056
5057 /* Restart FRL training or fall back to TMDS mode */
5058 intel_dp_check_frl_training(intel_dp);
5059 }
5060 }
5061
5062 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)5063 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5064 {
5065 u8 link_status[DP_LINK_STATUS_SIZE];
5066
5067 if (!intel_dp->link_trained)
5068 return false;
5069
5070 /*
5071 * While PSR source HW is enabled, it will control main-link sending
5072 * frames, enabling and disabling it so trying to do a retrain will fail
5073 * as the link would or not be on or it could mix training patterns
5074 * and frame data at the same time causing retrain to fail.
5075 * Also when exiting PSR, HW will retrain the link anyways fixing
5076 * any link status error.
5077 */
5078 if (intel_psr_enabled(intel_dp))
5079 return false;
5080
5081 if (intel_dp->link.force_retrain)
5082 return true;
5083
5084 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5085 link_status) < 0)
5086 return false;
5087
5088 /*
5089 * Validate the cached values of intel_dp->link_rate and
5090 * intel_dp->lane_count before attempting to retrain.
5091 *
5092 * FIXME would be nice to user the crtc state here, but since
5093 * we need to call this from the short HPD handler that seems
5094 * a bit hard.
5095 */
5096 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5097 intel_dp->lane_count))
5098 return false;
5099
5100 if (intel_dp->link.retrain_disabled)
5101 return false;
5102
5103 if (intel_dp->link.seq_train_failures)
5104 return true;
5105
5106 /* Retrain if link not ok */
5107 return !intel_dp_link_ok(intel_dp, link_status) &&
5108 !intel_psr_link_ok(intel_dp);
5109 }
5110
intel_dp_has_connector(struct intel_dp * intel_dp,const struct drm_connector_state * conn_state)5111 bool intel_dp_has_connector(struct intel_dp *intel_dp,
5112 const struct drm_connector_state *conn_state)
5113 {
5114 struct intel_display *display = to_intel_display(intel_dp);
5115 struct intel_encoder *encoder;
5116 enum pipe pipe;
5117
5118 if (!conn_state->best_encoder)
5119 return false;
5120
5121 /* SST */
5122 encoder = &dp_to_dig_port(intel_dp)->base;
5123 if (conn_state->best_encoder == &encoder->base)
5124 return true;
5125
5126 /* MST */
5127 for_each_pipe(display, pipe) {
5128 encoder = &intel_dp->mst_encoders[pipe]->base;
5129 if (conn_state->best_encoder == &encoder->base)
5130 return true;
5131 }
5132
5133 return false;
5134 }
5135
wait_for_connector_hw_done(const struct drm_connector_state * conn_state)5136 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5137 {
5138 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5139 struct intel_display *display = to_intel_display(connector);
5140
5141 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
5142
5143 if (!conn_state->commit)
5144 return;
5145
5146 drm_WARN_ON(display->drm,
5147 !wait_for_completion_timeout(&conn_state->commit->hw_done,
5148 msecs_to_jiffies(5000)));
5149 }
5150
intel_dp_get_active_pipes(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)5151 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5152 struct drm_modeset_acquire_ctx *ctx,
5153 u8 *pipe_mask)
5154 {
5155 struct intel_display *display = to_intel_display(intel_dp);
5156 struct drm_connector_list_iter conn_iter;
5157 struct intel_connector *connector;
5158 int ret = 0;
5159
5160 *pipe_mask = 0;
5161
5162 drm_connector_list_iter_begin(display->drm, &conn_iter);
5163 for_each_intel_connector_iter(connector, &conn_iter) {
5164 struct drm_connector_state *conn_state =
5165 connector->base.state;
5166 struct intel_crtc_state *crtc_state;
5167 struct intel_crtc *crtc;
5168
5169 if (!intel_dp_has_connector(intel_dp, conn_state))
5170 continue;
5171
5172 crtc = to_intel_crtc(conn_state->crtc);
5173 if (!crtc)
5174 continue;
5175
5176 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5177 if (ret)
5178 break;
5179
5180 crtc_state = to_intel_crtc_state(crtc->base.state);
5181
5182 drm_WARN_ON(display->drm,
5183 !intel_crtc_has_dp_encoder(crtc_state));
5184
5185 if (!crtc_state->hw.active)
5186 continue;
5187
5188 wait_for_connector_hw_done(conn_state);
5189
5190 *pipe_mask |= BIT(crtc->pipe);
5191 }
5192 drm_connector_list_iter_end(&conn_iter);
5193
5194 return ret;
5195 }
5196
intel_dp_flush_connector_commits(struct intel_connector * connector)5197 void intel_dp_flush_connector_commits(struct intel_connector *connector)
5198 {
5199 wait_for_connector_hw_done(connector->base.state);
5200 }
5201
intel_dp_is_connected(struct intel_dp * intel_dp)5202 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5203 {
5204 struct intel_connector *connector = intel_dp->attached_connector;
5205
5206 return connector->base.status == connector_status_connected ||
5207 intel_dp->is_mst;
5208 }
5209
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)5210 static int intel_dp_retrain_link(struct intel_encoder *encoder,
5211 struct drm_modeset_acquire_ctx *ctx)
5212 {
5213 struct intel_display *display = to_intel_display(encoder);
5214 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5215 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5216 u8 pipe_mask;
5217 int ret;
5218
5219 if (!intel_dp_is_connected(intel_dp))
5220 return 0;
5221
5222 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
5223 ctx);
5224 if (ret)
5225 return ret;
5226
5227 if (!intel_dp_needs_link_retrain(intel_dp))
5228 return 0;
5229
5230 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5231 if (ret)
5232 return ret;
5233
5234 if (pipe_mask == 0)
5235 return 0;
5236
5237 if (!intel_dp_needs_link_retrain(intel_dp))
5238 return 0;
5239
5240 drm_dbg_kms(display->drm,
5241 "[ENCODER:%d:%s] retraining link (forced %s)\n",
5242 encoder->base.base.id, encoder->base.name,
5243 str_yes_no(intel_dp->link.force_retrain));
5244
5245 ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
5246 if (ret == -EDEADLK)
5247 return ret;
5248
5249 intel_dp->link.force_retrain = false;
5250
5251 if (ret)
5252 drm_dbg_kms(display->drm,
5253 "[ENCODER:%d:%s] link retraining failed: %pe\n",
5254 encoder->base.base.id, encoder->base.name,
5255 ERR_PTR(ret));
5256
5257 return ret;
5258 }
5259
intel_dp_link_check(struct intel_encoder * encoder)5260 void intel_dp_link_check(struct intel_encoder *encoder)
5261 {
5262 struct drm_modeset_acquire_ctx ctx;
5263 int ret;
5264
5265 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5266 ret = intel_dp_retrain_link(encoder, &ctx);
5267 }
5268
intel_dp_check_link_state(struct intel_dp * intel_dp)5269 void intel_dp_check_link_state(struct intel_dp *intel_dp)
5270 {
5271 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5272 struct intel_encoder *encoder = &dig_port->base;
5273
5274 if (!intel_dp_is_connected(intel_dp))
5275 return;
5276
5277 if (!intel_dp_needs_link_retrain(intel_dp))
5278 return;
5279
5280 intel_encoder_link_check_queue_work(encoder, 0);
5281 }
5282
intel_dp_check_device_service_irq(struct intel_dp * intel_dp)5283 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5284 {
5285 struct intel_display *display = to_intel_display(intel_dp);
5286 u8 val;
5287
5288 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5289 return;
5290
5291 if (drm_dp_dpcd_readb(&intel_dp->aux,
5292 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5293 return;
5294
5295 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5296
5297 if (val & DP_AUTOMATED_TEST_REQUEST)
5298 intel_dp_test_request(intel_dp);
5299
5300 if (val & DP_CP_IRQ)
5301 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5302
5303 if (val & DP_SINK_SPECIFIC_IRQ)
5304 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5305 }
5306
intel_dp_check_link_service_irq(struct intel_dp * intel_dp)5307 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5308 {
5309 struct intel_display *display = to_intel_display(intel_dp);
5310 bool reprobe_needed = false;
5311 u8 val;
5312
5313 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5314 return false;
5315
5316 if (drm_dp_dpcd_readb(&intel_dp->aux,
5317 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5318 return false;
5319
5320 if ((val & DP_TUNNELING_IRQ) &&
5321 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5322 &intel_dp->aux))
5323 reprobe_needed = true;
5324
5325 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5326 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5327 return reprobe_needed;
5328
5329 if (val & HDMI_LINK_STATUS_CHANGED)
5330 intel_dp_handle_hdmi_link_status_change(intel_dp);
5331
5332 return reprobe_needed;
5333 }
5334
5335 /*
5336 * According to DP spec
5337 * 5.1.2:
5338 * 1. Read DPCD
5339 * 2. Configure link according to Receiver Capabilities
5340 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5341 * 4. Check link status on receipt of hot-plug interrupt
5342 *
5343 * intel_dp_short_pulse - handles short pulse interrupts
5344 * when full detection is not required.
5345 * Returns %true if short pulse is handled and full detection
5346 * is NOT required and %false otherwise.
5347 */
5348 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)5349 intel_dp_short_pulse(struct intel_dp *intel_dp)
5350 {
5351 u8 old_sink_count = intel_dp->sink_count;
5352 bool reprobe_needed = false;
5353 bool ret;
5354
5355 intel_dp_test_reset(intel_dp);
5356
5357 /*
5358 * Now read the DPCD to see if it's actually running
5359 * If the current value of sink count doesn't match with
5360 * the value that was stored earlier or dpcd read failed
5361 * we need to do full detection
5362 */
5363 ret = intel_dp_get_dpcd(intel_dp);
5364
5365 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5366 /* No need to proceed if we are going to do full detect */
5367 return false;
5368 }
5369
5370 intel_dp_check_device_service_irq(intel_dp);
5371 reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5372
5373 /* Handle CEC interrupts, if any */
5374 drm_dp_cec_irq(&intel_dp->aux);
5375
5376 intel_dp_check_link_state(intel_dp);
5377
5378 intel_psr_short_pulse(intel_dp);
5379
5380 if (intel_dp_test_short_pulse(intel_dp))
5381 reprobe_needed = true;
5382
5383 return !reprobe_needed;
5384 }
5385
5386 /* XXX this is probably wrong for multiple downstream ports */
5387 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)5388 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5389 {
5390 struct intel_display *display = to_intel_display(intel_dp);
5391 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5392 u8 *dpcd = intel_dp->dpcd;
5393 u8 type;
5394
5395 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5396 return connector_status_connected;
5397
5398 lspcon_resume(dig_port);
5399
5400 if (!intel_dp_get_dpcd(intel_dp))
5401 return connector_status_disconnected;
5402
5403 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5404
5405 /* if there's no downstream port, we're done */
5406 if (!drm_dp_is_branch(dpcd))
5407 return connector_status_connected;
5408
5409 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5410 if (intel_dp_has_sink_count(intel_dp) &&
5411 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5412 return intel_dp->sink_count ?
5413 connector_status_connected : connector_status_disconnected;
5414 }
5415
5416 if (intel_dp->mst_detect == DRM_DP_MST)
5417 return connector_status_connected;
5418
5419 /* If no HPD, poke DDC gently */
5420 if (drm_probe_ddc(&intel_dp->aux.ddc))
5421 return connector_status_connected;
5422
5423 /* Well we tried, say unknown for unreliable port types */
5424 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5425 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5426 if (type == DP_DS_PORT_TYPE_VGA ||
5427 type == DP_DS_PORT_TYPE_NON_EDID)
5428 return connector_status_unknown;
5429 } else {
5430 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5431 DP_DWN_STRM_PORT_TYPE_MASK;
5432 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5433 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5434 return connector_status_unknown;
5435 }
5436
5437 /* Anything else is out of spec, warn and ignore */
5438 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5439 return connector_status_disconnected;
5440 }
5441
5442 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)5443 edp_detect(struct intel_dp *intel_dp)
5444 {
5445 return connector_status_connected;
5446 }
5447
intel_digital_port_lock(struct intel_encoder * encoder)5448 void intel_digital_port_lock(struct intel_encoder *encoder)
5449 {
5450 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5451
5452 if (dig_port->lock)
5453 dig_port->lock(dig_port);
5454 }
5455
intel_digital_port_unlock(struct intel_encoder * encoder)5456 void intel_digital_port_unlock(struct intel_encoder *encoder)
5457 {
5458 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5459
5460 if (dig_port->unlock)
5461 dig_port->unlock(dig_port);
5462 }
5463
5464 /*
5465 * intel_digital_port_connected_locked - is the specified port connected?
5466 * @encoder: intel_encoder
5467 *
5468 * In cases where there's a connector physically connected but it can't be used
5469 * by our hardware we also return false, since the rest of the driver should
5470 * pretty much treat the port as disconnected. This is relevant for type-C
5471 * (starting on ICL) where there's ownership involved.
5472 *
5473 * The caller must hold the lock acquired by calling intel_digital_port_lock()
5474 * when calling this function.
5475 *
5476 * Return %true if port is connected, %false otherwise.
5477 */
intel_digital_port_connected_locked(struct intel_encoder * encoder)5478 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5479 {
5480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5481 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5482 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5483 bool is_connected = false;
5484 intel_wakeref_t wakeref;
5485
5486 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5487 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5488
5489 do {
5490 is_connected = dig_port->connected(encoder);
5491 if (is_connected || is_glitch_free)
5492 break;
5493 usleep_range(10, 30);
5494 } while (time_before(jiffies, wait_expires));
5495 }
5496
5497 return is_connected;
5498 }
5499
intel_digital_port_connected(struct intel_encoder * encoder)5500 bool intel_digital_port_connected(struct intel_encoder *encoder)
5501 {
5502 bool ret;
5503
5504 intel_digital_port_lock(encoder);
5505 ret = intel_digital_port_connected_locked(encoder);
5506 intel_digital_port_unlock(encoder);
5507
5508 return ret;
5509 }
5510
5511 static const struct drm_edid *
intel_dp_get_edid(struct intel_dp * intel_dp)5512 intel_dp_get_edid(struct intel_dp *intel_dp)
5513 {
5514 struct intel_connector *connector = intel_dp->attached_connector;
5515 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5516
5517 /* Use panel fixed edid if we have one */
5518 if (fixed_edid) {
5519 /* invalid edid */
5520 if (IS_ERR(fixed_edid))
5521 return NULL;
5522
5523 return drm_edid_dup(fixed_edid);
5524 }
5525
5526 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5527 }
5528
5529 static void
intel_dp_update_dfp(struct intel_dp * intel_dp,const struct drm_edid * drm_edid)5530 intel_dp_update_dfp(struct intel_dp *intel_dp,
5531 const struct drm_edid *drm_edid)
5532 {
5533 struct intel_display *display = to_intel_display(intel_dp);
5534 struct intel_connector *connector = intel_dp->attached_connector;
5535
5536 intel_dp->dfp.max_bpc =
5537 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5538 intel_dp->downstream_ports, drm_edid);
5539
5540 intel_dp->dfp.max_dotclock =
5541 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5542 intel_dp->downstream_ports);
5543
5544 intel_dp->dfp.min_tmds_clock =
5545 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5546 intel_dp->downstream_ports,
5547 drm_edid);
5548 intel_dp->dfp.max_tmds_clock =
5549 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5550 intel_dp->downstream_ports,
5551 drm_edid);
5552
5553 intel_dp->dfp.pcon_max_frl_bw =
5554 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5555 intel_dp->downstream_ports);
5556
5557 drm_dbg_kms(display->drm,
5558 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5559 connector->base.base.id, connector->base.name,
5560 intel_dp->dfp.max_bpc,
5561 intel_dp->dfp.max_dotclock,
5562 intel_dp->dfp.min_tmds_clock,
5563 intel_dp->dfp.max_tmds_clock,
5564 intel_dp->dfp.pcon_max_frl_bw);
5565
5566 intel_dp_get_pcon_dsc_cap(intel_dp);
5567 }
5568
5569 static bool
intel_dp_can_ycbcr420(struct intel_dp * intel_dp)5570 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5571 {
5572 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5573 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5574 return true;
5575
5576 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5577 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5578 return true;
5579
5580 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5581 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5582 return true;
5583
5584 return false;
5585 }
5586
5587 static void
intel_dp_update_420(struct intel_dp * intel_dp)5588 intel_dp_update_420(struct intel_dp *intel_dp)
5589 {
5590 struct intel_display *display = to_intel_display(intel_dp);
5591 struct intel_connector *connector = intel_dp->attached_connector;
5592
5593 intel_dp->dfp.ycbcr420_passthrough =
5594 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5595 intel_dp->downstream_ports);
5596 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5597 intel_dp->dfp.ycbcr_444_to_420 =
5598 dp_to_dig_port(intel_dp)->lspcon.active ||
5599 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5600 intel_dp->downstream_ports);
5601 intel_dp->dfp.rgb_to_ycbcr =
5602 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5603 intel_dp->downstream_ports,
5604 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5605
5606 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5607
5608 drm_dbg_kms(display->drm,
5609 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5610 connector->base.base.id, connector->base.name,
5611 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5612 str_yes_no(connector->base.ycbcr_420_allowed),
5613 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5614 }
5615
5616 static void
intel_dp_set_edid(struct intel_dp * intel_dp)5617 intel_dp_set_edid(struct intel_dp *intel_dp)
5618 {
5619 struct intel_display *display = to_intel_display(intel_dp);
5620 struct intel_connector *connector = intel_dp->attached_connector;
5621 const struct drm_edid *drm_edid;
5622 bool vrr_capable;
5623
5624 intel_dp_unset_edid(intel_dp);
5625 drm_edid = intel_dp_get_edid(intel_dp);
5626 connector->detect_edid = drm_edid;
5627
5628 /* Below we depend on display info having been updated */
5629 drm_edid_connector_update(&connector->base, drm_edid);
5630
5631 vrr_capable = intel_vrr_is_capable(connector);
5632 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5633 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5634 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5635
5636 intel_dp_update_dfp(intel_dp, drm_edid);
5637 intel_dp_update_420(intel_dp);
5638
5639 drm_dp_cec_attach(&intel_dp->aux,
5640 connector->base.display_info.source_physical_address);
5641 }
5642
5643 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)5644 intel_dp_unset_edid(struct intel_dp *intel_dp)
5645 {
5646 struct intel_connector *connector = intel_dp->attached_connector;
5647
5648 drm_dp_cec_unset_edid(&intel_dp->aux);
5649 drm_edid_free(connector->detect_edid);
5650 connector->detect_edid = NULL;
5651
5652 intel_dp->dfp.max_bpc = 0;
5653 intel_dp->dfp.max_dotclock = 0;
5654 intel_dp->dfp.min_tmds_clock = 0;
5655 intel_dp->dfp.max_tmds_clock = 0;
5656
5657 intel_dp->dfp.pcon_max_frl_bw = 0;
5658
5659 intel_dp->dfp.ycbcr_444_to_420 = false;
5660 connector->base.ycbcr_420_allowed = false;
5661
5662 drm_connector_set_vrr_capable_property(&connector->base,
5663 false);
5664 }
5665
5666 static void
intel_dp_detect_sdp_caps(struct intel_dp * intel_dp)5667 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5668 {
5669 struct intel_display *display = to_intel_display(intel_dp);
5670
5671 intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5672 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5673 }
5674
5675 static int
intel_dp_detect(struct drm_connector * _connector,struct drm_modeset_acquire_ctx * ctx,bool force)5676 intel_dp_detect(struct drm_connector *_connector,
5677 struct drm_modeset_acquire_ctx *ctx,
5678 bool force)
5679 {
5680 struct intel_display *display = to_intel_display(_connector->dev);
5681 struct intel_connector *connector = to_intel_connector(_connector);
5682 struct intel_dp *intel_dp = intel_attached_dp(connector);
5683 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5684 struct intel_encoder *encoder = &dig_port->base;
5685 enum drm_connector_status status;
5686 int ret;
5687
5688 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5689 connector->base.base.id, connector->base.name);
5690 drm_WARN_ON(display->drm,
5691 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
5692
5693 if (!intel_display_device_enabled(display))
5694 return connector_status_disconnected;
5695
5696 if (!intel_display_driver_check_access(display))
5697 return connector->base.status;
5698
5699 intel_dp_flush_connector_commits(connector);
5700
5701 intel_pps_vdd_on(intel_dp);
5702
5703 /* Can't disconnect eDP */
5704 if (intel_dp_is_edp(intel_dp))
5705 status = edp_detect(intel_dp);
5706 else if (intel_digital_port_connected(encoder))
5707 status = intel_dp_detect_dpcd(intel_dp);
5708 else
5709 status = connector_status_disconnected;
5710
5711 if (status != connector_status_disconnected &&
5712 !intel_dp_mst_verify_dpcd_state(intel_dp))
5713 /*
5714 * This requires retrying detection for instance to re-enable
5715 * the MST mode that got reset via a long HPD pulse. The retry
5716 * will happen either via the hotplug handler's retry logic,
5717 * ensured by setting the connector here to SST/disconnected,
5718 * or via a userspace connector probing in response to the
5719 * hotplug uevent sent when removing the MST connectors.
5720 */
5721 status = connector_status_disconnected;
5722
5723 if (status == connector_status_disconnected) {
5724 intel_dp_test_reset(intel_dp);
5725 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
5726 intel_dp->psr.sink_panel_replay_support = false;
5727 intel_dp->psr.sink_panel_replay_su_support = false;
5728
5729 intel_dp_mst_disconnect(intel_dp);
5730
5731 intel_dp_tunnel_disconnect(intel_dp);
5732
5733 goto out_unset_edid;
5734 }
5735
5736 intel_dp_init_source_oui(intel_dp);
5737
5738 ret = intel_dp_tunnel_detect(intel_dp, ctx);
5739 if (ret == -EDEADLK) {
5740 status = ret;
5741
5742 goto out_vdd_off;
5743 }
5744
5745 if (ret == 1)
5746 connector->base.epoch_counter++;
5747
5748 if (!intel_dp_is_edp(intel_dp))
5749 intel_psr_init_dpcd(intel_dp);
5750
5751 intel_dp_detect_dsc_caps(intel_dp, connector);
5752
5753 intel_dp_detect_sdp_caps(intel_dp);
5754
5755 if (intel_dp->reset_link_params) {
5756 intel_dp_reset_link_params(intel_dp);
5757 intel_dp->reset_link_params = false;
5758 }
5759
5760 intel_dp_mst_configure(intel_dp);
5761
5762 intel_dp_print_rates(intel_dp);
5763
5764 if (intel_dp->is_mst) {
5765 /*
5766 * If we are in MST mode then this connector
5767 * won't appear connected or have anything
5768 * with EDID on it
5769 */
5770 status = connector_status_disconnected;
5771 goto out_unset_edid;
5772 }
5773
5774 /*
5775 * Some external monitors do not signal loss of link synchronization
5776 * with an IRQ_HPD, so force a link status check.
5777 *
5778 * TODO: this probably became redundant, so remove it: the link state
5779 * is rechecked/recovered now after modesets, where the loss of
5780 * synchronization tends to occur.
5781 */
5782 if (!intel_dp_is_edp(intel_dp))
5783 intel_dp_check_link_state(intel_dp);
5784
5785 /*
5786 * Clearing NACK and defer counts to get their exact values
5787 * while reading EDID which are required by Compliance tests
5788 * 4.2.2.4 and 4.2.2.5
5789 */
5790 intel_dp->aux.i2c_nack_count = 0;
5791 intel_dp->aux.i2c_defer_count = 0;
5792
5793 intel_dp_set_edid(intel_dp);
5794 if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5795 status = connector_status_connected;
5796
5797 intel_dp_check_device_service_irq(intel_dp);
5798
5799 out_unset_edid:
5800 if (status != connector_status_connected && !intel_dp->is_mst)
5801 intel_dp_unset_edid(intel_dp);
5802
5803 if (!intel_dp_is_edp(intel_dp))
5804 drm_dp_set_subconnector_property(&connector->base,
5805 status,
5806 intel_dp->dpcd,
5807 intel_dp->downstream_ports);
5808 out_vdd_off:
5809 intel_pps_vdd_off(intel_dp);
5810
5811 return status;
5812 }
5813
5814 static void
intel_dp_force(struct drm_connector * connector)5815 intel_dp_force(struct drm_connector *connector)
5816 {
5817 struct intel_display *display = to_intel_display(connector->dev);
5818 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5819
5820 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5821 connector->base.id, connector->name);
5822
5823 if (!intel_display_driver_check_access(display))
5824 return;
5825
5826 intel_dp_unset_edid(intel_dp);
5827
5828 if (connector->status != connector_status_connected)
5829 return;
5830
5831 intel_dp_set_edid(intel_dp);
5832 }
5833
intel_dp_get_modes(struct drm_connector * _connector)5834 static int intel_dp_get_modes(struct drm_connector *_connector)
5835 {
5836 struct intel_display *display = to_intel_display(_connector->dev);
5837 struct intel_connector *connector = to_intel_connector(_connector);
5838 struct intel_dp *intel_dp = intel_attached_dp(connector);
5839 int num_modes;
5840
5841 /* drm_edid_connector_update() done in ->detect() or ->force() */
5842 num_modes = drm_edid_connector_add_modes(&connector->base);
5843
5844 /* Also add fixed mode, which may or may not be present in EDID */
5845 if (intel_dp_is_edp(intel_dp))
5846 num_modes += intel_panel_get_modes(connector);
5847
5848 if (num_modes)
5849 return num_modes;
5850
5851 if (!connector->detect_edid) {
5852 struct drm_display_mode *mode;
5853
5854 mode = drm_dp_downstream_mode(display->drm,
5855 intel_dp->dpcd,
5856 intel_dp->downstream_ports);
5857 if (mode) {
5858 drm_mode_probed_add(&connector->base, mode);
5859 num_modes++;
5860 }
5861 }
5862
5863 return num_modes;
5864 }
5865
5866 static int
intel_dp_connector_register(struct drm_connector * connector)5867 intel_dp_connector_register(struct drm_connector *connector)
5868 {
5869 struct intel_display *display = to_intel_display(connector->dev);
5870 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5871 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5872 struct intel_lspcon *lspcon = &dig_port->lspcon;
5873 int ret;
5874
5875 ret = intel_connector_register(connector);
5876 if (ret)
5877 return ret;
5878
5879 drm_dbg_kms(display->drm, "registering %s bus for %s\n",
5880 intel_dp->aux.name, connector->kdev->kobj.name);
5881
5882 intel_dp->aux.dev = connector->kdev;
5883 ret = drm_dp_aux_register(&intel_dp->aux);
5884 if (!ret)
5885 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5886
5887 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5888 return ret;
5889
5890 /*
5891 * ToDo: Clean this up to handle lspcon init and resume more
5892 * efficiently and streamlined.
5893 */
5894 if (lspcon_init(dig_port)) {
5895 lspcon_detect_hdr_capability(lspcon);
5896 if (lspcon->hdr_supported)
5897 drm_connector_attach_hdr_output_metadata_property(connector);
5898 }
5899
5900 return ret;
5901 }
5902
5903 static void
intel_dp_connector_unregister(struct drm_connector * connector)5904 intel_dp_connector_unregister(struct drm_connector *connector)
5905 {
5906 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5907
5908 drm_dp_cec_unregister_connector(&intel_dp->aux);
5909 drm_dp_aux_unregister(&intel_dp->aux);
5910 intel_connector_unregister(connector);
5911 }
5912
intel_dp_connector_sync_state(struct intel_connector * connector,const struct intel_crtc_state * crtc_state)5913 void intel_dp_connector_sync_state(struct intel_connector *connector,
5914 const struct intel_crtc_state *crtc_state)
5915 {
5916 struct intel_display *display = to_intel_display(connector);
5917
5918 if (crtc_state && crtc_state->dsc.compression_enable) {
5919 drm_WARN_ON(display->drm,
5920 !connector->dp.dsc_decompression_aux);
5921 connector->dp.dsc_decompression_enabled = true;
5922 } else {
5923 connector->dp.dsc_decompression_enabled = false;
5924 }
5925 }
5926
intel_dp_encoder_flush_work(struct drm_encoder * _encoder)5927 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
5928 {
5929 struct intel_encoder *encoder = to_intel_encoder(_encoder);
5930 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5931 struct intel_dp *intel_dp = &dig_port->dp;
5932
5933 intel_encoder_link_check_flush_work(encoder);
5934
5935 intel_dp_mst_encoder_cleanup(dig_port);
5936
5937 intel_dp_tunnel_destroy(intel_dp);
5938
5939 intel_pps_vdd_off_sync(intel_dp);
5940
5941 /*
5942 * Ensure power off delay is respected on module remove, so that we can
5943 * reduce delays at driver probe. See pps_init_timestamps().
5944 */
5945 intel_pps_wait_power_cycle(intel_dp);
5946
5947 intel_dp_aux_fini(intel_dp);
5948 }
5949
intel_dp_encoder_suspend(struct intel_encoder * encoder)5950 void intel_dp_encoder_suspend(struct intel_encoder *encoder)
5951 {
5952 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5953
5954 intel_pps_vdd_off_sync(intel_dp);
5955
5956 intel_dp_tunnel_suspend(intel_dp);
5957 }
5958
intel_dp_encoder_shutdown(struct intel_encoder * encoder)5959 void intel_dp_encoder_shutdown(struct intel_encoder *encoder)
5960 {
5961 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5962
5963 intel_pps_wait_power_cycle(intel_dp);
5964 }
5965
intel_modeset_tile_group(struct intel_atomic_state * state,int tile_group_id)5966 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5967 int tile_group_id)
5968 {
5969 struct intel_display *display = to_intel_display(state);
5970 struct drm_connector_list_iter conn_iter;
5971 struct drm_connector *connector;
5972 int ret = 0;
5973
5974 drm_connector_list_iter_begin(display->drm, &conn_iter);
5975 drm_for_each_connector_iter(connector, &conn_iter) {
5976 struct drm_connector_state *conn_state;
5977 struct intel_crtc_state *crtc_state;
5978 struct intel_crtc *crtc;
5979
5980 if (!connector->has_tile ||
5981 connector->tile_group->id != tile_group_id)
5982 continue;
5983
5984 conn_state = drm_atomic_get_connector_state(&state->base,
5985 connector);
5986 if (IS_ERR(conn_state)) {
5987 ret = PTR_ERR(conn_state);
5988 break;
5989 }
5990
5991 crtc = to_intel_crtc(conn_state->crtc);
5992
5993 if (!crtc)
5994 continue;
5995
5996 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5997 crtc_state->uapi.mode_changed = true;
5998
5999 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6000 if (ret)
6001 break;
6002 }
6003 drm_connector_list_iter_end(&conn_iter);
6004
6005 return ret;
6006 }
6007
intel_modeset_affected_transcoders(struct intel_atomic_state * state,u8 transcoders)6008 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6009 {
6010 struct intel_display *display = to_intel_display(state);
6011 struct intel_crtc *crtc;
6012
6013 if (transcoders == 0)
6014 return 0;
6015
6016 for_each_intel_crtc(display->drm, crtc) {
6017 struct intel_crtc_state *crtc_state;
6018 int ret;
6019
6020 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6021 if (IS_ERR(crtc_state))
6022 return PTR_ERR(crtc_state);
6023
6024 if (!crtc_state->hw.enable)
6025 continue;
6026
6027 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6028 continue;
6029
6030 crtc_state->uapi.mode_changed = true;
6031
6032 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6033 if (ret)
6034 return ret;
6035
6036 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6037 if (ret)
6038 return ret;
6039
6040 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6041 }
6042
6043 drm_WARN_ON(display->drm, transcoders != 0);
6044
6045 return 0;
6046 }
6047
intel_modeset_synced_crtcs(struct intel_atomic_state * state,struct drm_connector * connector)6048 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6049 struct drm_connector *connector)
6050 {
6051 const struct drm_connector_state *old_conn_state =
6052 drm_atomic_get_old_connector_state(&state->base, connector);
6053 const struct intel_crtc_state *old_crtc_state;
6054 struct intel_crtc *crtc;
6055 u8 transcoders;
6056
6057 crtc = to_intel_crtc(old_conn_state->crtc);
6058 if (!crtc)
6059 return 0;
6060
6061 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6062
6063 if (!old_crtc_state->hw.active)
6064 return 0;
6065
6066 transcoders = old_crtc_state->sync_mode_slaves_mask;
6067 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6068 transcoders |= BIT(old_crtc_state->master_transcoder);
6069
6070 return intel_modeset_affected_transcoders(state,
6071 transcoders);
6072 }
6073
intel_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * _state)6074 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6075 struct drm_atomic_state *_state)
6076 {
6077 struct intel_display *display = to_intel_display(conn->dev);
6078 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6079 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6080 struct intel_connector *intel_conn = to_intel_connector(conn);
6081 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6082 int ret;
6083
6084 ret = intel_digital_connector_atomic_check(conn, &state->base);
6085 if (ret)
6086 return ret;
6087
6088 if (intel_dp_mst_source_support(intel_dp)) {
6089 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
6090 if (ret)
6091 return ret;
6092 }
6093
6094 if (!intel_connector_needs_modeset(state, conn))
6095 return 0;
6096
6097 ret = intel_dp_tunnel_atomic_check_state(state,
6098 intel_dp,
6099 intel_conn);
6100 if (ret)
6101 return ret;
6102
6103 /*
6104 * We don't enable port sync on BDW due to missing w/as and
6105 * due to not having adjusted the modeset sequence appropriately.
6106 */
6107 if (DISPLAY_VER(display) < 9)
6108 return 0;
6109
6110 if (conn->has_tile) {
6111 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6112 if (ret)
6113 return ret;
6114 }
6115
6116 return intel_modeset_synced_crtcs(state, conn);
6117 }
6118
intel_dp_oob_hotplug_event(struct drm_connector * connector,enum drm_connector_status hpd_state)6119 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6120 enum drm_connector_status hpd_state)
6121 {
6122 struct intel_display *display = to_intel_display(connector->dev);
6123 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6124 struct drm_i915_private *i915 = to_i915(connector->dev);
6125 bool hpd_high = hpd_state == connector_status_connected;
6126 unsigned int hpd_pin = encoder->hpd_pin;
6127 bool need_work = false;
6128
6129 spin_lock_irq(&i915->irq_lock);
6130 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6131 display->hotplug.event_bits |= BIT(hpd_pin);
6132
6133 __assign_bit(hpd_pin,
6134 &display->hotplug.oob_hotplug_last_state,
6135 hpd_high);
6136 need_work = true;
6137 }
6138 spin_unlock_irq(&i915->irq_lock);
6139
6140 if (need_work)
6141 intel_hpd_schedule_detection(i915);
6142 }
6143
6144 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6145 .force = intel_dp_force,
6146 .fill_modes = drm_helper_probe_single_connector_modes,
6147 .atomic_get_property = intel_digital_connector_atomic_get_property,
6148 .atomic_set_property = intel_digital_connector_atomic_set_property,
6149 .late_register = intel_dp_connector_register,
6150 .early_unregister = intel_dp_connector_unregister,
6151 .destroy = intel_connector_destroy,
6152 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6153 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6154 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6155 };
6156
6157 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6158 .detect_ctx = intel_dp_detect,
6159 .get_modes = intel_dp_get_modes,
6160 .mode_valid = intel_dp_mode_valid,
6161 .atomic_check = intel_dp_connector_atomic_check,
6162 };
6163
6164 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * dig_port,bool long_hpd)6165 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6166 {
6167 struct intel_display *display = to_intel_display(dig_port);
6168 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6169 struct intel_dp *intel_dp = &dig_port->dp;
6170 u8 dpcd[DP_RECEIVER_CAP_SIZE];
6171
6172 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6173 (long_hpd ||
6174 intel_runtime_pm_suspended(&i915->runtime_pm) ||
6175 !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6176 /*
6177 * vdd off can generate a long/short pulse on eDP which
6178 * would require vdd on to handle it, and thus we
6179 * would end up in an endless cycle of
6180 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6181 */
6182 drm_dbg_kms(display->drm,
6183 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6184 long_hpd ? "long" : "short",
6185 dig_port->base.base.base.id,
6186 dig_port->base.base.name);
6187 return IRQ_HANDLED;
6188 }
6189
6190 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6191 dig_port->base.base.base.id,
6192 dig_port->base.base.name,
6193 long_hpd ? "long" : "short");
6194
6195 /*
6196 * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6197 * response to long HPD pulses. The DP hotplug handler does that,
6198 * however the hotplug handler may be blocked by another
6199 * connector's/encoder's hotplug handler. Since the TBT CM may not
6200 * complete the DP tunnel BW request for the latter connector/encoder
6201 * waiting for this encoder's DPRX read, perform a dummy read here.
6202 */
6203 if (long_hpd)
6204 intel_dp_read_dprx_caps(intel_dp, dpcd);
6205
6206 if (long_hpd) {
6207 intel_dp->reset_link_params = true;
6208 intel_dp_invalidate_source_oui(intel_dp);
6209
6210 return IRQ_NONE;
6211 }
6212
6213 if (intel_dp->is_mst) {
6214 if (!intel_dp_check_mst_status(intel_dp))
6215 return IRQ_NONE;
6216 } else if (!intel_dp_short_pulse(intel_dp)) {
6217 return IRQ_NONE;
6218 }
6219
6220 return IRQ_HANDLED;
6221 }
6222
_intel_dp_is_port_edp(struct intel_display * display,const struct intel_bios_encoder_data * devdata,enum port port)6223 static bool _intel_dp_is_port_edp(struct intel_display *display,
6224 const struct intel_bios_encoder_data *devdata,
6225 enum port port)
6226 {
6227 /*
6228 * eDP not supported on g4x. so bail out early just
6229 * for a bit extra safety in case the VBT is bonkers.
6230 */
6231 if (DISPLAY_VER(display) < 5)
6232 return false;
6233
6234 if (DISPLAY_VER(display) < 9 && port == PORT_A)
6235 return true;
6236
6237 return devdata && intel_bios_encoder_supports_edp(devdata);
6238 }
6239
intel_dp_is_port_edp(struct intel_display * display,enum port port)6240 bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6241 {
6242 const struct intel_bios_encoder_data *devdata =
6243 intel_bios_encoder_data_lookup(display, port);
6244
6245 return _intel_dp_is_port_edp(display, devdata, port);
6246 }
6247
6248 bool
intel_dp_has_gamut_metadata_dip(struct intel_encoder * encoder)6249 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6250 {
6251 struct intel_display *display = to_intel_display(encoder);
6252 enum port port = encoder->port;
6253
6254 if (intel_bios_encoder_is_lspcon(encoder->devdata))
6255 return false;
6256
6257 if (DISPLAY_VER(display) >= 11)
6258 return true;
6259
6260 if (port == PORT_A)
6261 return false;
6262
6263 if (display->platform.haswell || display->platform.broadwell ||
6264 DISPLAY_VER(display) >= 9)
6265 return true;
6266
6267 return false;
6268 }
6269
6270 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)6271 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6272 {
6273 struct intel_display *display = to_intel_display(intel_dp);
6274 enum port port = dp_to_dig_port(intel_dp)->base.port;
6275
6276 if (!intel_dp_is_edp(intel_dp))
6277 drm_connector_attach_dp_subconnector_property(connector);
6278
6279 if (!display->platform.g4x && port != PORT_A)
6280 intel_attach_force_audio_property(connector);
6281
6282 intel_attach_broadcast_rgb_property(connector);
6283 if (HAS_GMCH(display))
6284 drm_connector_attach_max_bpc_property(connector, 6, 10);
6285 else if (DISPLAY_VER(display) >= 5)
6286 drm_connector_attach_max_bpc_property(connector, 6, 12);
6287
6288 /* Register HDMI colorspace for case of lspcon */
6289 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6290 drm_connector_attach_content_type_property(connector);
6291 intel_attach_hdmi_colorspace_property(connector);
6292 } else {
6293 intel_attach_dp_colorspace_property(connector);
6294 }
6295
6296 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6297 drm_connector_attach_hdr_output_metadata_property(connector);
6298
6299 if (HAS_VRR(display))
6300 drm_connector_attach_vrr_capable_property(connector);
6301 }
6302
6303 static void
intel_edp_add_properties(struct intel_dp * intel_dp)6304 intel_edp_add_properties(struct intel_dp *intel_dp)
6305 {
6306 struct intel_display *display = to_intel_display(intel_dp);
6307 struct intel_connector *connector = intel_dp->attached_connector;
6308 const struct drm_display_mode *fixed_mode =
6309 intel_panel_preferred_fixed_mode(connector);
6310
6311 intel_attach_scaling_mode_property(&connector->base);
6312
6313 drm_connector_set_panel_orientation_with_quirk(&connector->base,
6314 display->vbt.orientation,
6315 fixed_mode->hdisplay,
6316 fixed_mode->vdisplay);
6317 }
6318
intel_edp_backlight_setup(struct intel_dp * intel_dp,struct intel_connector * connector)6319 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6320 struct intel_connector *connector)
6321 {
6322 struct intel_display *display = to_intel_display(intel_dp);
6323 enum pipe pipe = INVALID_PIPE;
6324
6325 if (display->platform.valleyview || display->platform.cherryview)
6326 pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6327
6328 intel_backlight_setup(connector, pipe);
6329 }
6330
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * connector)6331 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6332 struct intel_connector *connector)
6333 {
6334 struct intel_display *display = to_intel_display(intel_dp);
6335 struct drm_i915_private *dev_priv = to_i915(display->drm);
6336 struct drm_display_mode *fixed_mode;
6337 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6338 bool has_dpcd;
6339 const struct drm_edid *drm_edid;
6340
6341 if (!intel_dp_is_edp(intel_dp))
6342 return true;
6343
6344 /*
6345 * On IBX/CPT we may get here with LVDS already registered. Since the
6346 * driver uses the only internal power sequencer available for both
6347 * eDP and LVDS bail out early in this case to prevent interfering
6348 * with an already powered-on LVDS power sequencer.
6349 */
6350 if (intel_get_lvds_encoder(dev_priv)) {
6351 drm_WARN_ON(display->drm,
6352 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6353 drm_info(display->drm,
6354 "LVDS was detected, not registering eDP\n");
6355
6356 return false;
6357 }
6358
6359 intel_bios_init_panel_early(display, &connector->panel,
6360 encoder->devdata);
6361
6362 if (!intel_pps_init(intel_dp)) {
6363 drm_info(display->drm,
6364 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6365 encoder->base.base.id, encoder->base.name);
6366 /*
6367 * The BIOS may have still enabled VDD on the PPS even
6368 * though it's unusable. Make sure we turn it back off
6369 * and to release the power domain references/etc.
6370 */
6371 goto out_vdd_off;
6372 }
6373
6374 /*
6375 * Enable HPD sense for live status check.
6376 * intel_hpd_irq_setup() will turn it off again
6377 * if it's no longer needed later.
6378 *
6379 * The DPCD probe below will make sure VDD is on.
6380 */
6381 intel_hpd_enable_detection(encoder);
6382
6383 intel_alpm_init_dpcd(intel_dp);
6384
6385 /* Cache DPCD and EDID for edp. */
6386 has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
6387
6388 if (!has_dpcd) {
6389 /* if this fails, presume the device is a ghost */
6390 drm_info(display->drm,
6391 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6392 encoder->base.base.id, encoder->base.name);
6393 goto out_vdd_off;
6394 }
6395
6396 /*
6397 * VBT and straps are liars. Also check HPD as that seems
6398 * to be the most reliable piece of information available.
6399 *
6400 * ... expect on devices that forgot to hook HPD up for eDP
6401 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6402 * ports are attempting to use the same AUX CH, according to VBT.
6403 */
6404 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6405 /*
6406 * If this fails, presume the DPCD answer came
6407 * from some other port using the same AUX CH.
6408 *
6409 * FIXME maybe cleaner to check this before the
6410 * DPCD read? Would need sort out the VDD handling...
6411 */
6412 if (!intel_digital_port_connected(encoder)) {
6413 drm_info(display->drm,
6414 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6415 encoder->base.base.id, encoder->base.name);
6416 goto out_vdd_off;
6417 }
6418
6419 /*
6420 * Unfortunately even the HPD based detection fails on
6421 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6422 * back to checking for a VGA branch device. Only do this
6423 * on known affected platforms to minimize false positives.
6424 */
6425 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6426 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6427 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6428 drm_info(display->drm,
6429 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6430 encoder->base.base.id, encoder->base.name);
6431 goto out_vdd_off;
6432 }
6433 }
6434
6435 mutex_lock(&display->drm->mode_config.mutex);
6436 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
6437 if (!drm_edid) {
6438 /* Fallback to EDID from ACPI OpRegion, if any */
6439 drm_edid = intel_opregion_get_edid(connector);
6440 if (drm_edid)
6441 drm_dbg_kms(display->drm,
6442 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6443 connector->base.base.id, connector->base.name);
6444 }
6445 if (drm_edid) {
6446 if (drm_edid_connector_update(&connector->base, drm_edid) ||
6447 !drm_edid_connector_add_modes(&connector->base)) {
6448 drm_edid_connector_update(&connector->base, NULL);
6449 drm_edid_free(drm_edid);
6450 drm_edid = ERR_PTR(-EINVAL);
6451 }
6452 } else {
6453 drm_edid = ERR_PTR(-ENOENT);
6454 }
6455
6456 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,
6457 IS_ERR(drm_edid) ? NULL : drm_edid);
6458
6459 intel_panel_add_edid_fixed_modes(connector, true);
6460
6461 /* MSO requires information from the EDID */
6462 intel_edp_mso_init(intel_dp);
6463
6464 /* multiply the mode clock and horizontal timings for MSO */
6465 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
6466 intel_edp_mso_mode_fixup(connector, fixed_mode);
6467
6468 /* fallback to VBT if available for eDP */
6469 if (!intel_panel_preferred_fixed_mode(connector))
6470 intel_panel_add_vbt_lfp_fixed_mode(connector);
6471
6472 mutex_unlock(&display->drm->mode_config.mutex);
6473
6474 if (!intel_panel_preferred_fixed_mode(connector)) {
6475 drm_info(display->drm,
6476 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6477 encoder->base.base.id, encoder->base.name);
6478 goto out_vdd_off;
6479 }
6480
6481 intel_panel_init(connector, drm_edid);
6482
6483 intel_edp_backlight_setup(intel_dp, connector);
6484
6485 intel_edp_add_properties(intel_dp);
6486
6487 intel_pps_init_late(intel_dp);
6488
6489 return true;
6490
6491 out_vdd_off:
6492 intel_pps_vdd_off_sync(intel_dp);
6493 intel_bios_fini_panel(&connector->panel);
6494
6495 return false;
6496 }
6497
intel_dp_modeset_retry_work_fn(struct work_struct * work)6498 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6499 {
6500 struct intel_connector *connector = container_of(work, typeof(*connector),
6501 modeset_retry_work);
6502 struct intel_display *display = to_intel_display(connector);
6503
6504 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,
6505 connector->base.name);
6506
6507 /* Grab the locks before changing connector property*/
6508 mutex_lock(&display->drm->mode_config.mutex);
6509 /* Set connector link status to BAD and send a Uevent to notify
6510 * userspace to do a modeset.
6511 */
6512 drm_connector_set_link_status_property(&connector->base,
6513 DRM_MODE_LINK_STATUS_BAD);
6514 mutex_unlock(&display->drm->mode_config.mutex);
6515 /* Send Hotplug uevent so userspace can reprobe */
6516 drm_kms_helper_connector_hotplug_event(&connector->base);
6517
6518 drm_connector_put(&connector->base);
6519 }
6520
intel_dp_init_modeset_retry_work(struct intel_connector * connector)6521 void intel_dp_init_modeset_retry_work(struct intel_connector *connector)
6522 {
6523 INIT_WORK(&connector->modeset_retry_work,
6524 intel_dp_modeset_retry_work_fn);
6525 }
6526
6527 bool
intel_dp_init_connector(struct intel_digital_port * dig_port,struct intel_connector * connector)6528 intel_dp_init_connector(struct intel_digital_port *dig_port,
6529 struct intel_connector *connector)
6530 {
6531 struct intel_display *display = to_intel_display(dig_port);
6532 struct intel_dp *intel_dp = &dig_port->dp;
6533 struct intel_encoder *encoder = &dig_port->base;
6534 struct drm_device *dev = encoder->base.dev;
6535 struct drm_i915_private *dev_priv = to_i915(dev);
6536 enum port port = encoder->port;
6537 int type;
6538
6539 /* Initialize the work for modeset in case of link train failure */
6540 intel_dp_init_modeset_retry_work(connector);
6541
6542 if (drm_WARN(dev, dig_port->max_lanes < 1,
6543 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6544 dig_port->max_lanes, encoder->base.base.id,
6545 encoder->base.name))
6546 return false;
6547
6548 intel_dp->reset_link_params = true;
6549
6550 /* Preserve the current hw state. */
6551 intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
6552 intel_dp->attached_connector = connector;
6553
6554 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {
6555 /*
6556 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6557 * although in theory it could work on TypeC legacy ports.
6558 */
6559 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6560 DISPLAY_VER(display) < 30);
6561 type = DRM_MODE_CONNECTOR_eDP;
6562 encoder->type = INTEL_OUTPUT_EDP;
6563
6564 /* eDP only on port B and/or C on vlv/chv */
6565 if (drm_WARN_ON(dev, (display->platform.valleyview ||
6566 display->platform.cherryview) &&
6567 port != PORT_B && port != PORT_C))
6568 return false;
6569 } else {
6570 type = DRM_MODE_CONNECTOR_DisplayPort;
6571 }
6572
6573 intel_dp_set_default_sink_rates(intel_dp);
6574 intel_dp_set_default_max_sink_lane_count(intel_dp);
6575
6576 if (display->platform.valleyview || display->platform.cherryview)
6577 vlv_pps_pipe_init(intel_dp);
6578
6579 intel_dp_aux_init(intel_dp);
6580 connector->dp.dsc_decompression_aux = &intel_dp->aux;
6581
6582 drm_dbg_kms(display->drm,
6583 "Adding %s connector on [ENCODER:%d:%s]\n",
6584 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6585 encoder->base.base.id, encoder->base.name);
6586
6587 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs,
6588 type, &intel_dp->aux.ddc);
6589 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);
6590
6591 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6592 connector->base.interlace_allowed = true;
6593
6594 if (type != DRM_MODE_CONNECTOR_eDP)
6595 connector->polled = DRM_CONNECTOR_POLL_HPD;
6596 connector->base.polled = connector->polled;
6597
6598 intel_connector_attach_encoder(connector, encoder);
6599
6600 if (HAS_DDI(display))
6601 connector->get_hw_state = intel_ddi_connector_get_hw_state;
6602 else
6603 connector->get_hw_state = intel_connector_get_hw_state;
6604 connector->sync_state = intel_dp_connector_sync_state;
6605
6606 if (!intel_edp_init_connector(intel_dp, connector)) {
6607 intel_dp_aux_fini(intel_dp);
6608 goto fail;
6609 }
6610
6611 intel_dp_set_source_rates(intel_dp);
6612 intel_dp_set_common_rates(intel_dp);
6613 intel_dp_reset_link_params(intel_dp);
6614
6615 /* init MST on ports that can support it */
6616 intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
6617
6618 intel_dp_add_properties(intel_dp, &connector->base);
6619
6620 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6621 int ret = intel_dp_hdcp_init(dig_port, connector);
6622 if (ret)
6623 drm_dbg_kms(display->drm,
6624 "HDCP init failed, skipping.\n");
6625 }
6626
6627 intel_dp->frl.is_trained = false;
6628 intel_dp->frl.trained_rate_gbps = 0;
6629
6630 intel_psr_init(intel_dp);
6631
6632 return true;
6633
6634 fail:
6635 intel_display_power_flush_work(dev_priv);
6636 drm_connector_cleanup(&connector->base);
6637
6638 return false;
6639 }
6640
intel_dp_mst_suspend(struct intel_display * display)6641 void intel_dp_mst_suspend(struct intel_display *display)
6642 {
6643 struct intel_encoder *encoder;
6644
6645 if (!HAS_DISPLAY(display))
6646 return;
6647
6648 for_each_intel_encoder(display->drm, encoder) {
6649 struct intel_dp *intel_dp;
6650
6651 if (encoder->type != INTEL_OUTPUT_DDI)
6652 continue;
6653
6654 intel_dp = enc_to_intel_dp(encoder);
6655
6656 if (!intel_dp_mst_source_support(intel_dp))
6657 continue;
6658
6659 if (intel_dp->is_mst)
6660 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6661 }
6662 }
6663
intel_dp_mst_resume(struct intel_display * display)6664 void intel_dp_mst_resume(struct intel_display *display)
6665 {
6666 struct intel_encoder *encoder;
6667
6668 if (!HAS_DISPLAY(display))
6669 return;
6670
6671 for_each_intel_encoder(display->drm, encoder) {
6672 struct intel_dp *intel_dp;
6673 int ret;
6674
6675 if (encoder->type != INTEL_OUTPUT_DDI)
6676 continue;
6677
6678 intel_dp = enc_to_intel_dp(encoder);
6679
6680 if (!intel_dp_mst_source_support(intel_dp))
6681 continue;
6682
6683 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6684 true);
6685 if (ret) {
6686 intel_dp->is_mst = false;
6687 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6688 false);
6689 }
6690 }
6691 }
6692