1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2025 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 */
6
7 #include <linux/devcoredump.h>
8 #include <linux/firmware.h>
9 #include <linux/platform_device.h>
10 #include <linux/of_net.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_reserved_mem.h>
13 #include <linux/regmap.h>
14
15 #include "airoha_eth.h"
16
17 #define NPU_EN7581_FIRMWARE_DATA "airoha/en7581_npu_data.bin"
18 #define NPU_EN7581_FIRMWARE_RV32 "airoha/en7581_npu_rv32.bin"
19 #define NPU_EN7581_7996_FIRMWARE_DATA "airoha/en7581_MT7996_npu_data.bin"
20 #define NPU_EN7581_7996_FIRMWARE_RV32 "airoha/en7581_MT7996_npu_rv32.bin"
21 #define NPU_AN7583_FIRMWARE_DATA "airoha/an7583_npu_data.bin"
22 #define NPU_AN7583_FIRMWARE_RV32 "airoha/an7583_npu_rv32.bin"
23 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000
24 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x10000
25 #define NPU_DUMP_SIZE 512
26
27 #define REG_NPU_LOCAL_SRAM 0x0
28
29 #define NPU_PC_BASE_ADDR 0x305000
30 #define REG_PC_DBG(_n) (0x305000 + ((_n) * 0x100))
31
32 #define NPU_CLUSTER_BASE_ADDR 0x306000
33
34 #define REG_CR_BOOT_TRIGGER (NPU_CLUSTER_BASE_ADDR + 0x000)
35 #define REG_CR_BOOT_CONFIG (NPU_CLUSTER_BASE_ADDR + 0x004)
36 #define REG_CR_BOOT_BASE(_n) (NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2))
37
38 #define NPU_MBOX_BASE_ADDR 0x30c000
39
40 #define REG_CR_MBOX_INT_STATUS (NPU_MBOX_BASE_ADDR + 0x000)
41 #define MBOX_INT_STATUS_MASK BIT(8)
42
43 #define REG_CR_MBOX_INT_MASK(_n) (NPU_MBOX_BASE_ADDR + 0x004 + ((_n) << 2))
44 #define REG_CR_MBQ0_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x030 + ((_n) << 2))
45 #define REG_CR_MBQ8_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x0b0 + ((_n) << 2))
46 #define REG_CR_NPU_MIB(_n) (NPU_MBOX_BASE_ADDR + 0x140 + ((_n) << 2))
47
48 #define NPU_WLAN_BASE_ADDR 0x30d000
49
50 #define REG_IRQ_STATUS (NPU_WLAN_BASE_ADDR + 0x030)
51 #define REG_IRQ_RXDONE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 2) + 0x034)
52 #define NPU_IRQ_RX_MASK(_n) ((_n) == 1 ? BIT(17) : BIT(16))
53
54 #define REG_TX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x080)
55 #define REG_TX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x084)
56 #define REG_TX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x088)
57 #define REG_TX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x08c)
58
59 #define REG_RX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x180)
60 #define REG_RX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x184)
61 #define REG_RX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x188)
62 #define REG_RX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x18c)
63
64 #define NPU_TIMER_BASE_ADDR 0x310100
65 #define REG_WDT_TIMER_CTRL(_n) (NPU_TIMER_BASE_ADDR + ((_n) * 0x100))
66 #define WDT_EN_MASK BIT(25)
67 #define WDT_INTR_MASK BIT(21)
68
69 enum {
70 NPU_OP_SET = 1,
71 NPU_OP_SET_NO_WAIT,
72 NPU_OP_GET,
73 NPU_OP_GET_NO_WAIT,
74 };
75
76 enum {
77 NPU_FUNC_WIFI,
78 NPU_FUNC_TUNNEL,
79 NPU_FUNC_NOTIFY,
80 NPU_FUNC_DBA,
81 NPU_FUNC_TR471,
82 NPU_FUNC_PPE,
83 };
84
85 enum {
86 NPU_MBOX_ERROR,
87 NPU_MBOX_SUCCESS,
88 };
89
90 enum {
91 PPE_FUNC_SET_WAIT,
92 PPE_FUNC_SET_WAIT_HWNAT_INIT,
93 PPE_FUNC_SET_WAIT_HWNAT_DEINIT,
94 PPE_FUNC_SET_WAIT_API,
95 PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP,
96 };
97
98 enum {
99 PPE2_SRAM_SET_ENTRY,
100 PPE_SRAM_SET_ENTRY,
101 PPE_SRAM_SET_VAL,
102 PPE_SRAM_RESET_VAL,
103 };
104
105 enum {
106 QDMA_WAN_ETHER = 1,
107 QDMA_WAN_PON_XDSL,
108 };
109
110 struct airoha_npu_fw {
111 const char *name;
112 int max_size;
113 };
114
115 struct airoha_npu_soc_data {
116 struct airoha_npu_fw fw_rv32;
117 struct airoha_npu_fw fw_data;
118 };
119
120 #define MBOX_MSG_FUNC_ID GENMASK(14, 11)
121 #define MBOX_MSG_STATIC_BUF BIT(5)
122 #define MBOX_MSG_STATUS GENMASK(4, 2)
123 #define MBOX_MSG_DONE BIT(1)
124 #define MBOX_MSG_WAIT_RSP BIT(0)
125
126 #define PPE_TYPE_L2B_IPV4 2
127 #define PPE_TYPE_L2B_IPV4_IPV6 3
128
129 struct ppe_mbox_data {
130 u32 func_type;
131 u32 func_id;
132 union {
133 struct {
134 u8 cds;
135 u8 xpon_hal_api;
136 u8 wan_xsi;
137 u8 ct_joyme4;
138 u8 max_packet;
139 u8 rsv[3];
140 u32 ppe_type;
141 u32 wan_mode;
142 u32 wan_sel;
143 } init_info;
144 struct {
145 u32 func_id;
146 u32 size;
147 u32 data;
148 } set_info;
149 struct {
150 u32 npu_stats_addr;
151 u32 foe_stats_addr;
152 } stats_info;
153 };
154 };
155
156 struct wlan_mbox_data {
157 u32 ifindex:4;
158 u32 func_type:4;
159 u32 func_id;
160 DECLARE_FLEX_ARRAY(u8, d);
161 };
162
airoha_npu_send_msg(struct airoha_npu * npu,int func_id,void * p,int size)163 static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
164 void *p, int size)
165 {
166 u16 core = 0; /* FIXME */
167 u32 val, offset = core << 4;
168 dma_addr_t dma_addr;
169 int ret;
170
171 dma_addr = dma_map_single(npu->dev, p, size, DMA_BIDIRECTIONAL);
172 ret = dma_mapping_error(npu->dev, dma_addr);
173 if (ret)
174 return ret;
175
176 spin_lock_bh(&npu->cores[core].lock);
177
178 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr);
179 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size);
180 regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val);
181 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1);
182 val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP;
183 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val);
184
185 ret = regmap_read_poll_timeout_atomic(npu->regmap,
186 REG_CR_MBQ0_CTRL(3) + offset,
187 val, (val & MBOX_MSG_DONE),
188 100, 100 * MSEC_PER_SEC);
189 if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS)
190 ret = -EINVAL;
191
192 spin_unlock_bh(&npu->cores[core].lock);
193
194 dma_unmap_single(npu->dev, dma_addr, size, DMA_BIDIRECTIONAL);
195
196 return ret;
197 }
198
airoha_npu_load_firmware(struct device * dev,void __iomem * addr,const char * fw_name,int fw_max_size)199 static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr,
200 const char *fw_name, int fw_max_size)
201 {
202 const struct firmware *fw;
203 int ret;
204
205 ret = request_firmware_direct(&fw, fw_name, dev);
206 if (ret)
207 return dev_err_probe(dev, ret == -ENOENT ? -EPROBE_DEFER : ret,
208 "failed to load %s\n", fw_name);
209
210 if (fw->size > fw_max_size) {
211 dev_err(dev, "%s: fw size too overlimit (%zu)\n",
212 fw_name, fw->size);
213 ret = -E2BIG;
214 goto out;
215 }
216
217 memcpy_toio(addr, fw->data, fw->size);
218 out:
219 release_firmware(fw);
220
221 return ret;
222 }
223
224 static int
airoha_npu_load_firmware_from_dts(struct device * dev,void __iomem * addr,void __iomem * base)225 airoha_npu_load_firmware_from_dts(struct device *dev, void __iomem *addr,
226 void __iomem *base)
227 {
228 const char *fw_names[2];
229 int ret;
230
231 ret = of_property_read_string_array(dev->of_node, "firmware-name",
232 fw_names, ARRAY_SIZE(fw_names));
233 if (ret != ARRAY_SIZE(fw_names))
234 return dev_err_probe(dev, -EINVAL,
235 "invalid firmware-name property\n");
236
237 ret = airoha_npu_load_firmware(dev, addr, fw_names[0],
238 NPU_EN7581_FIRMWARE_RV32_MAX_SIZE);
239 if (ret)
240 return ret;
241
242 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,
243 fw_names[1],
244 NPU_EN7581_FIRMWARE_DATA_MAX_SIZE);
245 }
246
airoha_npu_run_firmware(struct device * dev,void __iomem * base,struct resource * res)247 static int airoha_npu_run_firmware(struct device *dev, void __iomem *base,
248 struct resource *res)
249 {
250 const struct airoha_npu_soc_data *soc;
251 void __iomem *addr;
252 int ret;
253
254 soc = of_device_get_match_data(dev);
255 if (!soc)
256 return -EINVAL;
257
258 addr = devm_ioremap_resource(dev, res);
259 if (IS_ERR(addr))
260 return PTR_ERR(addr);
261
262 /* Try to load firmware images using the firmware names provided via
263 * dts if available.
264 */
265 if (of_find_property(dev->of_node, "firmware-name", NULL))
266 return airoha_npu_load_firmware_from_dts(dev, addr, base);
267
268 /* Load rv32 npu firmware */
269 ret = airoha_npu_load_firmware(dev, addr, soc->fw_rv32.name,
270 soc->fw_rv32.max_size);
271 if (ret)
272 return ret;
273
274 /* Load data npu firmware */
275 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM,
276 soc->fw_data.name,
277 soc->fw_data.max_size);
278 }
279
airoha_npu_mbox_handler(int irq,void * npu_instance)280 static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance)
281 {
282 struct airoha_npu *npu = npu_instance;
283
284 /* clear mbox interrupt status */
285 regmap_write(npu->regmap, REG_CR_MBOX_INT_STATUS,
286 MBOX_INT_STATUS_MASK);
287
288 /* acknowledge npu */
289 regmap_update_bits(npu->regmap, REG_CR_MBQ8_CTRL(3),
290 MBOX_MSG_STATUS | MBOX_MSG_DONE, MBOX_MSG_DONE);
291
292 return IRQ_HANDLED;
293 }
294
airoha_npu_wdt_work(struct work_struct * work)295 static void airoha_npu_wdt_work(struct work_struct *work)
296 {
297 struct airoha_npu_core *core;
298 struct airoha_npu *npu;
299 void *dump;
300 u32 val[3];
301 int c;
302
303 core = container_of(work, struct airoha_npu_core, wdt_work);
304 npu = core->npu;
305
306 dump = vzalloc(NPU_DUMP_SIZE);
307 if (!dump)
308 return;
309
310 c = core - &npu->cores[0];
311 regmap_bulk_read(npu->regmap, REG_PC_DBG(c), val, ARRAY_SIZE(val));
312 snprintf(dump, NPU_DUMP_SIZE, "PC: %08x SP: %08x LR: %08x\n",
313 val[0], val[1], val[2]);
314
315 dev_coredumpv(npu->dev, dump, NPU_DUMP_SIZE, GFP_KERNEL);
316 }
317
airoha_npu_wdt_handler(int irq,void * core_instance)318 static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)
319 {
320 struct airoha_npu_core *core = core_instance;
321 struct airoha_npu *npu = core->npu;
322 int c = core - &npu->cores[0];
323 u32 val;
324
325 regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK);
326 if (!regmap_read(npu->regmap, REG_WDT_TIMER_CTRL(c), &val) &&
327 FIELD_GET(WDT_EN_MASK, val))
328 schedule_work(&core->wdt_work);
329
330 return IRQ_HANDLED;
331 }
332
airoha_npu_ppe_init(struct airoha_npu * npu)333 static int airoha_npu_ppe_init(struct airoha_npu *npu)
334 {
335 struct ppe_mbox_data *ppe_data;
336 int err;
337
338 ppe_data = kzalloc_obj(*ppe_data);
339 if (!ppe_data)
340 return -ENOMEM;
341
342 ppe_data->func_type = NPU_OP_SET;
343 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT;
344 ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6;
345 ppe_data->init_info.wan_mode = QDMA_WAN_ETHER;
346
347 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
348 sizeof(*ppe_data));
349 kfree(ppe_data);
350
351 return err;
352 }
353
airoha_npu_ppe_deinit(struct airoha_npu * npu)354 static int airoha_npu_ppe_deinit(struct airoha_npu *npu)
355 {
356 struct ppe_mbox_data *ppe_data;
357 int err;
358
359 ppe_data = kzalloc_obj(*ppe_data);
360 if (!ppe_data)
361 return -ENOMEM;
362
363 ppe_data->func_type = NPU_OP_SET;
364 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT;
365
366 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
367 sizeof(*ppe_data));
368 kfree(ppe_data);
369
370 return err;
371 }
372
airoha_npu_ppe_flush_sram_entries(struct airoha_npu * npu,dma_addr_t foe_addr,int sram_num_entries)373 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu,
374 dma_addr_t foe_addr,
375 int sram_num_entries)
376 {
377 struct ppe_mbox_data *ppe_data;
378 int err;
379
380 ppe_data = kzalloc_obj(*ppe_data);
381 if (!ppe_data)
382 return -ENOMEM;
383
384 ppe_data->func_type = NPU_OP_SET;
385 ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
386 ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL;
387 ppe_data->set_info.data = foe_addr;
388 ppe_data->set_info.size = sram_num_entries;
389
390 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
391 sizeof(*ppe_data));
392 kfree(ppe_data);
393
394 return err;
395 }
396
airoha_npu_foe_commit_entry(struct airoha_npu * npu,dma_addr_t foe_addr,u32 entry_size,u32 hash,bool ppe2)397 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu,
398 dma_addr_t foe_addr,
399 u32 entry_size, u32 hash, bool ppe2)
400 {
401 struct ppe_mbox_data *ppe_data;
402 int err;
403
404 ppe_data = kzalloc_obj(*ppe_data, GFP_ATOMIC);
405 if (!ppe_data)
406 return -ENOMEM;
407
408 ppe_data->func_type = NPU_OP_SET;
409 ppe_data->func_id = PPE_FUNC_SET_WAIT_API;
410 ppe_data->set_info.data = foe_addr;
411 ppe_data->set_info.size = entry_size;
412 ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
413 : PPE_SRAM_SET_ENTRY;
414
415 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
416 sizeof(*ppe_data));
417 if (err)
418 goto out;
419
420 ppe_data->set_info.func_id = PPE_SRAM_SET_VAL;
421 ppe_data->set_info.data = hash;
422 ppe_data->set_info.size = sizeof(u32);
423
424 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
425 sizeof(*ppe_data));
426 out:
427 kfree(ppe_data);
428
429 return err;
430 }
431
airoha_npu_ppe_stats_setup(struct airoha_npu * npu,dma_addr_t foe_stats_addr,u32 num_stats_entries)432 static int airoha_npu_ppe_stats_setup(struct airoha_npu *npu,
433 dma_addr_t foe_stats_addr,
434 u32 num_stats_entries)
435 {
436 int err, size = num_stats_entries * sizeof(*npu->stats);
437 struct ppe_mbox_data *ppe_data;
438
439 ppe_data = kzalloc_obj(*ppe_data, GFP_ATOMIC);
440 if (!ppe_data)
441 return -ENOMEM;
442
443 ppe_data->func_type = NPU_OP_SET;
444 ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP;
445 ppe_data->stats_info.foe_stats_addr = foe_stats_addr;
446
447 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data,
448 sizeof(*ppe_data));
449 if (err)
450 goto out;
451
452 npu->stats = devm_ioremap(npu->dev,
453 ppe_data->stats_info.npu_stats_addr,
454 size);
455 if (!npu->stats)
456 err = -ENOMEM;
457 out:
458 kfree(ppe_data);
459
460 return err;
461 }
462
airoha_npu_wlan_msg_send(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_set_cmd func_id,void * data,int data_len,gfp_t gfp)463 static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex,
464 enum airoha_npu_wlan_set_cmd func_id,
465 void *data, int data_len, gfp_t gfp)
466 {
467 struct wlan_mbox_data *wlan_data;
468 int err, len;
469
470 len = sizeof(*wlan_data) + data_len;
471 wlan_data = kzalloc(len, gfp);
472 if (!wlan_data)
473 return -ENOMEM;
474
475 wlan_data->ifindex = ifindex;
476 wlan_data->func_type = NPU_OP_SET;
477 wlan_data->func_id = func_id;
478 memcpy(wlan_data->d, data, data_len);
479
480 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);
481 kfree(wlan_data);
482
483 return err;
484 }
485
airoha_npu_wlan_msg_get(struct airoha_npu * npu,int ifindex,enum airoha_npu_wlan_get_cmd func_id,void * data,int data_len,gfp_t gfp)486 static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex,
487 enum airoha_npu_wlan_get_cmd func_id,
488 void *data, int data_len, gfp_t gfp)
489 {
490 struct wlan_mbox_data *wlan_data;
491 int err, len;
492
493 len = sizeof(*wlan_data) + data_len;
494 wlan_data = kzalloc(len, gfp);
495 if (!wlan_data)
496 return -ENOMEM;
497
498 wlan_data->ifindex = ifindex;
499 wlan_data->func_type = NPU_OP_GET;
500 wlan_data->func_id = func_id;
501
502 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len);
503 if (!err)
504 memcpy(data, wlan_data->d, data_len);
505 kfree(wlan_data);
506
507 return err;
508 }
509
510 static int
airoha_npu_wlan_set_reserved_memory(struct airoha_npu * npu,int ifindex,const char * name,enum airoha_npu_wlan_set_cmd func_id)511 airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu,
512 int ifindex, const char *name,
513 enum airoha_npu_wlan_set_cmd func_id)
514 {
515 struct device *dev = npu->dev;
516 struct resource res;
517 int err;
518 u32 val;
519
520 err = of_reserved_mem_region_to_resource_byname(dev->of_node, name,
521 &res);
522 if (err)
523 return err;
524
525 val = res.start;
526 return airoha_npu_wlan_msg_send(npu, ifindex, func_id, &val,
527 sizeof(val), GFP_KERNEL);
528 }
529
airoha_npu_wlan_init_memory(struct airoha_npu * npu)530 static int airoha_npu_wlan_init_memory(struct airoha_npu *npu)
531 {
532 enum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU;
533 u32 val = 0;
534 int err;
535
536 err = airoha_npu_wlan_msg_send(npu, 1, cmd, &val, sizeof(val),
537 GFP_KERNEL);
538 if (err)
539 return err;
540
541 cmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR;
542 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-bufid", cmd);
543 if (err)
544 return err;
545
546 cmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR;
547 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "pkt", cmd);
548 if (err)
549 return err;
550
551 cmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR;
552 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-pkt", cmd);
553 if (err)
554 return err;
555
556 if (of_property_match_string(npu->dev->of_node, "memory-region-names",
557 "ba") >= 0) {
558 cmd = WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR;
559 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "ba", cmd);
560 if (err)
561 return err;
562 }
563
564 cmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU;
565 return airoha_npu_wlan_msg_send(npu, 0, cmd, &val, sizeof(val),
566 GFP_KERNEL);
567 }
568
airoha_npu_wlan_queue_addr_get(struct airoha_npu * npu,int qid,bool xmit)569 static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid,
570 bool xmit)
571 {
572 if (xmit)
573 return REG_TX_BASE(qid + 2);
574
575 return REG_RX_BASE(qid);
576 }
577
airoha_npu_wlan_irq_status_set(struct airoha_npu * npu,u32 val)578 static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val)
579 {
580 regmap_write(npu->regmap, REG_IRQ_STATUS, val);
581 }
582
airoha_npu_wlan_irq_status_get(struct airoha_npu * npu,int q)583 static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q)
584 {
585 u32 val;
586
587 regmap_read(npu->regmap, REG_IRQ_STATUS, &val);
588 return val;
589 }
590
airoha_npu_wlan_irq_enable(struct airoha_npu * npu,int q)591 static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q)
592 {
593 regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q));
594 }
595
airoha_npu_wlan_irq_disable(struct airoha_npu * npu,int q)596 static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q)
597 {
598 regmap_clear_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q));
599 }
600
airoha_npu_get(struct device * dev)601 struct airoha_npu *airoha_npu_get(struct device *dev)
602 {
603 struct platform_device *pdev;
604 struct device_node *np;
605 struct airoha_npu *npu;
606
607 np = of_parse_phandle(dev->of_node, "airoha,npu", 0);
608 if (!np)
609 return ERR_PTR(-ENODEV);
610
611 pdev = of_find_device_by_node(np);
612
613 if (!pdev) {
614 dev_err(dev, "cannot find device node %s\n", np->name);
615 of_node_put(np);
616 return ERR_PTR(-ENODEV);
617 }
618 of_node_put(np);
619
620 if (!try_module_get(THIS_MODULE)) {
621 dev_err(dev, "failed to get the device driver module\n");
622 npu = ERR_PTR(-ENODEV);
623 goto error_pdev_put;
624 }
625
626 npu = platform_get_drvdata(pdev);
627 if (!npu) {
628 npu = ERR_PTR(-ENODEV);
629 goto error_module_put;
630 }
631
632 if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER)) {
633 dev_err(&pdev->dev,
634 "failed to create device link to consumer %s\n",
635 dev_name(dev));
636 npu = ERR_PTR(-EINVAL);
637 goto error_module_put;
638 }
639
640 return npu;
641
642 error_module_put:
643 module_put(THIS_MODULE);
644 error_pdev_put:
645 platform_device_put(pdev);
646
647 return npu;
648 }
649 EXPORT_SYMBOL_GPL(airoha_npu_get);
650
airoha_npu_put(struct airoha_npu * npu)651 void airoha_npu_put(struct airoha_npu *npu)
652 {
653 module_put(THIS_MODULE);
654 put_device(npu->dev);
655 }
656 EXPORT_SYMBOL_GPL(airoha_npu_put);
657
658 static const struct airoha_npu_soc_data en7581_npu_soc_data = {
659 .fw_rv32 = {
660 .name = NPU_EN7581_FIRMWARE_RV32,
661 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE,
662 },
663 .fw_data = {
664 .name = NPU_EN7581_FIRMWARE_DATA,
665 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE,
666 },
667 };
668
669 static const struct airoha_npu_soc_data an7583_npu_soc_data = {
670 .fw_rv32 = {
671 .name = NPU_AN7583_FIRMWARE_RV32,
672 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE,
673 },
674 .fw_data = {
675 .name = NPU_AN7583_FIRMWARE_DATA,
676 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE,
677 },
678 };
679
680 static const struct of_device_id of_airoha_npu_match[] = {
681 { .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data },
682 { .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data },
683 { /* sentinel */ }
684 };
685 MODULE_DEVICE_TABLE(of, of_airoha_npu_match);
686
687 static const struct regmap_config regmap_config = {
688 .name = "npu",
689 .reg_bits = 32,
690 .val_bits = 32,
691 .reg_stride = 4,
692 .disable_locking = true,
693 };
694
airoha_npu_probe(struct platform_device * pdev)695 static int airoha_npu_probe(struct platform_device *pdev)
696 {
697 struct device *dev = &pdev->dev;
698 struct airoha_npu *npu;
699 struct resource res;
700 void __iomem *base;
701 int i, irq, err;
702 u32 val;
703
704 base = devm_platform_ioremap_resource(pdev, 0);
705 if (IS_ERR(base))
706 return PTR_ERR(base);
707
708 npu = devm_kzalloc(dev, sizeof(*npu), GFP_KERNEL);
709 if (!npu)
710 return -ENOMEM;
711
712 npu->dev = dev;
713 npu->ops.ppe_init = airoha_npu_ppe_init;
714 npu->ops.ppe_deinit = airoha_npu_ppe_deinit;
715 npu->ops.ppe_init_stats = airoha_npu_ppe_stats_setup;
716 npu->ops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries;
717 npu->ops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry;
718 npu->ops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory;
719 npu->ops.wlan_send_msg = airoha_npu_wlan_msg_send;
720 npu->ops.wlan_get_msg = airoha_npu_wlan_msg_get;
721 npu->ops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get;
722 npu->ops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set;
723 npu->ops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get;
724 npu->ops.wlan_enable_irq = airoha_npu_wlan_irq_enable;
725 npu->ops.wlan_disable_irq = airoha_npu_wlan_irq_disable;
726
727 npu->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
728 if (IS_ERR(npu->regmap))
729 return PTR_ERR(npu->regmap);
730
731 err = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
732 if (err)
733 return err;
734
735 irq = platform_get_irq(pdev, 0);
736 if (irq < 0)
737 return irq;
738
739 err = devm_request_irq(dev, irq, airoha_npu_mbox_handler,
740 IRQF_SHARED, "airoha-npu-mbox", npu);
741 if (err)
742 return err;
743
744 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) {
745 struct airoha_npu_core *core = &npu->cores[i];
746
747 spin_lock_init(&core->lock);
748 core->npu = npu;
749
750 irq = platform_get_irq(pdev, i + 1);
751 if (irq < 0)
752 return irq;
753
754 err = devm_request_irq(dev, irq, airoha_npu_wdt_handler,
755 IRQF_SHARED, "airoha-npu-wdt", core);
756 if (err)
757 return err;
758
759 INIT_WORK(&core->wdt_work, airoha_npu_wdt_work);
760 }
761
762 /* wlan IRQ lines */
763 for (i = 0; i < ARRAY_SIZE(npu->irqs); i++) {
764 irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1);
765 if (irq < 0)
766 return irq;
767
768 npu->irqs[i] = irq;
769 }
770
771 err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
772 if (err)
773 return err;
774
775 err = airoha_npu_run_firmware(dev, base, &res);
776 if (err)
777 return err;
778
779 regmap_write(npu->regmap, REG_CR_NPU_MIB(10),
780 res.start + NPU_EN7581_FIRMWARE_RV32_MAX_SIZE);
781 regmap_write(npu->regmap, REG_CR_NPU_MIB(11), 0x40000); /* SRAM 256K */
782 regmap_write(npu->regmap, REG_CR_NPU_MIB(12), 0);
783 regmap_write(npu->regmap, REG_CR_NPU_MIB(21), 1);
784 msleep(100);
785
786 /* setting booting address */
787 for (i = 0; i < NPU_NUM_CORES; i++)
788 regmap_write(npu->regmap, REG_CR_BOOT_BASE(i), res.start);
789 usleep_range(1000, 2000);
790
791 /* enable NPU cores */
792 regmap_write(npu->regmap, REG_CR_BOOT_CONFIG, 0xff);
793 regmap_write(npu->regmap, REG_CR_BOOT_TRIGGER, 0x1);
794 msleep(100);
795
796 if (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION,
797 &val, sizeof(val), GFP_KERNEL))
798 dev_info(dev, "NPU fw version: %0d.%d\n",
799 (val >> 16) & 0xffff, val & 0xffff);
800
801 platform_set_drvdata(pdev, npu);
802
803 return 0;
804 }
805
airoha_npu_remove(struct platform_device * pdev)806 static void airoha_npu_remove(struct platform_device *pdev)
807 {
808 struct airoha_npu *npu = platform_get_drvdata(pdev);
809 int i;
810
811 for (i = 0; i < ARRAY_SIZE(npu->cores); i++)
812 cancel_work_sync(&npu->cores[i].wdt_work);
813 }
814
815 static struct platform_driver airoha_npu_driver = {
816 .probe = airoha_npu_probe,
817 .remove = airoha_npu_remove,
818 .driver = {
819 .name = "airoha-npu",
820 .of_match_table = of_airoha_npu_match,
821 },
822 };
823 module_platform_driver(airoha_npu_driver);
824
825 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA);
826 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32);
827 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_DATA);
828 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_RV32);
829 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_DATA);
830 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_RV32);
831 MODULE_LICENSE("GPL v2");
832 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
833 MODULE_DESCRIPTION("Airoha Network Processor Unit driver");
834