1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright(c) 2015 EZchip Technologies.
4 */
5
6 #include <linux/module.h>
7 #include <linux/etherdevice.h>
8 #include <linux/interrupt.h>
9 #include <linux/of_net.h>
10 #include <linux/platform_device.h>
11 #include "nps_enet.h"
12
13 #define DRV_NAME "nps_mgt_enet"
14
nps_enet_is_tx_pending(struct nps_enet_priv * priv)15 static inline bool nps_enet_is_tx_pending(struct nps_enet_priv *priv)
16 {
17 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
18 u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
19
20 return (!tx_ctrl_ct && priv->tx_skb);
21 }
22
nps_enet_clean_rx_fifo(struct net_device * ndev,u32 frame_len)23 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
24 {
25 struct nps_enet_priv *priv = netdev_priv(ndev);
26 u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
27
28 /* Empty Rx FIFO buffer by reading all words */
29 for (i = 0; i < len; i++)
30 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
31 }
32
nps_enet_read_rx_fifo(struct net_device * ndev,unsigned char * dst,u32 length)33 static void nps_enet_read_rx_fifo(struct net_device *ndev,
34 unsigned char *dst, u32 length)
35 {
36 struct nps_enet_priv *priv = netdev_priv(ndev);
37 s32 i, last = length & (sizeof(u32) - 1);
38 u32 *reg = (u32 *)dst, len = length / sizeof(u32);
39 bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
40
41 /* In case dst is not aligned we need an intermediate buffer */
42 if (dst_is_aligned) {
43 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
44 reg += len;
45 } else { /* !dst_is_aligned */
46 for (i = 0; i < len; i++, reg++) {
47 u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
48
49 put_unaligned_be32(buf, reg);
50 }
51 }
52 /* copy last bytes (if any) */
53 if (last) {
54 u32 buf;
55
56 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
57 memcpy((u8 *)reg, &buf, last);
58 }
59 }
60
nps_enet_rx_handler(struct net_device * ndev)61 static u32 nps_enet_rx_handler(struct net_device *ndev)
62 {
63 u32 frame_len, err = 0;
64 u32 work_done = 0;
65 struct nps_enet_priv *priv = netdev_priv(ndev);
66 struct sk_buff *skb;
67 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
68 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
69 u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
70 u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
71
72 frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
73
74 /* Check if we got RX */
75 if (!rx_ctrl_cr)
76 return work_done;
77
78 /* If we got here there is a work for us */
79 work_done++;
80
81 /* Check Rx error */
82 if (rx_ctrl_er) {
83 ndev->stats.rx_errors++;
84 err = 1;
85 }
86
87 /* Check Rx CRC error */
88 if (rx_ctrl_crc) {
89 ndev->stats.rx_crc_errors++;
90 ndev->stats.rx_dropped++;
91 err = 1;
92 }
93
94 /* Check Frame length Min 64b */
95 if (unlikely(frame_len < ETH_ZLEN)) {
96 ndev->stats.rx_length_errors++;
97 ndev->stats.rx_dropped++;
98 err = 1;
99 }
100
101 if (err)
102 goto rx_irq_clean;
103
104 /* Skb allocation */
105 skb = netdev_alloc_skb_ip_align(ndev, frame_len);
106 if (unlikely(!skb)) {
107 ndev->stats.rx_errors++;
108 ndev->stats.rx_dropped++;
109 goto rx_irq_clean;
110 }
111
112 /* Copy frame from Rx fifo into the skb */
113 nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
114
115 skb_put(skb, frame_len);
116 skb->protocol = eth_type_trans(skb, ndev);
117 skb->ip_summed = CHECKSUM_UNNECESSARY;
118
119 ndev->stats.rx_packets++;
120 ndev->stats.rx_bytes += frame_len;
121 netif_receive_skb(skb);
122
123 goto rx_irq_frame_done;
124
125 rx_irq_clean:
126 /* Clean Rx fifo */
127 nps_enet_clean_rx_fifo(ndev, frame_len);
128
129 rx_irq_frame_done:
130 /* Ack Rx ctrl register */
131 nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
132
133 return work_done;
134 }
135
nps_enet_tx_handler(struct net_device * ndev)136 static void nps_enet_tx_handler(struct net_device *ndev)
137 {
138 struct nps_enet_priv *priv = netdev_priv(ndev);
139 u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
140 u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
141 u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
142
143 /* Check if we got TX */
144 if (!nps_enet_is_tx_pending(priv))
145 return;
146
147 /* Ack Tx ctrl register */
148 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
149
150 /* Check Tx transmit error */
151 if (unlikely(tx_ctrl_et)) {
152 ndev->stats.tx_errors++;
153 } else {
154 ndev->stats.tx_packets++;
155 ndev->stats.tx_bytes += tx_ctrl_nt;
156 }
157
158 dev_kfree_skb(priv->tx_skb);
159 priv->tx_skb = NULL;
160
161 if (netif_queue_stopped(ndev))
162 netif_wake_queue(ndev);
163 }
164
165 /**
166 * nps_enet_poll - NAPI poll handler.
167 * @napi: Pointer to napi_struct structure.
168 * @budget: How many frames to process on one call.
169 *
170 * returns: Number of processed frames
171 */
nps_enet_poll(struct napi_struct * napi,int budget)172 static int nps_enet_poll(struct napi_struct *napi, int budget)
173 {
174 struct net_device *ndev = napi->dev;
175 struct nps_enet_priv *priv = netdev_priv(ndev);
176 u32 work_done;
177
178 nps_enet_tx_handler(ndev);
179 work_done = nps_enet_rx_handler(ndev);
180 if ((work_done < budget) && napi_complete_done(napi, work_done)) {
181 u32 buf_int_enable_value = 0;
182
183 /* set tx_done and rx_rdy bits */
184 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
185 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
186
187 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
188 buf_int_enable_value);
189
190 /* in case we will get a tx interrupt while interrupts
191 * are masked, we will lose it since the tx is edge interrupt.
192 * specifically, while executing the code section above,
193 * between nps_enet_tx_handler and the interrupts enable, all
194 * tx requests will be stuck until we will get an rx interrupt.
195 * the two code lines below will solve this situation by
196 * re-adding ourselves to the poll list.
197 */
198 if (nps_enet_is_tx_pending(priv)) {
199 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
200 napi_schedule(napi);
201 }
202 }
203
204 return work_done;
205 }
206
207 /**
208 * nps_enet_irq_handler - Global interrupt handler for ENET.
209 * @irq: irq number.
210 * @dev_instance: device instance.
211 *
212 * returns: IRQ_HANDLED for all cases.
213 *
214 * EZchip ENET has 2 interrupt causes, and depending on bits raised in
215 * CTRL registers we may tell what is a reason for interrupt to fire up.
216 * We got one for RX and the other for TX (completion).
217 */
nps_enet_irq_handler(s32 irq,void * dev_instance)218 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
219 {
220 struct net_device *ndev = dev_instance;
221 struct nps_enet_priv *priv = netdev_priv(ndev);
222 u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
223 u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
224
225 if (nps_enet_is_tx_pending(priv) || rx_ctrl_cr)
226 if (likely(napi_schedule_prep(&priv->napi))) {
227 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
228 __napi_schedule(&priv->napi);
229 }
230
231 return IRQ_HANDLED;
232 }
233
nps_enet_set_hw_mac_address(struct net_device * ndev)234 static void nps_enet_set_hw_mac_address(struct net_device *ndev)
235 {
236 struct nps_enet_priv *priv = netdev_priv(ndev);
237 u32 ge_mac_cfg_1_value = 0;
238 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
239
240 /* set MAC address in HW */
241 ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
242 ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
243 ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
244 ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
245 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
246 | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
247 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
248 | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
249
250 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
251 ge_mac_cfg_1_value);
252
253 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
254 *ge_mac_cfg_2_value);
255 }
256
257 /**
258 * nps_enet_hw_reset - Reset the network device.
259 * @ndev: Pointer to the network device.
260 *
261 * This function reset the PCS and TX fifo.
262 * The programming model is to set the relevant reset bits
263 * wait for some time for this to propagate and then unset
264 * the reset bits. This way we ensure that reset procedure
265 * is done successfully by device.
266 */
nps_enet_hw_reset(struct net_device * ndev)267 static void nps_enet_hw_reset(struct net_device *ndev)
268 {
269 struct nps_enet_priv *priv = netdev_priv(ndev);
270 u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
271
272 /* Pcs reset sequence*/
273 ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
274 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
275 usleep_range(10, 20);
276 ge_rst_value = 0;
277 nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
278
279 /* Tx fifo reset sequence */
280 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
281 phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
282 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
283 phase_fifo_ctl_value);
284 usleep_range(10, 20);
285 phase_fifo_ctl_value = 0;
286 nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
287 phase_fifo_ctl_value);
288 }
289
nps_enet_hw_enable_control(struct net_device * ndev)290 static void nps_enet_hw_enable_control(struct net_device *ndev)
291 {
292 struct nps_enet_priv *priv = netdev_priv(ndev);
293 u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
294 u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
295 u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
296 s32 max_frame_length;
297
298 /* Enable Rx and Tx statistics */
299 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
300 | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
301
302 /* Discard packets with different MAC address */
303 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
304 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
305
306 /* Discard multicast packets */
307 *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
308 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
309
310 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
311 *ge_mac_cfg_2_value);
312
313 /* Discard Packets bigger than max frame length */
314 max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
315 if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
316 *ge_mac_cfg_3_value =
317 (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
318 | max_frame_length << CFG_3_MAX_LEN_SHIFT;
319 }
320
321 /* Enable interrupts */
322 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
323 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
324 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
325 buf_int_enable_value);
326
327 /* Write device MAC address to HW */
328 nps_enet_set_hw_mac_address(ndev);
329
330 /* Rx and Tx HW features */
331 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
332 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
333 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
334
335 /* IFG configuration */
336 ge_mac_cfg_0_value |=
337 NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
338 ge_mac_cfg_0_value |=
339 NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
340
341 /* preamble configuration */
342 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
343 ge_mac_cfg_0_value |=
344 NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
345
346 /* enable flow control frames */
347 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
348 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
349 ge_mac_cfg_0_value |=
350 NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
351 *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
352 | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
353
354 /* Enable Rx and Tx */
355 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
356 ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
357
358 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
359 *ge_mac_cfg_3_value);
360 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
361 ge_mac_cfg_0_value);
362 }
363
nps_enet_hw_disable_control(struct net_device * ndev)364 static void nps_enet_hw_disable_control(struct net_device *ndev)
365 {
366 struct nps_enet_priv *priv = netdev_priv(ndev);
367
368 /* Disable interrupts */
369 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
370
371 /* Disable Rx and Tx */
372 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
373 }
374
nps_enet_send_frame(struct net_device * ndev,struct sk_buff * skb)375 static void nps_enet_send_frame(struct net_device *ndev,
376 struct sk_buff *skb)
377 {
378 struct nps_enet_priv *priv = netdev_priv(ndev);
379 u32 tx_ctrl_value = 0;
380 short length = skb->len;
381 u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
382 u32 *src = (void *)skb->data;
383 bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
384
385 /* In case src is not aligned we need an intermediate buffer */
386 if (src_is_aligned)
387 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
388 else /* !src_is_aligned */
389 for (i = 0; i < len; i++, src++)
390 nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
391 get_unaligned_be32(src));
392
393 /* Write the length of the Frame */
394 tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
395
396 tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
397 /* Send Frame */
398 nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
399 }
400
401 /**
402 * nps_enet_set_mac_address - Set the MAC address for this device.
403 * @ndev: Pointer to net_device structure.
404 * @p: 6 byte Address to be written as MAC address.
405 *
406 * This function copies the HW address from the sockaddr structure to the
407 * net_device structure and updates the address in HW.
408 *
409 * returns: -EBUSY if the net device is busy or 0 if the address is set
410 * successfully.
411 */
nps_enet_set_mac_address(struct net_device * ndev,void * p)412 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
413 {
414 struct sockaddr *addr = p;
415 s32 res;
416
417 if (netif_running(ndev))
418 return -EBUSY;
419
420 res = eth_mac_addr(ndev, p);
421 if (!res) {
422 eth_hw_addr_set(ndev, addr->sa_data);
423 nps_enet_set_hw_mac_address(ndev);
424 }
425
426 return res;
427 }
428
429 /**
430 * nps_enet_set_rx_mode - Change the receive filtering mode.
431 * @ndev: Pointer to the network device.
432 *
433 * This function enables/disables promiscuous mode
434 */
nps_enet_set_rx_mode(struct net_device * ndev)435 static void nps_enet_set_rx_mode(struct net_device *ndev)
436 {
437 struct nps_enet_priv *priv = netdev_priv(ndev);
438 u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
439
440 if (ndev->flags & IFF_PROMISC) {
441 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
442 | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
443 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
444 | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
445
446 } else {
447 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
448 | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
449 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
450 | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
451 }
452
453 nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
454 }
455
456 /**
457 * nps_enet_open - Open the network device.
458 * @ndev: Pointer to the network device.
459 *
460 * returns: 0, on success or non-zero error value on failure.
461 *
462 * This function sets the MAC address, requests and enables an IRQ
463 * for the ENET device and starts the Tx queue.
464 */
nps_enet_open(struct net_device * ndev)465 static s32 nps_enet_open(struct net_device *ndev)
466 {
467 struct nps_enet_priv *priv = netdev_priv(ndev);
468 s32 err;
469
470 /* Reset private variables */
471 priv->tx_skb = NULL;
472 priv->ge_mac_cfg_2_value = 0;
473 priv->ge_mac_cfg_3_value = 0;
474
475 /* ge_mac_cfg_3 default values */
476 priv->ge_mac_cfg_3_value |=
477 NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
478
479 priv->ge_mac_cfg_3_value |=
480 NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
481
482 /* Disable HW device */
483 nps_enet_hw_disable_control(ndev);
484
485 /* irq Rx allocation */
486 err = request_irq(priv->irq, nps_enet_irq_handler,
487 0, "enet-rx-tx", ndev);
488 if (err)
489 return err;
490
491 napi_enable(&priv->napi);
492
493 /* Enable HW device */
494 nps_enet_hw_reset(ndev);
495 nps_enet_hw_enable_control(ndev);
496
497 netif_start_queue(ndev);
498
499 return 0;
500 }
501
502 /**
503 * nps_enet_stop - Close the network device.
504 * @ndev: Pointer to the network device.
505 *
506 * This function stops the Tx queue, disables interrupts for the ENET device.
507 */
nps_enet_stop(struct net_device * ndev)508 static s32 nps_enet_stop(struct net_device *ndev)
509 {
510 struct nps_enet_priv *priv = netdev_priv(ndev);
511
512 napi_disable(&priv->napi);
513 netif_stop_queue(ndev);
514 nps_enet_hw_disable_control(ndev);
515 free_irq(priv->irq, ndev);
516
517 return 0;
518 }
519
520 /**
521 * nps_enet_start_xmit - Starts the data transmission.
522 * @skb: sk_buff pointer that contains data to be Transmitted.
523 * @ndev: Pointer to net_device structure.
524 *
525 * returns: NETDEV_TX_OK, on success
526 * NETDEV_TX_BUSY, if any of the descriptors are not free.
527 *
528 * This function is invoked from upper layers to initiate transmission.
529 */
nps_enet_start_xmit(struct sk_buff * skb,struct net_device * ndev)530 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
531 struct net_device *ndev)
532 {
533 struct nps_enet_priv *priv = netdev_priv(ndev);
534
535 /* This driver handles one frame at a time */
536 netif_stop_queue(ndev);
537
538 priv->tx_skb = skb;
539
540 /* make sure tx_skb is actually written to the memory
541 * before the HW is informed and the IRQ is fired.
542 */
543 wmb();
544
545 nps_enet_send_frame(ndev, skb);
546
547 return NETDEV_TX_OK;
548 }
549
550 #ifdef CONFIG_NET_POLL_CONTROLLER
nps_enet_poll_controller(struct net_device * ndev)551 static void nps_enet_poll_controller(struct net_device *ndev)
552 {
553 disable_irq(ndev->irq);
554 nps_enet_irq_handler(ndev->irq, ndev);
555 enable_irq(ndev->irq);
556 }
557 #endif
558
559 static const struct net_device_ops nps_netdev_ops = {
560 .ndo_open = nps_enet_open,
561 .ndo_stop = nps_enet_stop,
562 .ndo_start_xmit = nps_enet_start_xmit,
563 .ndo_set_mac_address = nps_enet_set_mac_address,
564 .ndo_set_rx_mode = nps_enet_set_rx_mode,
565 #ifdef CONFIG_NET_POLL_CONTROLLER
566 .ndo_poll_controller = nps_enet_poll_controller,
567 #endif
568 };
569
nps_enet_probe(struct platform_device * pdev)570 static s32 nps_enet_probe(struct platform_device *pdev)
571 {
572 struct device *dev = &pdev->dev;
573 struct net_device *ndev;
574 struct nps_enet_priv *priv;
575 s32 err = 0;
576
577 if (!dev->of_node)
578 return -ENODEV;
579
580 ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
581 if (!ndev)
582 return -ENOMEM;
583
584 platform_set_drvdata(pdev, ndev);
585 SET_NETDEV_DEV(ndev, dev);
586 priv = netdev_priv(ndev);
587
588 /* The EZ NET specific entries in the device structure. */
589 ndev->netdev_ops = &nps_netdev_ops;
590 ndev->watchdog_timeo = (400 * HZ / 1000);
591 /* FIXME :: no multicast support yet */
592 ndev->flags &= ~IFF_MULTICAST;
593
594 priv->regs_base = devm_platform_ioremap_resource(pdev, 0);
595 if (IS_ERR(priv->regs_base)) {
596 err = PTR_ERR(priv->regs_base);
597 goto out_netdev;
598 }
599 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
600
601 /* set kernel MAC address to dev */
602 err = of_get_ethdev_address(dev->of_node, ndev);
603 if (err)
604 eth_hw_addr_random(ndev);
605
606 /* Get IRQ number */
607 priv->irq = platform_get_irq(pdev, 0);
608 if (priv->irq < 0) {
609 err = -ENODEV;
610 goto out_netdev;
611 }
612
613 netif_napi_add_weight(ndev, &priv->napi, nps_enet_poll,
614 NPS_ENET_NAPI_POLL_WEIGHT);
615
616 /* Register the driver. Should be the last thing in probe */
617 err = register_netdev(ndev);
618 if (err) {
619 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
620 ndev->name, (s32)err);
621 goto out_netif_api;
622 }
623
624 dev_info(dev, "(rx/tx=%d)\n", priv->irq);
625 return 0;
626
627 out_netif_api:
628 netif_napi_del(&priv->napi);
629 out_netdev:
630 free_netdev(ndev);
631
632 return err;
633 }
634
nps_enet_remove(struct platform_device * pdev)635 static void nps_enet_remove(struct platform_device *pdev)
636 {
637 struct net_device *ndev = platform_get_drvdata(pdev);
638 struct nps_enet_priv *priv = netdev_priv(ndev);
639
640 unregister_netdev(ndev);
641 netif_napi_del(&priv->napi);
642 free_netdev(ndev);
643 }
644
645 static const struct of_device_id nps_enet_dt_ids[] = {
646 { .compatible = "ezchip,nps-mgt-enet" },
647 { /* Sentinel */ }
648 };
649 MODULE_DEVICE_TABLE(of, nps_enet_dt_ids);
650
651 static struct platform_driver nps_enet_driver = {
652 .probe = nps_enet_probe,
653 .remove = nps_enet_remove,
654 .driver = {
655 .name = DRV_NAME,
656 .of_match_table = nps_enet_dt_ids,
657 },
658 };
659
660 module_platform_driver(nps_enet_driver);
661
662 MODULE_AUTHOR("EZchip Semiconductor");
663 MODULE_DESCRIPTION("EZchip NPS Ethernet driver");
664 MODULE_LICENSE("GPL v2");
665