1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/bitfield.h> 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/io.h> 19 #include <linux/lockdep.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/property.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 28 #include <asm/byteorder.h> 29 30 #include <linux/serial_8250.h> 31 #include <linux/serial_reg.h> 32 33 #include "8250_dwlib.h" 34 35 #define OCTEON_UART_USR 0x27 /* UART Status Register */ 36 37 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ 38 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ 39 40 /* Renesas specific register fields */ 41 #define RZN1_UART_xDMACR_DMA_EN BIT(0) 42 #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) 43 #define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1) 44 #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) 45 #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) 46 47 /* Quirks */ 48 #define DW_UART_QUIRK_OCTEON BIT(0) 49 #define DW_UART_QUIRK_ARMADA_38X BIT(1) 50 #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2) 51 #define DW_UART_QUIRK_IS_DMA_FC BIT(3) 52 #define DW_UART_QUIRK_APMC0D08 BIT(4) 53 #define DW_UART_QUIRK_CPR_VALUE BIT(5) 54 #define DW_UART_QUIRK_IER_KICK BIT(6) 55 56 /* 57 * Number of consecutive IIR_NO_INT interrupts required to trigger interrupt 58 * storm prevention code. 59 */ 60 #define DW_UART_QUIRK_IER_KICK_THRES 4 61 62 struct dw8250_platform_data { 63 u8 usr_reg; 64 u32 cpr_value; 65 unsigned int quirks; 66 }; 67 68 struct dw8250_data { 69 struct dw8250_port_data data; 70 const struct dw8250_platform_data *pdata; 71 72 u32 msr_mask_on; 73 u32 msr_mask_off; 74 struct clk *clk; 75 struct clk *pclk; 76 struct reset_control *rst; 77 78 unsigned int skip_autocfg:1; 79 unsigned int uart_16550_compatible:1; 80 unsigned int in_idle:1; 81 82 u8 no_int_count; 83 }; 84 85 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 86 { 87 return container_of(data, struct dw8250_data, data); 88 } 89 90 static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value) 91 { 92 struct dw8250_data *d = to_dw8250_data(p->private_data); 93 94 /* Override any modem control signals if needed */ 95 if (offset == UART_MSR) { 96 value |= d->msr_mask_on; 97 value &= ~d->msr_mask_off; 98 } 99 100 return value; 101 } 102 103 static void dw8250_idle_exit(struct uart_port *p) 104 { 105 struct dw8250_data *d = to_dw8250_data(p->private_data); 106 struct uart_8250_port *up = up_to_u8250p(p); 107 108 if (d->uart_16550_compatible) 109 return; 110 111 if (up->capabilities & UART_CAP_FIFO) 112 serial_port_out(p, UART_FCR, up->fcr); 113 serial_port_out(p, UART_MCR, up->mcr); 114 serial_port_out(p, UART_IER, up->ier); 115 116 /* DMA Rx is restarted by IRQ handler as needed. */ 117 if (up->dma) 118 serial8250_tx_dma_resume(up); 119 120 d->in_idle = 0; 121 } 122 123 /* 124 * Ensure BUSY is not asserted. If DW UART is configured with 125 * !uart_16550_compatible, the writes to LCR, DLL, and DLH fail while 126 * BUSY is asserted. 127 * 128 * Context: port's lock must be held 129 */ 130 static int dw8250_idle_enter(struct uart_port *p) 131 { 132 struct dw8250_data *d = to_dw8250_data(p->private_data); 133 unsigned int usr_reg = d->pdata ? d->pdata->usr_reg : DW_UART_USR; 134 struct uart_8250_port *up = up_to_u8250p(p); 135 int retries; 136 u32 lsr; 137 138 lockdep_assert_held_once(&p->lock); 139 140 if (d->uart_16550_compatible) 141 return 0; 142 143 d->in_idle = 1; 144 145 /* Prevent triggering interrupt from RBR filling */ 146 serial_port_out(p, UART_IER, 0); 147 148 if (up->dma) { 149 serial8250_rx_dma_flush(up); 150 if (serial8250_tx_dma_running(up)) 151 serial8250_tx_dma_pause(up); 152 } 153 154 /* 155 * Wait until Tx becomes empty + one extra frame time to ensure all bits 156 * have been sent on the wire. 157 * 158 * FIXME: frame_time delay is too long with very low baudrates. 159 */ 160 serial8250_fifo_wait_for_lsr_thre(up, p->fifosize); 161 ndelay(p->frame_time); 162 163 serial_port_out(p, UART_MCR, up->mcr | UART_MCR_LOOP); 164 165 retries = 4; /* Arbitrary limit, 2 was always enough in tests */ 166 do { 167 serial8250_clear_fifos(up); 168 if (!(serial_port_in(p, usr_reg) & DW_UART_USR_BUSY)) 169 break; 170 /* FIXME: frame_time delay is too long with very low baudrates. */ 171 ndelay(p->frame_time); 172 } while (--retries); 173 174 lsr = serial_lsr_in(up); 175 if (lsr & UART_LSR_DR) { 176 serial_port_in(p, UART_RX); 177 up->lsr_saved_flags = 0; 178 } 179 180 /* Now guaranteed to have BUSY deasserted? Just sanity check */ 181 if (serial_port_in(p, usr_reg) & DW_UART_USR_BUSY) { 182 dw8250_idle_exit(p); 183 return -EBUSY; 184 } 185 186 return 0; 187 } 188 189 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, 190 unsigned int quot, unsigned int quot_frac) 191 { 192 struct uart_8250_port *up = up_to_u8250p(p); 193 int ret; 194 195 ret = dw8250_idle_enter(p); 196 if (ret < 0) 197 return; 198 199 serial_port_out(p, UART_LCR, up->lcr | UART_LCR_DLAB); 200 if (!(serial_port_in(p, UART_LCR) & UART_LCR_DLAB)) 201 goto idle_failed; 202 203 serial_dl_write(up, quot); 204 serial_port_out(p, UART_LCR, up->lcr); 205 206 idle_failed: 207 dw8250_idle_exit(p); 208 } 209 210 /* 211 * This function is being called as part of the uart_port::serial_out() 212 * routine. Hence, special care must be taken when serial_port_out() or 213 * serial_out() against the modified registers here, i.e. LCR (d->in_idle is 214 * used to break recursion loop). 215 */ 216 static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value) 217 { 218 struct dw8250_data *d = to_dw8250_data(p->private_data); 219 u32 lcr; 220 int ret; 221 222 if (offset != UART_LCR || d->uart_16550_compatible) 223 return; 224 225 lcr = serial_port_in(p, UART_LCR); 226 227 /* Make sure LCR write wasn't ignored */ 228 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 229 return; 230 231 if (d->in_idle) 232 goto write_err; 233 234 ret = dw8250_idle_enter(p); 235 if (ret < 0) 236 goto write_err; 237 238 serial_port_out(p, UART_LCR, value); 239 dw8250_idle_exit(p); 240 return; 241 242 write_err: 243 /* 244 * FIXME: this deadlocks if port->lock is already held 245 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 246 */ 247 return; /* Silences "label at the end of compound statement" */ 248 } 249 250 /* 251 * With BUSY, LCR writes can be very expensive (IRQ + complex retry logic). 252 * If the write does not change the value of the LCR register, skip it entirely. 253 */ 254 static bool dw8250_can_skip_reg_write(struct uart_port *p, unsigned int offset, u32 value) 255 { 256 struct dw8250_data *d = to_dw8250_data(p->private_data); 257 u32 lcr; 258 259 if (offset != UART_LCR || d->uart_16550_compatible) 260 return false; 261 262 lcr = serial_port_in(p, offset); 263 return lcr == value; 264 } 265 266 /* Returns once the transmitter is empty or we run out of retries */ 267 static void dw8250_tx_wait_empty(struct uart_port *p) 268 { 269 struct uart_8250_port *up = up_to_u8250p(p); 270 unsigned int tries = 20000; 271 unsigned int delay_threshold = tries - 1000; 272 unsigned int lsr; 273 274 while (tries--) { 275 lsr = readb (p->membase + (UART_LSR << p->regshift)); 276 up->lsr_saved_flags |= lsr & up->lsr_save_mask; 277 278 if (lsr & UART_LSR_TEMT) 279 break; 280 281 /* The device is first given a chance to empty without delay, 282 * to avoid slowdowns at high bitrates. If after 1000 tries 283 * the buffer has still not emptied, allow more time for low- 284 * speed links. */ 285 if (tries < delay_threshold) 286 udelay (1); 287 } 288 } 289 290 static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value) 291 { 292 if (dw8250_can_skip_reg_write(p, offset, value)) 293 return; 294 295 writeb(value, p->membase + (offset << p->regshift)); 296 dw8250_check_lcr(p, offset, value); 297 } 298 299 static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value) 300 { 301 if (dw8250_can_skip_reg_write(p, offset, value)) 302 return; 303 304 /* Allow the TX to drain before we reconfigure */ 305 if (offset == UART_LCR) 306 dw8250_tx_wait_empty(p); 307 308 dw8250_serial_out(p, offset, value); 309 } 310 311 static u32 dw8250_serial_in(struct uart_port *p, unsigned int offset) 312 { 313 u32 value = readb(p->membase + (offset << p->regshift)); 314 315 return dw8250_modify_msr(p, offset, value); 316 } 317 318 #ifdef CONFIG_64BIT 319 static u32 dw8250_serial_inq(struct uart_port *p, unsigned int offset) 320 { 321 u8 value = __raw_readq(p->membase + (offset << p->regshift)); 322 323 return dw8250_modify_msr(p, offset, value); 324 } 325 326 static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value) 327 { 328 if (dw8250_can_skip_reg_write(p, offset, value)) 329 return; 330 331 value &= 0xff; 332 __raw_writeq(value, p->membase + (offset << p->regshift)); 333 /* Read back to ensure register write ordering. */ 334 __raw_readq(p->membase + (UART_LCR << p->regshift)); 335 336 dw8250_check_lcr(p, offset, value); 337 } 338 #endif /* CONFIG_64BIT */ 339 340 static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value) 341 { 342 if (dw8250_can_skip_reg_write(p, offset, value)) 343 return; 344 345 writel(value, p->membase + (offset << p->regshift)); 346 dw8250_check_lcr(p, offset, value); 347 } 348 349 static u32 dw8250_serial_in32(struct uart_port *p, unsigned int offset) 350 { 351 u32 value = readl(p->membase + (offset << p->regshift)); 352 353 return dw8250_modify_msr(p, offset, value); 354 } 355 356 static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value) 357 { 358 if (dw8250_can_skip_reg_write(p, offset, value)) 359 return; 360 361 iowrite32be(value, p->membase + (offset << p->regshift)); 362 dw8250_check_lcr(p, offset, value); 363 } 364 365 static u32 dw8250_serial_in32be(struct uart_port *p, unsigned int offset) 366 { 367 u32 value = ioread32be(p->membase + (offset << p->regshift)); 368 369 return dw8250_modify_msr(p, offset, value); 370 } 371 372 /* 373 * INTC10EE UART can IRQ storm while reporting IIR_NO_INT. Inducing IIR value 374 * change has been observed to break the storm. 375 * 376 * If Tx is empty (THRE asserted), we use here IER_THRI to cause IIR_NO_INT -> 377 * IIR_THRI transition. 378 */ 379 static void dw8250_quirk_ier_kick(struct uart_port *p) 380 { 381 struct uart_8250_port *up = up_to_u8250p(p); 382 u32 lsr; 383 384 if (up->ier & UART_IER_THRI) 385 return; 386 387 lsr = serial_lsr_in(up); 388 if (!(lsr & UART_LSR_THRE)) 389 return; 390 391 serial_port_out(p, UART_IER, up->ier | UART_IER_THRI); 392 serial_port_in(p, UART_LCR); /* safe, no side-effects */ 393 serial_port_out(p, UART_IER, up->ier); 394 } 395 396 static int dw8250_handle_irq(struct uart_port *p) 397 { 398 struct uart_8250_port *up = up_to_u8250p(p); 399 struct dw8250_data *d = to_dw8250_data(p->private_data); 400 unsigned int iir = serial_port_in(p, UART_IIR); 401 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT; 402 unsigned int quirks = d->pdata->quirks; 403 unsigned int status; 404 405 guard(uart_port_lock_check_sysrq_irqsave)(p); 406 407 switch (FIELD_GET(DW_UART_IIR_IID, iir)) { 408 case UART_IIR_NO_INT: 409 if (d->uart_16550_compatible || up->dma) 410 return 0; 411 412 if (quirks & DW_UART_QUIRK_IER_KICK && 413 d->no_int_count == (DW_UART_QUIRK_IER_KICK_THRES - 1)) 414 dw8250_quirk_ier_kick(p); 415 d->no_int_count = (d->no_int_count + 1) % DW_UART_QUIRK_IER_KICK_THRES; 416 417 return 0; 418 419 case UART_IIR_BUSY: 420 /* Clear the USR */ 421 serial_port_in(p, d->pdata->usr_reg); 422 423 d->no_int_count = 0; 424 425 return 1; 426 } 427 428 d->no_int_count = 0; 429 430 /* 431 * There are ways to get Designware-based UARTs into a state where 432 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 433 * data available. If we see such a case then we'll do a bogus 434 * read. If we don't do this then the "RX TIMEOUT" interrupt will 435 * fire forever. 436 * 437 * This problem has only been observed so far when not in DMA mode 438 * so we limit the workaround only to non-DMA mode. 439 */ 440 if (!up->dma && rx_timeout) { 441 status = serial_lsr_in(up); 442 443 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 444 serial_port_in(p, UART_RX); 445 } 446 447 /* Manually stop the Rx DMA transfer when acting as flow controller */ 448 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { 449 status = serial_lsr_in(up); 450 451 if (status & (UART_LSR_DR | UART_LSR_BI)) { 452 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); 453 dw8250_writel_ext(p, DW_UART_DMASA, 1); 454 } 455 } 456 457 serial8250_handle_irq_locked(p, iir); 458 459 return 1; 460 } 461 462 static void 463 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 464 { 465 if (!state) 466 pm_runtime_get_sync(port->dev); 467 468 serial8250_do_pm(port, state, old); 469 470 if (state) 471 pm_runtime_put_sync_suspend(port->dev); 472 } 473 474 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 475 const struct ktermios *old) 476 { 477 unsigned long newrate = tty_termios_baud_rate(termios) * 16; 478 struct dw8250_data *d = to_dw8250_data(p->private_data); 479 long rate; 480 int ret; 481 482 clk_disable_unprepare(d->clk); 483 rate = clk_round_rate(d->clk, newrate); 484 if (rate > 0) { 485 ret = clk_set_rate(d->clk, newrate); 486 if (!ret) 487 p->uartclk = rate; 488 } 489 clk_prepare_enable(d->clk); 490 491 dw8250_do_set_termios(p, termios, old); 492 } 493 494 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 495 { 496 struct uart_8250_port *up = up_to_u8250p(p); 497 unsigned int mcr = serial_port_in(p, UART_MCR); 498 499 if (up->capabilities & UART_CAP_IRDA) { 500 if (termios->c_line == N_IRDA) 501 mcr |= DW_UART_MCR_SIRE; 502 else 503 mcr &= ~DW_UART_MCR_SIRE; 504 505 serial_port_out(p, UART_MCR, mcr); 506 } 507 serial8250_do_set_ldisc(p, termios); 508 } 509 510 /* 511 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 512 * channel on platforms that have DMA engines, but don't have any channels 513 * assigned to the UART. 514 * 515 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 516 * core problem is fixed, this function is no longer needed. 517 */ 518 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 519 { 520 return false; 521 } 522 523 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 524 { 525 return param == chan->device->dev; 526 } 527 528 static void dw8250_setup_dma_filter(struct uart_port *p, struct dw8250_data *data) 529 { 530 /* Platforms with iDMA 64-bit */ 531 if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) { 532 data->data.dma.rx_param = p->dev->parent; 533 data->data.dma.tx_param = p->dev->parent; 534 data->data.dma.fn = dw8250_idma_filter; 535 } else { 536 data->data.dma.fn = dw8250_fallback_dma_filter; 537 } 538 } 539 540 static u32 dw8250_rzn1_get_dmacr_burst(int max_burst) 541 { 542 if (max_burst >= 8) 543 return RZN1_UART_xDMACR_8_WORD_BURST; 544 else if (max_burst >= 4) 545 return RZN1_UART_xDMACR_4_WORD_BURST; 546 else 547 return RZN1_UART_xDMACR_1_WORD_BURST; 548 } 549 550 static void dw8250_prepare_tx_dma(struct uart_8250_port *p) 551 { 552 struct uart_port *up = &p->port; 553 struct uart_8250_dma *dma = p->dma; 554 u32 val; 555 556 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0); 557 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | 558 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | 559 RZN1_UART_xDMACR_DMA_EN; 560 dw8250_writel_ext(up, RZN1_UART_TDMACR, val); 561 } 562 563 static void dw8250_prepare_rx_dma(struct uart_8250_port *p) 564 { 565 struct uart_port *up = &p->port; 566 struct uart_8250_dma *dma = p->dma; 567 u32 val; 568 569 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0); 570 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | 571 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | 572 RZN1_UART_xDMACR_DMA_EN; 573 dw8250_writel_ext(up, RZN1_UART_RDMACR, val); 574 } 575 576 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 577 { 578 unsigned int quirks = data->pdata->quirks; 579 u32 cpr_value = data->pdata->cpr_value; 580 581 if (quirks & DW_UART_QUIRK_CPR_VALUE) 582 data->data.cpr_value = cpr_value; 583 584 #ifdef CONFIG_64BIT 585 if (quirks & DW_UART_QUIRK_OCTEON) { 586 p->serial_in = dw8250_serial_inq; 587 p->serial_out = dw8250_serial_outq; 588 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 589 p->type = PORT_OCTEON; 590 data->skip_autocfg = true; 591 } 592 #endif 593 594 if (quirks & DW_UART_QUIRK_ARMADA_38X) 595 p->serial_out = dw8250_serial_out38x; 596 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE) 597 p->set_termios = dw8250_do_set_termios; 598 if (quirks & DW_UART_QUIRK_IS_DMA_FC) { 599 data->data.dma.txconf.device_fc = 1; 600 data->data.dma.rxconf.device_fc = 1; 601 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; 602 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; 603 } 604 if (quirks & DW_UART_QUIRK_APMC0D08) { 605 p->iotype = UPIO_MEM32; 606 p->regshift = 2; 607 p->serial_in = dw8250_serial_in32; 608 data->uart_16550_compatible = true; 609 } 610 } 611 612 static void dw8250_reset_control_assert(void *data) 613 { 614 reset_control_assert(data); 615 } 616 617 static void dw8250_shutdown(struct uart_port *port) 618 { 619 struct dw8250_data *d = to_dw8250_data(port->private_data); 620 621 serial8250_do_shutdown(port); 622 d->no_int_count = 0; 623 } 624 625 static int dw8250_probe(struct platform_device *pdev) 626 { 627 struct uart_8250_port uart = {}, *up = &uart; 628 struct uart_port *p = &up->port; 629 struct device *dev = &pdev->dev; 630 struct dw8250_data *data; 631 struct resource *regs; 632 int err; 633 634 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 635 if (!regs) 636 return dev_err_probe(dev, -EINVAL, "no registers defined\n"); 637 638 spin_lock_init(&p->lock); 639 p->pm = dw8250_do_pm; 640 p->type = PORT_8250; 641 p->flags = UPF_FIXED_PORT; 642 p->dev = dev; 643 644 p->set_ldisc = dw8250_set_ldisc; 645 p->set_termios = dw8250_set_termios; 646 p->set_divisor = dw8250_set_divisor; 647 648 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 649 if (!data) 650 return -ENOMEM; 651 652 p->private_data = &data->data; 653 654 p->mapbase = regs->start; 655 p->mapsize = resource_size(regs); 656 657 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize); 658 if (!p->membase) 659 return -ENOMEM; 660 661 err = uart_read_port_properties(p); 662 /* no interrupt -> fall back to polling */ 663 if (err == -ENXIO) 664 err = 0; 665 if (err) 666 return err; 667 668 switch (p->iotype) { 669 case UPIO_MEM: 670 p->serial_in = dw8250_serial_in; 671 p->serial_out = dw8250_serial_out; 672 break; 673 case UPIO_MEM32: 674 p->serial_in = dw8250_serial_in32; 675 p->serial_out = dw8250_serial_out32; 676 break; 677 case UPIO_MEM32BE: 678 p->serial_in = dw8250_serial_in32be; 679 p->serial_out = dw8250_serial_out32be; 680 break; 681 default: 682 return -ENODEV; 683 } 684 685 if (device_property_read_bool(dev, "dcd-override")) { 686 /* Always report DCD as active */ 687 data->msr_mask_on |= UART_MSR_DCD; 688 data->msr_mask_off |= UART_MSR_DDCD; 689 } 690 691 if (device_property_read_bool(dev, "dsr-override")) { 692 /* Always report DSR as active */ 693 data->msr_mask_on |= UART_MSR_DSR; 694 data->msr_mask_off |= UART_MSR_DDSR; 695 } 696 697 if (device_property_read_bool(dev, "cts-override")) { 698 /* Always report CTS as active */ 699 data->msr_mask_on |= UART_MSR_CTS; 700 data->msr_mask_off |= UART_MSR_DCTS; 701 } 702 703 if (device_property_read_bool(dev, "ri-override")) { 704 /* Always report Ring indicator as inactive */ 705 data->msr_mask_off |= UART_MSR_RI; 706 data->msr_mask_off |= UART_MSR_TERI; 707 } 708 709 /* If there is separate baudclk, get the rate from it. */ 710 data->clk = devm_clk_get_optional_enabled(dev, "baudclk"); 711 if (data->clk == NULL) 712 data->clk = devm_clk_get_optional_enabled(dev, NULL); 713 if (IS_ERR(data->clk)) 714 return dev_err_probe(dev, PTR_ERR(data->clk), 715 "failed to get baudclk\n"); 716 717 if (data->clk) 718 p->uartclk = clk_get_rate(data->clk); 719 720 /* If no clock rate is defined, fail. */ 721 if (!p->uartclk) 722 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); 723 724 data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk"); 725 if (IS_ERR(data->pclk)) 726 return PTR_ERR(data->pclk); 727 728 data->rst = devm_reset_control_array_get_optional_exclusive(dev); 729 if (IS_ERR(data->rst)) 730 return PTR_ERR(data->rst); 731 732 err = reset_control_deassert(data->rst); 733 if (err) 734 return dev_err_probe(dev, err, "failed to deassert resets\n"); 735 736 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); 737 if (err) 738 return err; 739 740 err = pm_runtime_set_active(dev); 741 if (err) 742 return dev_err_probe(dev, err, "Failed to set the runtime suspend as active\n"); 743 744 data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible"); 745 746 data->pdata = device_get_match_data(p->dev); 747 if (data->pdata) 748 dw8250_quirks(p, data); 749 750 /* If the Busy Functionality is not implemented, don't handle it */ 751 if (data->uart_16550_compatible) { 752 p->handle_irq = NULL; 753 } else if (data->pdata) { 754 p->handle_irq = dw8250_handle_irq; 755 p->shutdown = dw8250_shutdown; 756 } 757 758 dw8250_setup_dma_filter(p, data); 759 760 if (!data->skip_autocfg) 761 dw8250_setup_port(p); 762 763 /* If we have a valid fifosize, try hooking up DMA */ 764 if (p->fifosize) { 765 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 766 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 767 up->dma = &data->data.dma; 768 } 769 770 data->data.line = serial8250_register_8250_port(up); 771 if (data->data.line < 0) 772 return data->data.line; 773 774 platform_set_drvdata(pdev, data); 775 776 pm_runtime_enable(dev); 777 778 return 0; 779 } 780 781 static void dw8250_remove(struct platform_device *pdev) 782 { 783 struct dw8250_data *data = platform_get_drvdata(pdev); 784 struct device *dev = &pdev->dev; 785 786 pm_runtime_get_sync(dev); 787 788 serial8250_unregister_port(data->data.line); 789 790 pm_runtime_disable(dev); 791 pm_runtime_put_noidle(dev); 792 } 793 794 static int dw8250_suspend(struct device *dev) 795 { 796 struct dw8250_data *data = dev_get_drvdata(dev); 797 798 serial8250_suspend_port(data->data.line); 799 800 return 0; 801 } 802 803 static int dw8250_resume(struct device *dev) 804 { 805 struct dw8250_data *data = dev_get_drvdata(dev); 806 807 serial8250_resume_port(data->data.line); 808 809 return 0; 810 } 811 812 static int dw8250_runtime_suspend(struct device *dev) 813 { 814 struct dw8250_data *data = dev_get_drvdata(dev); 815 816 clk_disable_unprepare(data->clk); 817 818 clk_disable_unprepare(data->pclk); 819 820 return 0; 821 } 822 823 static int dw8250_runtime_resume(struct device *dev) 824 { 825 int ret; 826 struct dw8250_data *data = dev_get_drvdata(dev); 827 828 ret = clk_prepare_enable(data->pclk); 829 if (ret) 830 return ret; 831 832 ret = clk_prepare_enable(data->clk); 833 if (ret) { 834 clk_disable_unprepare(data->pclk); 835 return ret; 836 } 837 838 return 0; 839 } 840 841 static _DEFINE_DEV_PM_OPS(dw8250_pm_ops, dw8250_suspend, dw8250_resume, 842 dw8250_runtime_suspend, dw8250_runtime_resume, 843 NULL); 844 845 static const struct dw8250_platform_data dw8250_dw_apb = { 846 .usr_reg = DW_UART_USR, 847 }; 848 849 static const struct dw8250_platform_data dw8250_octeon_3860_data = { 850 .usr_reg = OCTEON_UART_USR, 851 .quirks = DW_UART_QUIRK_OCTEON, 852 }; 853 854 static const struct dw8250_platform_data dw8250_armada_38x_data = { 855 .usr_reg = DW_UART_USR, 856 .quirks = DW_UART_QUIRK_ARMADA_38X, 857 }; 858 859 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { 860 .usr_reg = DW_UART_USR, 861 .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | 862 DW_UART_CPR_AFCE_MODE | 863 DW_UART_CPR_THRE_MODE | 864 DW_UART_CPR_ADDITIONAL_FEATURES | 865 DW_UART_CPR_FIFO_ACCESS | 866 DW_UART_CPR_FIFO_STAT | 867 DW_UART_CPR_SHADOW | 868 DW_UART_CPR_DMA_EXTRA | 869 DW_UART_CPR_FIFO_MODE_FROM_SIZE(16), 870 .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, 871 }; 872 873 static const struct dw8250_platform_data dw8250_skip_set_rate_data = { 874 .usr_reg = DW_UART_USR, 875 .quirks = DW_UART_QUIRK_SKIP_SET_RATE, 876 }; 877 878 static const struct dw8250_platform_data dw8250_intc10ee = { 879 .usr_reg = DW_UART_USR, 880 .quirks = DW_UART_QUIRK_IER_KICK, 881 }; 882 883 static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { 884 .usr_reg = DW_UART_USR, 885 .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | 886 DW_UART_CPR_THRE_MODE | 887 DW_UART_CPR_DMA_EXTRA | 888 DW_UART_CPR_FIFO_MODE_FROM_SIZE(32), 889 .quirks = DW_UART_QUIRK_CPR_VALUE, 890 }; 891 892 static const struct of_device_id dw8250_of_match[] = { 893 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, 894 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, 895 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, 896 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, 897 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, 898 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, 899 { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, 900 { /* Sentinel */ } 901 }; 902 MODULE_DEVICE_TABLE(of, dw8250_of_match); 903 904 static const struct dw8250_platform_data dw8250_apmc0d08 = { 905 .usr_reg = DW_UART_USR, 906 .quirks = DW_UART_QUIRK_APMC0D08, 907 }; 908 909 static const struct acpi_device_id dw8250_acpi_match[] = { 910 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb }, 911 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb }, 912 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb }, 913 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb }, 914 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb }, 915 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 }, 916 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb }, 917 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb }, 918 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb }, 919 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb }, 920 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb }, 921 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb }, 922 { "INTC10EE", (kernel_ulong_t)&dw8250_intc10ee }, 923 { }, 924 }; 925 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 926 927 static struct platform_driver dw8250_platform_driver = { 928 .driver = { 929 .name = "dw-apb-uart", 930 .pm = pm_ptr(&dw8250_pm_ops), 931 .of_match_table = dw8250_of_match, 932 .acpi_match_table = dw8250_acpi_match, 933 }, 934 .probe = dw8250_probe, 935 .remove = dw8250_remove, 936 }; 937 938 module_platform_driver(dw8250_platform_driver); 939 940 MODULE_IMPORT_NS("SERIAL_8250"); 941 MODULE_AUTHOR("Jamie Iles"); 942 MODULE_LICENSE("GPL"); 943 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 944 MODULE_ALIAS("platform:dw-apb-uart"); 945