1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Synopsys DesignWare 8250 driver.
4 *
5 * Copyright 2011 Picochip, Jamie Iles.
6 * Copyright 2013 Intel Corporation
7 *
8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
9 * LCR is written whilst busy. If it is, then a busy detect interrupt is
10 * raised, the LCR needs to be rewritten and the uart status register read.
11 */
12 #include <linux/bitfield.h>
13 #include <linux/bits.h>
14 #include <linux/cleanup.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/io.h>
19 #include <linux/lockdep.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26
27 #include <asm/byteorder.h>
28
29 #include <linux/serial_8250.h>
30 #include <linux/serial_reg.h>
31
32 #include "8250_dwlib.h"
33
34 #define OCTEON_UART_USR 0x27 /* UART Status Register */
35
36 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
37 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
38
39 /* Renesas specific register fields */
40 #define RZN1_UART_xDMACR_DMA_EN BIT(0)
41 #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
42 #define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
43 #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
44 #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
45
46 /* Quirks */
47 #define DW_UART_QUIRK_OCTEON BIT(0)
48 #define DW_UART_QUIRK_ARMADA_38X BIT(1)
49 #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
50 #define DW_UART_QUIRK_IS_DMA_FC BIT(3)
51 #define DW_UART_QUIRK_APMC0D08 BIT(4)
52 #define DW_UART_QUIRK_CPR_VALUE BIT(5)
53 #define DW_UART_QUIRK_IER_KICK BIT(6)
54
55 /*
56 * Number of consecutive IIR_NO_INT interrupts required to trigger interrupt
57 * storm prevention code.
58 */
59 #define DW_UART_QUIRK_IER_KICK_THRES 4
60
61 struct dw8250_platform_data {
62 u8 usr_reg;
63 u32 cpr_value;
64 unsigned int quirks;
65 };
66
67 struct dw8250_data {
68 struct dw8250_port_data data;
69 const struct dw8250_platform_data *pdata;
70
71 u32 msr_mask_on;
72 u32 msr_mask_off;
73 struct clk *clk;
74 struct clk *pclk;
75 struct reset_control *rst;
76
77 unsigned int skip_autocfg:1;
78 unsigned int uart_16550_compatible:1;
79 unsigned int in_idle:1;
80
81 u8 no_int_count;
82 };
83
to_dw8250_data(struct dw8250_port_data * data)84 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
85 {
86 return container_of(data, struct dw8250_data, data);
87 }
88
dw8250_modify_msr(struct uart_port * p,unsigned int offset,u32 value)89 static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value)
90 {
91 struct dw8250_data *d = to_dw8250_data(p->private_data);
92
93 /* Override any modem control signals if needed */
94 if (offset == UART_MSR) {
95 value |= d->msr_mask_on;
96 value &= ~d->msr_mask_off;
97 }
98
99 return value;
100 }
101
dw8250_idle_exit(struct uart_port * p)102 static void dw8250_idle_exit(struct uart_port *p)
103 {
104 struct dw8250_data *d = to_dw8250_data(p->private_data);
105 struct uart_8250_port *up = up_to_u8250p(p);
106
107 if (d->uart_16550_compatible)
108 return;
109
110 if (up->capabilities & UART_CAP_FIFO)
111 serial_port_out(p, UART_FCR, up->fcr);
112 serial_port_out(p, UART_MCR, up->mcr);
113 serial_port_out(p, UART_IER, up->ier);
114
115 /* DMA Rx is restarted by IRQ handler as needed. */
116 if (up->dma)
117 serial8250_tx_dma_resume(up);
118
119 d->in_idle = 0;
120 }
121
122 /*
123 * Ensure BUSY is not asserted. If DW UART is configured with
124 * !uart_16550_compatible, the writes to LCR, DLL, and DLH fail while
125 * BUSY is asserted.
126 *
127 * Context: port's lock must be held
128 */
dw8250_idle_enter(struct uart_port * p)129 static int dw8250_idle_enter(struct uart_port *p)
130 {
131 struct dw8250_data *d = to_dw8250_data(p->private_data);
132 unsigned int usr_reg = d->pdata ? d->pdata->usr_reg : DW_UART_USR;
133 struct uart_8250_port *up = up_to_u8250p(p);
134 int retries;
135 u32 lsr;
136
137 lockdep_assert_held_once(&p->lock);
138
139 if (d->uart_16550_compatible)
140 return 0;
141
142 d->in_idle = 1;
143
144 /* Prevent triggering interrupt from RBR filling */
145 serial_port_out(p, UART_IER, 0);
146
147 if (up->dma) {
148 serial8250_rx_dma_flush(up);
149 if (serial8250_tx_dma_running(up))
150 serial8250_tx_dma_pause(up);
151 }
152
153 /*
154 * Wait until Tx becomes empty + one extra frame time to ensure all bits
155 * have been sent on the wire.
156 *
157 * FIXME: frame_time delay is too long with very low baudrates.
158 */
159 serial8250_fifo_wait_for_lsr_thre(up, p->fifosize);
160 ndelay(p->frame_time);
161
162 serial_port_out(p, UART_MCR, up->mcr | UART_MCR_LOOP);
163
164 retries = 4; /* Arbitrary limit, 2 was always enough in tests */
165 do {
166 serial8250_clear_fifos(up);
167 if (!(serial_port_in(p, usr_reg) & DW_UART_USR_BUSY))
168 break;
169 /* FIXME: frame_time delay is too long with very low baudrates. */
170 ndelay(p->frame_time);
171 } while (--retries);
172
173 lsr = serial_lsr_in(up);
174 if (lsr & UART_LSR_DR) {
175 serial_port_in(p, UART_RX);
176 up->lsr_saved_flags = 0;
177 }
178
179 /* Now guaranteed to have BUSY deasserted? Just sanity check */
180 if (serial_port_in(p, usr_reg) & DW_UART_USR_BUSY) {
181 dw8250_idle_exit(p);
182 return -EBUSY;
183 }
184
185 return 0;
186 }
187
dw8250_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)188 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
189 unsigned int quot, unsigned int quot_frac)
190 {
191 struct uart_8250_port *up = up_to_u8250p(p);
192 int ret;
193
194 ret = dw8250_idle_enter(p);
195 if (ret < 0)
196 return;
197
198 serial_port_out(p, UART_LCR, up->lcr | UART_LCR_DLAB);
199 if (!(serial_port_in(p, UART_LCR) & UART_LCR_DLAB))
200 goto idle_failed;
201
202 serial_dl_write(up, quot);
203 serial_port_out(p, UART_LCR, up->lcr);
204
205 idle_failed:
206 dw8250_idle_exit(p);
207 }
208
209 /*
210 * This function is being called as part of the uart_port::serial_out()
211 * routine. Hence, special care must be taken when serial_port_out() or
212 * serial_out() against the modified registers here, i.e. LCR (d->in_idle is
213 * used to break recursion loop).
214 */
dw8250_check_lcr(struct uart_port * p,unsigned int offset,u32 value)215 static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value)
216 {
217 struct dw8250_data *d = to_dw8250_data(p->private_data);
218 u32 lcr;
219 int ret;
220
221 if (offset != UART_LCR || d->uart_16550_compatible)
222 return;
223
224 lcr = serial_port_in(p, UART_LCR);
225
226 /* Make sure LCR write wasn't ignored */
227 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
228 return;
229
230 if (d->in_idle)
231 goto write_err;
232
233 ret = dw8250_idle_enter(p);
234 if (ret < 0)
235 goto write_err;
236
237 serial_port_out(p, UART_LCR, value);
238 dw8250_idle_exit(p);
239 return;
240
241 write_err:
242 /*
243 * FIXME: this deadlocks if port->lock is already held
244 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
245 */
246 return; /* Silences "label at the end of compound statement" */
247 }
248
249 /*
250 * With BUSY, LCR writes can be very expensive (IRQ + complex retry logic).
251 * If the write does not change the value of the LCR register, skip it entirely.
252 */
dw8250_can_skip_reg_write(struct uart_port * p,unsigned int offset,u32 value)253 static bool dw8250_can_skip_reg_write(struct uart_port *p, unsigned int offset, u32 value)
254 {
255 struct dw8250_data *d = to_dw8250_data(p->private_data);
256 u32 lcr;
257
258 if (offset != UART_LCR || d->uart_16550_compatible)
259 return false;
260
261 lcr = serial_port_in(p, offset);
262 return lcr == value;
263 }
264
265 /* Returns once the transmitter is empty or we run out of retries */
dw8250_tx_wait_empty(struct uart_port * p)266 static void dw8250_tx_wait_empty(struct uart_port *p)
267 {
268 struct uart_8250_port *up = up_to_u8250p(p);
269 unsigned int tries = 20000;
270 unsigned int delay_threshold = tries - 1000;
271 unsigned int lsr;
272
273 while (tries--) {
274 lsr = readb (p->membase + (UART_LSR << p->regshift));
275 up->lsr_saved_flags |= lsr & up->lsr_save_mask;
276
277 if (lsr & UART_LSR_TEMT)
278 break;
279
280 /* The device is first given a chance to empty without delay,
281 * to avoid slowdowns at high bitrates. If after 1000 tries
282 * the buffer has still not emptied, allow more time for low-
283 * speed links. */
284 if (tries < delay_threshold)
285 udelay (1);
286 }
287 }
288
dw8250_serial_out(struct uart_port * p,unsigned int offset,u32 value)289 static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value)
290 {
291 if (dw8250_can_skip_reg_write(p, offset, value))
292 return;
293
294 writeb(value, p->membase + (offset << p->regshift));
295 dw8250_check_lcr(p, offset, value);
296 }
297
dw8250_serial_out38x(struct uart_port * p,unsigned int offset,u32 value)298 static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value)
299 {
300 if (dw8250_can_skip_reg_write(p, offset, value))
301 return;
302
303 /* Allow the TX to drain before we reconfigure */
304 if (offset == UART_LCR)
305 dw8250_tx_wait_empty(p);
306
307 dw8250_serial_out(p, offset, value);
308 }
309
dw8250_serial_in(struct uart_port * p,unsigned int offset)310 static u32 dw8250_serial_in(struct uart_port *p, unsigned int offset)
311 {
312 u32 value = readb(p->membase + (offset << p->regshift));
313
314 return dw8250_modify_msr(p, offset, value);
315 }
316
317 #ifdef CONFIG_64BIT
dw8250_serial_inq(struct uart_port * p,unsigned int offset)318 static u32 dw8250_serial_inq(struct uart_port *p, unsigned int offset)
319 {
320 u8 value = __raw_readq(p->membase + (offset << p->regshift));
321
322 return dw8250_modify_msr(p, offset, value);
323 }
324
dw8250_serial_outq(struct uart_port * p,unsigned int offset,u32 value)325 static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value)
326 {
327 if (dw8250_can_skip_reg_write(p, offset, value))
328 return;
329
330 value &= 0xff;
331 __raw_writeq(value, p->membase + (offset << p->regshift));
332 /* Read back to ensure register write ordering. */
333 __raw_readq(p->membase + (UART_LCR << p->regshift));
334
335 dw8250_check_lcr(p, offset, value);
336 }
337 #endif /* CONFIG_64BIT */
338
dw8250_serial_out32(struct uart_port * p,unsigned int offset,u32 value)339 static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value)
340 {
341 if (dw8250_can_skip_reg_write(p, offset, value))
342 return;
343
344 writel(value, p->membase + (offset << p->regshift));
345 dw8250_check_lcr(p, offset, value);
346 }
347
dw8250_serial_in32(struct uart_port * p,unsigned int offset)348 static u32 dw8250_serial_in32(struct uart_port *p, unsigned int offset)
349 {
350 u32 value = readl(p->membase + (offset << p->regshift));
351
352 return dw8250_modify_msr(p, offset, value);
353 }
354
dw8250_serial_out32be(struct uart_port * p,unsigned int offset,u32 value)355 static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value)
356 {
357 if (dw8250_can_skip_reg_write(p, offset, value))
358 return;
359
360 iowrite32be(value, p->membase + (offset << p->regshift));
361 dw8250_check_lcr(p, offset, value);
362 }
363
dw8250_serial_in32be(struct uart_port * p,unsigned int offset)364 static u32 dw8250_serial_in32be(struct uart_port *p, unsigned int offset)
365 {
366 u32 value = ioread32be(p->membase + (offset << p->regshift));
367
368 return dw8250_modify_msr(p, offset, value);
369 }
370
371 /*
372 * INTC10EE UART can IRQ storm while reporting IIR_NO_INT. Inducing IIR value
373 * change has been observed to break the storm.
374 *
375 * If Tx is empty (THRE asserted), we use here IER_THRI to cause IIR_NO_INT ->
376 * IIR_THRI transition.
377 */
dw8250_quirk_ier_kick(struct uart_port * p)378 static void dw8250_quirk_ier_kick(struct uart_port *p)
379 {
380 struct uart_8250_port *up = up_to_u8250p(p);
381 u32 lsr;
382
383 if (up->ier & UART_IER_THRI)
384 return;
385
386 lsr = serial_lsr_in(up);
387 if (!(lsr & UART_LSR_THRE))
388 return;
389
390 serial_port_out(p, UART_IER, up->ier | UART_IER_THRI);
391 serial_port_in(p, UART_LCR); /* safe, no side-effects */
392 serial_port_out(p, UART_IER, up->ier);
393 }
394
dw8250_handle_irq(struct uart_port * p)395 static int dw8250_handle_irq(struct uart_port *p)
396 {
397 struct uart_8250_port *up = up_to_u8250p(p);
398 struct dw8250_data *d = to_dw8250_data(p->private_data);
399 unsigned int iir = serial_port_in(p, UART_IIR);
400 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
401 unsigned int quirks = d->pdata->quirks;
402 unsigned int status;
403
404 guard(uart_port_lock_check_sysrq_irqsave)(p);
405
406 switch (FIELD_GET(DW_UART_IIR_IID, iir)) {
407 case UART_IIR_NO_INT:
408 if (d->uart_16550_compatible || up->dma)
409 return 0;
410
411 if (quirks & DW_UART_QUIRK_IER_KICK &&
412 d->no_int_count == (DW_UART_QUIRK_IER_KICK_THRES - 1))
413 dw8250_quirk_ier_kick(p);
414 d->no_int_count = (d->no_int_count + 1) % DW_UART_QUIRK_IER_KICK_THRES;
415
416 return 0;
417
418 case UART_IIR_BUSY:
419 /* Clear the USR */
420 serial_port_in(p, d->pdata->usr_reg);
421
422 d->no_int_count = 0;
423
424 return 1;
425 }
426
427 d->no_int_count = 0;
428
429 /*
430 * There are ways to get Designware-based UARTs into a state where
431 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
432 * data available. If we see such a case then we'll do a bogus
433 * read. If we don't do this then the "RX TIMEOUT" interrupt will
434 * fire forever.
435 *
436 * This problem has only been observed so far when not in DMA mode
437 * so we limit the workaround only to non-DMA mode.
438 */
439 if (!up->dma && rx_timeout) {
440 status = serial_lsr_in(up);
441
442 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
443 serial_port_in(p, UART_RX);
444 }
445
446 /* Manually stop the Rx DMA transfer when acting as flow controller */
447 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
448 status = serial_lsr_in(up);
449
450 if (status & (UART_LSR_DR | UART_LSR_BI)) {
451 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
452 dw8250_writel_ext(p, DW_UART_DMASA, 1);
453 }
454 }
455
456 serial8250_handle_irq_locked(p, iir);
457
458 return 1;
459 }
460
461 static void
dw8250_do_pm(struct uart_port * port,unsigned int state,unsigned int old)462 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
463 {
464 if (!state)
465 pm_runtime_get_sync(port->dev);
466
467 serial8250_do_pm(port, state, old);
468
469 if (state)
470 pm_runtime_put_sync_suspend(port->dev);
471 }
472
dw8250_set_termios(struct uart_port * p,struct ktermios * termios,const struct ktermios * old)473 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
474 const struct ktermios *old)
475 {
476 unsigned long newrate = tty_termios_baud_rate(termios) * 16;
477 struct dw8250_data *d = to_dw8250_data(p->private_data);
478 long rate;
479 int ret;
480
481 clk_disable_unprepare(d->clk);
482 rate = clk_round_rate(d->clk, newrate);
483 if (rate > 0) {
484 ret = clk_set_rate(d->clk, newrate);
485 if (!ret)
486 p->uartclk = rate;
487 }
488 clk_prepare_enable(d->clk);
489
490 dw8250_do_set_termios(p, termios, old);
491 }
492
dw8250_set_ldisc(struct uart_port * p,struct ktermios * termios)493 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
494 {
495 struct uart_8250_port *up = up_to_u8250p(p);
496 unsigned int mcr = serial_port_in(p, UART_MCR);
497
498 if (up->capabilities & UART_CAP_IRDA) {
499 if (termios->c_line == N_IRDA)
500 mcr |= DW_UART_MCR_SIRE;
501 else
502 mcr &= ~DW_UART_MCR_SIRE;
503
504 serial_port_out(p, UART_MCR, mcr);
505 }
506 serial8250_do_set_ldisc(p, termios);
507 }
508
509 /*
510 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
511 * channel on platforms that have DMA engines, but don't have any channels
512 * assigned to the UART.
513 *
514 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
515 * core problem is fixed, this function is no longer needed.
516 */
dw8250_fallback_dma_filter(struct dma_chan * chan,void * param)517 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
518 {
519 return false;
520 }
521
dw8250_idma_filter(struct dma_chan * chan,void * param)522 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
523 {
524 return param == chan->device->dev;
525 }
526
dw8250_setup_dma_filter(struct uart_port * p,struct dw8250_data * data)527 static void dw8250_setup_dma_filter(struct uart_port *p, struct dw8250_data *data)
528 {
529 /* Platforms with iDMA 64-bit */
530 if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) {
531 data->data.dma.rx_param = p->dev->parent;
532 data->data.dma.tx_param = p->dev->parent;
533 data->data.dma.fn = dw8250_idma_filter;
534 } else {
535 data->data.dma.fn = dw8250_fallback_dma_filter;
536 }
537 }
538
dw8250_rzn1_get_dmacr_burst(int max_burst)539 static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
540 {
541 if (max_burst >= 8)
542 return RZN1_UART_xDMACR_8_WORD_BURST;
543 else if (max_burst >= 4)
544 return RZN1_UART_xDMACR_4_WORD_BURST;
545 else
546 return RZN1_UART_xDMACR_1_WORD_BURST;
547 }
548
dw8250_prepare_tx_dma(struct uart_8250_port * p)549 static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
550 {
551 struct uart_port *up = &p->port;
552 struct uart_8250_dma *dma = p->dma;
553 u32 val;
554
555 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
556 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
557 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
558 RZN1_UART_xDMACR_DMA_EN;
559 dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
560 }
561
dw8250_prepare_rx_dma(struct uart_8250_port * p)562 static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
563 {
564 struct uart_port *up = &p->port;
565 struct uart_8250_dma *dma = p->dma;
566 u32 val;
567
568 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
569 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
570 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
571 RZN1_UART_xDMACR_DMA_EN;
572 dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
573 }
574
dw8250_quirks(struct uart_port * p,struct dw8250_data * data)575 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
576 {
577 unsigned int quirks = data->pdata->quirks;
578 u32 cpr_value = data->pdata->cpr_value;
579
580 if (quirks & DW_UART_QUIRK_CPR_VALUE)
581 data->data.cpr_value = cpr_value;
582
583 #ifdef CONFIG_64BIT
584 if (quirks & DW_UART_QUIRK_OCTEON) {
585 p->serial_in = dw8250_serial_inq;
586 p->serial_out = dw8250_serial_outq;
587 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
588 p->type = PORT_OCTEON;
589 data->skip_autocfg = true;
590 }
591 #endif
592
593 if (quirks & DW_UART_QUIRK_ARMADA_38X)
594 p->serial_out = dw8250_serial_out38x;
595 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
596 p->set_termios = dw8250_do_set_termios;
597 if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
598 data->data.dma.txconf.device_fc = 1;
599 data->data.dma.rxconf.device_fc = 1;
600 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
601 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
602 }
603 if (quirks & DW_UART_QUIRK_APMC0D08) {
604 p->iotype = UPIO_MEM32;
605 p->regshift = 2;
606 p->serial_in = dw8250_serial_in32;
607 data->uart_16550_compatible = true;
608 }
609 }
610
dw8250_reset_control_assert(void * data)611 static void dw8250_reset_control_assert(void *data)
612 {
613 reset_control_assert(data);
614 }
615
dw8250_shutdown(struct uart_port * port)616 static void dw8250_shutdown(struct uart_port *port)
617 {
618 struct dw8250_data *d = to_dw8250_data(port->private_data);
619
620 serial8250_do_shutdown(port);
621 d->no_int_count = 0;
622 }
623
dw8250_probe(struct platform_device * pdev)624 static int dw8250_probe(struct platform_device *pdev)
625 {
626 struct uart_8250_port uart = {}, *up = &uart;
627 struct uart_port *p = &up->port;
628 struct device *dev = &pdev->dev;
629 struct dw8250_data *data;
630 struct resource *regs;
631 int err;
632
633 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
634 if (!regs)
635 return dev_err_probe(dev, -EINVAL, "no registers defined\n");
636
637 spin_lock_init(&p->lock);
638 p->pm = dw8250_do_pm;
639 p->type = PORT_8250;
640 p->flags = UPF_FIXED_PORT;
641 p->dev = dev;
642
643 p->set_ldisc = dw8250_set_ldisc;
644 p->set_termios = dw8250_set_termios;
645 p->set_divisor = dw8250_set_divisor;
646
647 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
648 if (!data)
649 return -ENOMEM;
650
651 p->private_data = &data->data;
652
653 p->mapbase = regs->start;
654 p->mapsize = resource_size(regs);
655
656 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize);
657 if (!p->membase)
658 return -ENOMEM;
659
660 err = uart_read_port_properties(p);
661 /* no interrupt -> fall back to polling */
662 if (err == -ENXIO)
663 err = 0;
664 if (err)
665 return err;
666
667 switch (p->iotype) {
668 case UPIO_MEM:
669 p->serial_in = dw8250_serial_in;
670 p->serial_out = dw8250_serial_out;
671 break;
672 case UPIO_MEM32:
673 p->serial_in = dw8250_serial_in32;
674 p->serial_out = dw8250_serial_out32;
675 break;
676 case UPIO_MEM32BE:
677 p->serial_in = dw8250_serial_in32be;
678 p->serial_out = dw8250_serial_out32be;
679 break;
680 default:
681 return -ENODEV;
682 }
683
684 if (device_property_read_bool(dev, "dcd-override")) {
685 /* Always report DCD as active */
686 data->msr_mask_on |= UART_MSR_DCD;
687 data->msr_mask_off |= UART_MSR_DDCD;
688 }
689
690 if (device_property_read_bool(dev, "dsr-override")) {
691 /* Always report DSR as active */
692 data->msr_mask_on |= UART_MSR_DSR;
693 data->msr_mask_off |= UART_MSR_DDSR;
694 }
695
696 if (device_property_read_bool(dev, "cts-override")) {
697 /* Always report CTS as active */
698 data->msr_mask_on |= UART_MSR_CTS;
699 data->msr_mask_off |= UART_MSR_DCTS;
700 }
701
702 if (device_property_read_bool(dev, "ri-override")) {
703 /* Always report Ring indicator as inactive */
704 data->msr_mask_off |= UART_MSR_RI;
705 data->msr_mask_off |= UART_MSR_TERI;
706 }
707
708 /* If there is separate baudclk, get the rate from it. */
709 data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
710 if (data->clk == NULL)
711 data->clk = devm_clk_get_optional_enabled(dev, NULL);
712 if (IS_ERR(data->clk))
713 return dev_err_probe(dev, PTR_ERR(data->clk),
714 "failed to get baudclk\n");
715
716 if (data->clk)
717 p->uartclk = clk_get_rate(data->clk);
718
719 /* If no clock rate is defined, fail. */
720 if (!p->uartclk)
721 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
722
723 data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
724 if (IS_ERR(data->pclk))
725 return PTR_ERR(data->pclk);
726
727 data->rst = devm_reset_control_array_get_optional_exclusive(dev);
728 if (IS_ERR(data->rst))
729 return PTR_ERR(data->rst);
730
731 err = reset_control_deassert(data->rst);
732 if (err)
733 return dev_err_probe(dev, err, "failed to deassert resets\n");
734
735 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
736 if (err)
737 return err;
738
739 err = pm_runtime_set_active(dev);
740 if (err)
741 return dev_err_probe(dev, err, "Failed to set the runtime suspend as active\n");
742
743 data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible");
744
745 data->pdata = device_get_match_data(p->dev);
746 if (data->pdata)
747 dw8250_quirks(p, data);
748
749 /* If the Busy Functionality is not implemented, don't handle it */
750 if (data->uart_16550_compatible) {
751 p->handle_irq = NULL;
752 } else if (data->pdata) {
753 p->handle_irq = dw8250_handle_irq;
754 p->shutdown = dw8250_shutdown;
755 }
756
757 dw8250_setup_dma_filter(p, data);
758
759 if (!data->skip_autocfg)
760 dw8250_setup_port(p);
761
762 /* If we have a valid fifosize, try hooking up DMA */
763 if (p->fifosize) {
764 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
765 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
766 up->dma = &data->data.dma;
767 }
768
769 data->data.line = serial8250_register_8250_port(up);
770 if (data->data.line < 0)
771 return data->data.line;
772
773 platform_set_drvdata(pdev, data);
774
775 pm_runtime_enable(dev);
776
777 return 0;
778 }
779
dw8250_remove(struct platform_device * pdev)780 static void dw8250_remove(struct platform_device *pdev)
781 {
782 struct dw8250_data *data = platform_get_drvdata(pdev);
783 struct device *dev = &pdev->dev;
784
785 pm_runtime_get_sync(dev);
786
787 serial8250_unregister_port(data->data.line);
788
789 pm_runtime_disable(dev);
790 pm_runtime_put_noidle(dev);
791 }
792
dw8250_suspend(struct device * dev)793 static int dw8250_suspend(struct device *dev)
794 {
795 struct dw8250_data *data = dev_get_drvdata(dev);
796
797 serial8250_suspend_port(data->data.line);
798
799 return 0;
800 }
801
dw8250_resume(struct device * dev)802 static int dw8250_resume(struct device *dev)
803 {
804 struct dw8250_data *data = dev_get_drvdata(dev);
805
806 serial8250_resume_port(data->data.line);
807
808 return 0;
809 }
810
dw8250_runtime_suspend(struct device * dev)811 static int dw8250_runtime_suspend(struct device *dev)
812 {
813 struct dw8250_data *data = dev_get_drvdata(dev);
814
815 clk_disable_unprepare(data->clk);
816
817 clk_disable_unprepare(data->pclk);
818
819 return 0;
820 }
821
dw8250_runtime_resume(struct device * dev)822 static int dw8250_runtime_resume(struct device *dev)
823 {
824 int ret;
825 struct dw8250_data *data = dev_get_drvdata(dev);
826
827 ret = clk_prepare_enable(data->pclk);
828 if (ret)
829 return ret;
830
831 ret = clk_prepare_enable(data->clk);
832 if (ret) {
833 clk_disable_unprepare(data->pclk);
834 return ret;
835 }
836
837 return 0;
838 }
839
840 static _DEFINE_DEV_PM_OPS(dw8250_pm_ops, dw8250_suspend, dw8250_resume,
841 dw8250_runtime_suspend, dw8250_runtime_resume,
842 NULL);
843
844 static const struct dw8250_platform_data dw8250_dw_apb = {
845 .usr_reg = DW_UART_USR,
846 };
847
848 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
849 .usr_reg = OCTEON_UART_USR,
850 .quirks = DW_UART_QUIRK_OCTEON,
851 };
852
853 static const struct dw8250_platform_data dw8250_armada_38x_data = {
854 .usr_reg = DW_UART_USR,
855 .quirks = DW_UART_QUIRK_ARMADA_38X,
856 };
857
858 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
859 .usr_reg = DW_UART_USR,
860 .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
861 DW_UART_CPR_AFCE_MODE |
862 DW_UART_CPR_THRE_MODE |
863 DW_UART_CPR_ADDITIONAL_FEATURES |
864 DW_UART_CPR_FIFO_ACCESS |
865 DW_UART_CPR_FIFO_STAT |
866 DW_UART_CPR_SHADOW |
867 DW_UART_CPR_DMA_EXTRA |
868 DW_UART_CPR_FIFO_MODE_FROM_SIZE(16),
869 .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
870 };
871
872 static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
873 .usr_reg = DW_UART_USR,
874 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
875 };
876
877 static const struct dw8250_platform_data dw8250_intc10ee = {
878 .usr_reg = DW_UART_USR,
879 .quirks = DW_UART_QUIRK_IER_KICK,
880 };
881
882 static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
883 .usr_reg = DW_UART_USR,
884 .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
885 DW_UART_CPR_THRE_MODE |
886 DW_UART_CPR_DMA_EXTRA |
887 DW_UART_CPR_FIFO_MODE_FROM_SIZE(32),
888 .quirks = DW_UART_QUIRK_CPR_VALUE,
889 };
890
891 static const struct of_device_id dw8250_of_match[] = {
892 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
893 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
894 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
895 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
896 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
897 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
898 { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data },
899 { /* Sentinel */ }
900 };
901 MODULE_DEVICE_TABLE(of, dw8250_of_match);
902
903 static const struct dw8250_platform_data dw8250_apmc0d08 = {
904 .usr_reg = DW_UART_USR,
905 .quirks = DW_UART_QUIRK_APMC0D08,
906 };
907
908 static const struct acpi_device_id dw8250_acpi_match[] = {
909 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
910 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
911 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
912 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
913 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
914 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },
915 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
916 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
917 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
918 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
919 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
920 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
921 { "INTC10EE", (kernel_ulong_t)&dw8250_intc10ee },
922 { },
923 };
924 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
925
926 static struct platform_driver dw8250_platform_driver = {
927 .driver = {
928 .name = "dw-apb-uart",
929 .pm = pm_ptr(&dw8250_pm_ops),
930 .of_match_table = dw8250_of_match,
931 .acpi_match_table = dw8250_acpi_match,
932 },
933 .probe = dw8250_probe,
934 .remove = dw8250_remove,
935 };
936
937 module_platform_driver(dw8250_platform_driver);
938
939 MODULE_IMPORT_NS("SERIAL_8250");
940 MODULE_AUTHOR("Jamie Iles");
941 MODULE_LICENSE("GPL");
942 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
943 MODULE_ALIAS("platform:dw-apb-uart");
944