1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Nuvoton nct7201 and nct7202 power monitor chips.
4 *
5 * Copyright (c) 2024-2025 Nuvoton Technology corporation.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/delay.h>
12 #include <linux/dev_printk.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/time.h>
18 #include <linux/types.h>
19 #include <linux/unaligned.h>
20
21 #include <linux/iio/events.h>
22 #include <linux/iio/iio.h>
23
24 #define NCT7201_REG_INTERRUPT_STATUS 0x0C
25 #define NCT7201_REG_VOLT_LOW_BYTE 0x0F
26 #define NCT7201_REG_CONFIGURATION 0x10
27 #define NCT7201_BIT_CONFIGURATION_START BIT(0)
28 #define NCT7201_BIT_CONFIGURATION_ALERT_MSK BIT(1)
29 #define NCT7201_BIT_CONFIGURATION_CONV_RATE BIT(2)
30 #define NCT7201_BIT_CONFIGURATION_RESET BIT(7)
31
32 #define NCT7201_REG_ADVANCED_CONFIGURATION 0x11
33 #define NCT7201_BIT_ADVANCED_CONF_MOD_ALERT BIT(0)
34 #define NCT7201_BIT_ADVANCED_CONF_MOD_STS BIT(1)
35 #define NCT7201_BIT_ADVANCED_CONF_FAULT_QUEUE BIT(2)
36 #define NCT7201_BIT_ADVANCED_CONF_EN_DEEP_SHUTDOWN BIT(4)
37 #define NCT7201_BIT_ADVANCED_CONF_EN_SMB_TIMEOUT BIT(5)
38 #define NCT7201_BIT_ADVANCED_CONF_MOD_RSTIN BIT(7)
39
40 #define NCT7201_REG_CHANNEL_INPUT_MODE 0x12
41 #define NCT7201_REG_CHANNEL_ENABLE 0x13
42 #define NCT7201_REG_INTERRUPT_MASK_1 0x15
43 #define NCT7201_REG_INTERRUPT_MASK_2 0x16
44 #define NCT7201_REG_BUSY_STATUS 0x1E
45 #define NCT7201_BIT_BUSY BIT(0)
46 #define NCT7201_BIT_PWR_UP BIT(1)
47 #define NCT7201_REG_ONE_SHOT 0x1F
48 #define NCT7201_REG_SMUS_ADDRESS 0xFC
49 #define NCT7201_REG_VIN_MASK GENMASK(15, 3)
50
51 #define NCT7201_REG_VIN(i) (0x00 + i)
52 #define NCT7201_REG_VIN_HIGH_LIMIT(i) (0x20 + (i) * 2)
53 #define NCT7201_REG_VIN_LOW_LIMIT(i) (0x21 + (i) * 2)
54 #define NCT7201_MAX_CHANNEL 12
55
56 static const struct regmap_range nct7201_read_reg_range[] = {
57 regmap_reg_range(NCT7201_REG_INTERRUPT_STATUS, NCT7201_REG_BUSY_STATUS),
58 regmap_reg_range(NCT7201_REG_SMUS_ADDRESS, NCT7201_REG_SMUS_ADDRESS),
59 };
60
61 static const struct regmap_access_table nct7201_readable_regs_tbl = {
62 .yes_ranges = nct7201_read_reg_range,
63 .n_yes_ranges = ARRAY_SIZE(nct7201_read_reg_range),
64 };
65
66 static const struct regmap_range nct7201_write_reg_range[] = {
67 regmap_reg_range(NCT7201_REG_CONFIGURATION, NCT7201_REG_INTERRUPT_MASK_2),
68 regmap_reg_range(NCT7201_REG_ONE_SHOT, NCT7201_REG_ONE_SHOT),
69 };
70
71 static const struct regmap_access_table nct7201_writeable_regs_tbl = {
72 .yes_ranges = nct7201_write_reg_range,
73 .n_yes_ranges = ARRAY_SIZE(nct7201_write_reg_range),
74 };
75
76 static const struct regmap_range nct7201_read_vin_reg_range[] = {
77 regmap_reg_range(NCT7201_REG_VIN(0), NCT7201_REG_VIN(NCT7201_MAX_CHANNEL - 1)),
78 regmap_reg_range(NCT7201_REG_VIN_HIGH_LIMIT(0),
79 NCT7201_REG_VIN_LOW_LIMIT(NCT7201_MAX_CHANNEL - 1)),
80 };
81
82 static const struct regmap_access_table nct7201_readable_vin_regs_tbl = {
83 .yes_ranges = nct7201_read_vin_reg_range,
84 .n_yes_ranges = ARRAY_SIZE(nct7201_read_vin_reg_range),
85 };
86
87 static const struct regmap_range nct7201_write_vin_reg_range[] = {
88 regmap_reg_range(NCT7201_REG_VIN_HIGH_LIMIT(0),
89 NCT7201_REG_VIN_LOW_LIMIT(NCT7201_MAX_CHANNEL - 1)),
90 };
91
92 static const struct regmap_access_table nct7201_writeable_vin_regs_tbl = {
93 .yes_ranges = nct7201_write_vin_reg_range,
94 .n_yes_ranges = ARRAY_SIZE(nct7201_write_vin_reg_range),
95 };
96
97 static const struct regmap_config nct7201_regmap8_config = {
98 .name = "vin-data-read-byte",
99 .reg_bits = 8,
100 .val_bits = 8,
101 .use_single_read = true,
102 .use_single_write = true,
103 .max_register = 0xff,
104 .rd_table = &nct7201_readable_regs_tbl,
105 .wr_table = &nct7201_writeable_regs_tbl,
106 };
107
108 static const struct regmap_config nct7201_regmap16_config = {
109 .name = "vin-data-read-word",
110 .reg_bits = 8,
111 .val_bits = 16,
112 .max_register = 0xff,
113 .rd_table = &nct7201_readable_vin_regs_tbl,
114 .wr_table = &nct7201_writeable_vin_regs_tbl,
115 };
116
117 struct nct7201_chip_info {
118 struct regmap *regmap;
119 struct regmap *regmap16;
120 int num_vin_channels;
121 __le16 vin_mask;
122 };
123
124 struct nct7201_adc_model_data {
125 const char *model_name;
126 const struct iio_chan_spec *channels;
127 unsigned int num_channels;
128 int num_vin_channels;
129 };
130
131 static const struct iio_event_spec nct7201_events[] = {
132 {
133 .type = IIO_EV_TYPE_THRESH,
134 .dir = IIO_EV_DIR_RISING,
135 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
136 BIT(IIO_EV_INFO_ENABLE),
137 }, {
138 .type = IIO_EV_TYPE_THRESH,
139 .dir = IIO_EV_DIR_FALLING,
140 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
141 BIT(IIO_EV_INFO_ENABLE),
142 },
143 };
144
145 #define NCT7201_VOLTAGE_CHANNEL(num) \
146 { \
147 .type = IIO_VOLTAGE, \
148 .indexed = 1, \
149 .channel = num + 1, \
150 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
151 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
152 .address = num, \
153 .event_spec = nct7201_events, \
154 .num_event_specs = ARRAY_SIZE(nct7201_events), \
155 }
156
157 static const struct iio_chan_spec nct7201_channels[] = {
158 NCT7201_VOLTAGE_CHANNEL(0),
159 NCT7201_VOLTAGE_CHANNEL(1),
160 NCT7201_VOLTAGE_CHANNEL(2),
161 NCT7201_VOLTAGE_CHANNEL(3),
162 NCT7201_VOLTAGE_CHANNEL(4),
163 NCT7201_VOLTAGE_CHANNEL(5),
164 NCT7201_VOLTAGE_CHANNEL(6),
165 NCT7201_VOLTAGE_CHANNEL(7),
166 };
167
168 static const struct iio_chan_spec nct7202_channels[] = {
169 NCT7201_VOLTAGE_CHANNEL(0),
170 NCT7201_VOLTAGE_CHANNEL(1),
171 NCT7201_VOLTAGE_CHANNEL(2),
172 NCT7201_VOLTAGE_CHANNEL(3),
173 NCT7201_VOLTAGE_CHANNEL(4),
174 NCT7201_VOLTAGE_CHANNEL(5),
175 NCT7201_VOLTAGE_CHANNEL(6),
176 NCT7201_VOLTAGE_CHANNEL(7),
177 NCT7201_VOLTAGE_CHANNEL(8),
178 NCT7201_VOLTAGE_CHANNEL(9),
179 NCT7201_VOLTAGE_CHANNEL(10),
180 NCT7201_VOLTAGE_CHANNEL(11),
181 };
182
nct7201_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)183 static int nct7201_read_raw(struct iio_dev *indio_dev,
184 struct iio_chan_spec const *chan,
185 int *val, int *val2, long mask)
186 {
187 struct nct7201_chip_info *chip = iio_priv(indio_dev);
188 unsigned int value;
189 int err;
190
191 if (chan->type != IIO_VOLTAGE)
192 return -EOPNOTSUPP;
193
194 switch (mask) {
195 case IIO_CHAN_INFO_RAW:
196 err = regmap_read(chip->regmap16, NCT7201_REG_VIN(chan->address), &value);
197 if (err)
198 return err;
199 *val = FIELD_GET(NCT7201_REG_VIN_MASK, value);
200 return IIO_VAL_INT;
201 case IIO_CHAN_INFO_SCALE:
202 /* From the datasheet, we have to multiply by 0.0004995 */
203 *val = 0;
204 *val2 = 499500;
205 return IIO_VAL_INT_PLUS_NANO;
206 default:
207 return -EINVAL;
208 }
209 }
210
nct7201_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)211 static int nct7201_read_event_value(struct iio_dev *indio_dev,
212 const struct iio_chan_spec *chan,
213 enum iio_event_type type,
214 enum iio_event_direction dir,
215 enum iio_event_info info,
216 int *val, int *val2)
217 {
218 struct nct7201_chip_info *chip = iio_priv(indio_dev);
219 unsigned int value;
220 int err;
221
222 if (chan->type != IIO_VOLTAGE)
223 return -EOPNOTSUPP;
224
225 if (info != IIO_EV_INFO_VALUE)
226 return -EINVAL;
227
228 if (dir == IIO_EV_DIR_FALLING)
229 err = regmap_read(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->address),
230 &value);
231 else
232 err = regmap_read(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->address),
233 &value);
234 if (err)
235 return err;
236
237 *val = FIELD_GET(NCT7201_REG_VIN_MASK, value);
238
239 return IIO_VAL_INT;
240 }
241
nct7201_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)242 static int nct7201_write_event_value(struct iio_dev *indio_dev,
243 const struct iio_chan_spec *chan,
244 enum iio_event_type type,
245 enum iio_event_direction dir,
246 enum iio_event_info info,
247 int val, int val2)
248 {
249 struct nct7201_chip_info *chip = iio_priv(indio_dev);
250 int err;
251
252 if (chan->type != IIO_VOLTAGE)
253 return -EOPNOTSUPP;
254
255 if (info != IIO_EV_INFO_VALUE)
256 return -EOPNOTSUPP;
257
258 if (dir == IIO_EV_DIR_FALLING)
259 err = regmap_write(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->address),
260 FIELD_PREP(NCT7201_REG_VIN_MASK, val));
261 else
262 err = regmap_write(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->address),
263 FIELD_PREP(NCT7201_REG_VIN_MASK, val));
264
265 return err;
266 }
267
nct7201_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)268 static int nct7201_read_event_config(struct iio_dev *indio_dev,
269 const struct iio_chan_spec *chan,
270 enum iio_event_type type,
271 enum iio_event_direction dir)
272 {
273 struct nct7201_chip_info *chip = iio_priv(indio_dev);
274
275 if (chan->type != IIO_VOLTAGE)
276 return -EOPNOTSUPP;
277
278 return !!(le16_to_cpu(chip->vin_mask) & BIT(chan->address));
279 }
280
nct7201_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)281 static int nct7201_write_event_config(struct iio_dev *indio_dev,
282 const struct iio_chan_spec *chan,
283 enum iio_event_type type,
284 enum iio_event_direction dir,
285 bool state)
286 {
287 struct nct7201_chip_info *chip = iio_priv(indio_dev);
288 __le16 mask = cpu_to_le16(BIT(chan->address));
289 int err;
290
291 if (chan->type != IIO_VOLTAGE)
292 return -EOPNOTSUPP;
293
294 if (state)
295 chip->vin_mask |= mask;
296 else
297 chip->vin_mask &= ~mask;
298
299 if (chip->num_vin_channels <= 8)
300 err = regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE,
301 le16_to_cpu(chip->vin_mask));
302 else
303 err = regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE,
304 &chip->vin_mask, sizeof(chip->vin_mask));
305
306 return err;
307 }
308
309 static const struct iio_info nct7201_info = {
310 .read_raw = nct7201_read_raw,
311 .read_event_config = nct7201_read_event_config,
312 .write_event_config = nct7201_write_event_config,
313 .read_event_value = nct7201_read_event_value,
314 .write_event_value = nct7201_write_event_value,
315 };
316
317 static const struct iio_info nct7201_info_no_irq = {
318 .read_raw = nct7201_read_raw,
319 };
320
321 static const struct nct7201_adc_model_data nct7201_model_data = {
322 .model_name = "nct7201",
323 .channels = nct7201_channels,
324 .num_channels = ARRAY_SIZE(nct7201_channels),
325 .num_vin_channels = 8,
326 };
327
328 static const struct nct7201_adc_model_data nct7202_model_data = {
329 .model_name = "nct7202",
330 .channels = nct7202_channels,
331 .num_channels = ARRAY_SIZE(nct7202_channels),
332 .num_vin_channels = 12,
333 };
334
nct7201_init_chip(struct nct7201_chip_info * chip)335 static int nct7201_init_chip(struct nct7201_chip_info *chip)
336 {
337 struct device *dev = regmap_get_device(chip->regmap);
338 __le16 data = cpu_to_le16(GENMASK(chip->num_vin_channels - 1, 0));
339 unsigned int value;
340 int err;
341
342 err = regmap_write(chip->regmap, NCT7201_REG_CONFIGURATION,
343 NCT7201_BIT_CONFIGURATION_RESET);
344 if (err)
345 return dev_err_probe(dev, err, "Failed to reset chip\n");
346
347 /*
348 * After about 25 msecs, the device should be ready and then the power-up
349 * bit will be set to 1.
350 */
351 fsleep(25 * USEC_PER_MSEC);
352
353 err = regmap_read(chip->regmap, NCT7201_REG_BUSY_STATUS, &value);
354 if (err)
355 return dev_err_probe(dev, err, "Failed to read busy status\n");
356 if (!(value & NCT7201_BIT_PWR_UP))
357 return dev_err_probe(dev, -EIO, "Failed to power up after reset\n");
358
359 /* Enable Channels */
360 if (chip->num_vin_channels <= 8)
361 err = regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE,
362 le16_to_cpu(data));
363 else
364 err = regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE,
365 &data, sizeof(data));
366 if (err)
367 return dev_err_probe(dev, err, "Failed to enable channels\n");
368
369 err = regmap_bulk_read(chip->regmap, NCT7201_REG_CHANNEL_ENABLE,
370 &chip->vin_mask, sizeof(chip->vin_mask));
371 if (err)
372 return dev_err_probe(dev, err,
373 "Failed to read channel enable register\n");
374
375 /* Start monitoring if needed */
376 err = regmap_set_bits(chip->regmap, NCT7201_REG_CONFIGURATION,
377 NCT7201_BIT_CONFIGURATION_START);
378 if (err)
379 return dev_err_probe(dev, err, "Failed to start monitoring\n");
380
381 return 0;
382 }
383
nct7201_irq_handler(int irq,void * private)384 static irqreturn_t nct7201_irq_handler(int irq, void *private)
385 {
386 struct iio_dev *indio_dev = private;
387 struct nct7201_chip_info *chip = iio_priv(indio_dev);
388 __le16 data;
389 int err;
390
391 err = regmap_bulk_read(chip->regmap, NCT7201_REG_INTERRUPT_STATUS,
392 &data, sizeof(data));
393 if (err)
394 return IRQ_NONE;
395
396 if (data)
397 iio_push_event(indio_dev,
398 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
399 0,
400 IIO_EV_TYPE_THRESH,
401 IIO_EV_DIR_EITHER),
402 iio_get_time_ns(indio_dev));
403
404 return IRQ_HANDLED;
405 }
406
nct7201_probe(struct i2c_client * client)407 static int nct7201_probe(struct i2c_client *client)
408 {
409 const struct nct7201_adc_model_data *model_data;
410 struct device *dev = &client->dev;
411 struct nct7201_chip_info *chip;
412 struct iio_dev *indio_dev;
413 int ret;
414
415 model_data = i2c_get_match_data(client);
416 if (!model_data)
417 return -ENODEV;
418
419 indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
420 if (!indio_dev)
421 return -ENOMEM;
422 chip = iio_priv(indio_dev);
423
424 chip->regmap = devm_regmap_init_i2c(client, &nct7201_regmap8_config);
425 if (IS_ERR(chip->regmap))
426 return dev_err_probe(dev, PTR_ERR(chip->regmap),
427 "Failed to init regmap\n");
428
429 chip->regmap16 = devm_regmap_init_i2c(client, &nct7201_regmap16_config);
430 if (IS_ERR(chip->regmap16))
431 return dev_err_probe(dev, PTR_ERR(chip->regmap16),
432 "Failed to init regmap16\n");
433
434 chip->num_vin_channels = model_data->num_vin_channels;
435
436 ret = nct7201_init_chip(chip);
437 if (ret)
438 return ret;
439
440 indio_dev->name = model_data->model_name;
441 indio_dev->channels = model_data->channels;
442 indio_dev->num_channels = model_data->num_channels;
443 if (client->irq) {
444 /* Enable alert function */
445 ret = regmap_clear_bits(chip->regmap, NCT7201_REG_CONFIGURATION,
446 NCT7201_BIT_CONFIGURATION_ALERT_MSK);
447 if (ret)
448 return dev_err_probe(dev, ret,
449 "Failed to enable alert function\n");
450
451 ret = devm_request_threaded_irq(dev, client->irq,
452 NULL, nct7201_irq_handler,
453 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
454 client->name, indio_dev);
455 if (ret)
456 return dev_err_probe(dev, ret,
457 "Failed to assign interrupt.\n");
458
459 indio_dev->info = &nct7201_info;
460 } else {
461 indio_dev->info = &nct7201_info_no_irq;
462 }
463 indio_dev->modes = INDIO_DIRECT_MODE;
464
465 return devm_iio_device_register(dev, indio_dev);
466 }
467
468 static const struct i2c_device_id nct7201_id[] = {
469 { .name = "nct7201", .driver_data = (kernel_ulong_t)&nct7201_model_data },
470 { .name = "nct7202", .driver_data = (kernel_ulong_t)&nct7202_model_data },
471 { }
472 };
473 MODULE_DEVICE_TABLE(i2c, nct7201_id);
474
475 static const struct of_device_id nct7201_of_match[] = {
476 {
477 .compatible = "nuvoton,nct7201",
478 .data = &nct7201_model_data,
479 },
480 {
481 .compatible = "nuvoton,nct7202",
482 .data = &nct7202_model_data,
483 },
484 { }
485 };
486 MODULE_DEVICE_TABLE(of, nct7201_of_match);
487
488 static struct i2c_driver nct7201_driver = {
489 .driver = {
490 .name = "nct7201",
491 .of_match_table = nct7201_of_match,
492 },
493 .probe = nct7201_probe,
494 .id_table = nct7201_id,
495 };
496 module_i2c_driver(nct7201_driver);
497
498 MODULE_AUTHOR("Eason Yang <j2anfernee@gmail.com>");
499 MODULE_DESCRIPTION("Nuvoton NCT7201 voltage monitor driver");
500 MODULE_LICENSE("GPL");
501