1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid/types.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 #include <asm/vmxfeatures.h> 29 #include <asm/vdso/processor.h> 30 #include <asm/shstk.h> 31 32 #include <linux/personality.h> 33 #include <linux/cache.h> 34 #include <linux/threads.h> 35 #include <linux/math64.h> 36 #include <linux/err.h> 37 #include <linux/irqflags.h> 38 #include <linux/mem_encrypt.h> 39 40 /* 41 * We handle most unaligned accesses in hardware. On the other hand 42 * unaligned DMA can be quite expensive on some Nehalem processors. 43 * 44 * Based on this we disable the IP header alignment in network drivers. 45 */ 46 #define NET_IP_ALIGN 0 47 48 #define HBP_NUM 4 49 50 /* 51 * These alignment constraints are for performance in the vSMP case, 52 * but in the task_struct case we must also meet hardware imposed 53 * alignment requirements of the FPU state: 54 */ 55 #ifdef CONFIG_X86_VSMP 56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58 #else 59 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 60 # define ARCH_MIN_MMSTRUCT_ALIGN 0 61 #endif 62 63 extern u16 __read_mostly tlb_lli_4k; 64 extern u16 __read_mostly tlb_lli_2m; 65 extern u16 __read_mostly tlb_lli_4m; 66 extern u16 __read_mostly tlb_lld_4k; 67 extern u16 __read_mostly tlb_lld_2m; 68 extern u16 __read_mostly tlb_lld_4m; 69 extern u16 __read_mostly tlb_lld_1g; 70 71 /* 72 * CPU type and hardware bug flags. Kept separately for each CPU. 73 */ 74 75 struct cpuinfo_topology { 76 // Real APIC ID read from the local APIC 77 u32 apicid; 78 // The initial APIC ID provided by CPUID 79 u32 initial_apicid; 80 81 // Physical package ID 82 u32 pkg_id; 83 84 // Physical die ID on AMD, Relative on Intel 85 u32 die_id; 86 87 // Compute unit ID - AMD specific 88 u32 cu_id; 89 90 // Core ID relative to the package 91 u32 core_id; 92 93 // Logical ID mappings 94 u32 logical_pkg_id; 95 u32 logical_die_id; 96 u32 logical_core_id; 97 98 // AMD Node ID and Nodes per Package info 99 u32 amd_node_id; 100 101 // Cache level topology IDs 102 u32 llc_id; 103 u32 l2c_id; 104 105 // Hardware defined CPU-type 106 union { 107 u32 cpu_type; 108 struct { 109 // CPUID.1A.EAX[23-0] 110 u32 intel_native_model_id :24; 111 // CPUID.1A.EAX[31-24] 112 u32 intel_type :8; 113 }; 114 struct { 115 // CPUID 0x80000026.EBX 116 u32 amd_num_processors :16, 117 amd_power_eff_ranking :8, 118 amd_native_model_id :4, 119 amd_type :4; 120 }; 121 }; 122 }; 123 124 struct cpuinfo_x86 { 125 union { 126 /* 127 * The particular ordering (low-to-high) of (vendor, 128 * family, model) is done in case range of models, like 129 * it is usually done on AMD, need to be compared. 130 */ 131 struct { 132 __u8 x86_model; 133 /* CPU family */ 134 __u8 x86; 135 /* CPU vendor */ 136 __u8 x86_vendor; 137 __u8 x86_reserved; 138 }; 139 /* combined vendor, family, model */ 140 __u32 x86_vfm; 141 }; 142 __u8 x86_stepping; 143 union { 144 // MSR_IA32_PLATFORM_ID[52-50] 145 __u8 intel_platform_id; 146 __u8 amd_unused; 147 }; 148 #ifdef CONFIG_X86_64 149 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 150 int x86_tlbsize; 151 #endif 152 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 153 __u32 vmx_capability[NVMXINTS]; 154 #endif 155 __u8 x86_virt_bits; 156 __u8 x86_phys_bits; 157 /* Max extended CPUID function supported: */ 158 __u32 extended_cpuid_level; 159 /* Maximum supported CPUID level, -1=no CPUID: */ 160 int cpuid_level; 161 /* 162 * Align to size of unsigned long because the x86_capability array 163 * is passed to bitops which require the alignment. Use unnamed 164 * union to enforce the array is aligned to size of unsigned long. 165 */ 166 union { 167 __u32 x86_capability[NCAPINTS + NBUGINTS]; 168 unsigned long x86_capability_alignment; 169 }; 170 char x86_vendor_id[16]; 171 char x86_model_id[64]; 172 struct cpuinfo_topology topo; 173 struct cpuid_table cpuid; 174 /* in KB - valid for CPUS which support this call: */ 175 unsigned int x86_cache_size; 176 int x86_cache_alignment; /* In bytes */ 177 /* Cache QoS architectural values, valid only on the BSP: */ 178 int x86_cache_max_rmid; /* max index */ 179 int x86_cache_occ_scale; /* scale to bytes */ 180 int x86_cache_mbm_width_offset; 181 int x86_power; 182 unsigned long loops_per_jiffy; 183 /* protected processor identification number */ 184 u64 ppin; 185 u16 x86_clflush_size; 186 /* number of cores as seen by the OS: */ 187 u16 booted_cores; 188 /* Index into per_cpu list: */ 189 u16 cpu_index; 190 /* Is SMT active on this core? */ 191 bool smt_active; 192 u32 microcode; 193 /* Address space bits used by the cache internally */ 194 u8 x86_cache_bits; 195 unsigned initialized : 1; 196 } __randomize_layout; 197 198 #define X86_VENDOR_INTEL 0 199 #define X86_VENDOR_CYRIX 1 200 #define X86_VENDOR_AMD 2 201 #define X86_VENDOR_UMC 3 202 #define X86_VENDOR_CENTAUR 5 203 #define X86_VENDOR_TRANSMETA 7 204 #define X86_VENDOR_NSC 8 205 #define X86_VENDOR_HYGON 9 206 #define X86_VENDOR_ZHAOXIN 10 207 #define X86_VENDOR_VORTEX 11 208 #define X86_VENDOR_NUM 12 209 210 #define X86_VENDOR_UNKNOWN 0xff 211 212 /* 213 * capabilities of CPUs 214 */ 215 extern struct cpuinfo_x86 boot_cpu_data; 216 extern struct cpuinfo_x86 new_cpu_data; 217 218 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 219 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 220 221 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 222 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 223 224 extern const struct seq_operations cpuinfo_op; 225 226 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 227 228 extern void cpu_detect(struct cpuinfo_x86 *c); 229 230 static inline unsigned long long l1tf_pfn_limit(void) 231 { 232 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 233 } 234 235 void init_cpu_devs(void); 236 void get_cpu_vendor(struct cpuinfo_x86 *c); 237 extern void early_cpu_init(void); 238 extern void identify_secondary_cpu(unsigned int cpu); 239 extern void print_cpu_info(struct cpuinfo_x86 *); 240 void print_cpu_msr(struct cpuinfo_x86 *); 241 242 /* 243 * Friendlier CR3 helpers. 244 */ 245 static inline unsigned long read_cr3_pa(void) 246 { 247 return __read_cr3() & CR3_ADDR_MASK; 248 } 249 250 static inline unsigned long native_read_cr3_pa(void) 251 { 252 return __native_read_cr3() & CR3_ADDR_MASK; 253 } 254 255 static inline void load_cr3(pgd_t *pgdir) 256 { 257 write_cr3(__sme_pa(pgdir)); 258 } 259 260 /* 261 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 262 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 263 * unrelated to the task-switch mechanism: 264 */ 265 #ifdef CONFIG_X86_32 266 /* This is the TSS defined by the hardware. */ 267 struct x86_hw_tss { 268 unsigned short back_link, __blh; 269 unsigned long sp0; 270 unsigned short ss0, __ss0h; 271 unsigned long sp1; 272 273 /* 274 * We don't use ring 1, so ss1 is a convenient scratch space in 275 * the same cacheline as sp0. We use ss1 to cache the value in 276 * MSR_IA32_SYSENTER_CS. When we context switch 277 * MSR_IA32_SYSENTER_CS, we first check if the new value being 278 * written matches ss1, and, if it's not, then we wrmsr the new 279 * value and update ss1. 280 * 281 * The only reason we context switch MSR_IA32_SYSENTER_CS is 282 * that we set it to zero in vm86 tasks to avoid corrupting the 283 * stack if we were to go through the sysenter path from vm86 284 * mode. 285 */ 286 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 287 288 unsigned short __ss1h; 289 unsigned long sp2; 290 unsigned short ss2, __ss2h; 291 unsigned long __cr3; 292 unsigned long ip; 293 unsigned long flags; 294 unsigned long ax; 295 unsigned long cx; 296 unsigned long dx; 297 unsigned long bx; 298 unsigned long sp; 299 unsigned long bp; 300 unsigned long si; 301 unsigned long di; 302 unsigned short es, __esh; 303 unsigned short cs, __csh; 304 unsigned short ss, __ssh; 305 unsigned short ds, __dsh; 306 unsigned short fs, __fsh; 307 unsigned short gs, __gsh; 308 unsigned short ldt, __ldth; 309 unsigned short trace; 310 unsigned short io_bitmap_base; 311 312 } __attribute__((packed)); 313 #else 314 struct x86_hw_tss { 315 u32 reserved1; 316 u64 sp0; 317 u64 sp1; 318 319 /* 320 * Since Linux does not use ring 2, the 'sp2' slot is unused by 321 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 322 * the user RSP value. 323 */ 324 u64 sp2; 325 326 u64 reserved2; 327 u64 ist[7]; 328 u32 reserved3; 329 u32 reserved4; 330 u16 reserved5; 331 u16 io_bitmap_base; 332 333 } __attribute__((packed)); 334 #endif 335 336 /* 337 * IO-bitmap sizes: 338 */ 339 #define IO_BITMAP_BITS 65536 340 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 341 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 342 343 #define IO_BITMAP_OFFSET_VALID_MAP \ 344 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 345 offsetof(struct tss_struct, x86_tss)) 346 347 #define IO_BITMAP_OFFSET_VALID_ALL \ 348 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 349 offsetof(struct tss_struct, x86_tss)) 350 351 #ifdef CONFIG_X86_IOPL_IOPERM 352 /* 353 * sizeof(unsigned long) coming from an extra "long" at the end of the 354 * iobitmap. The limit is inclusive, i.e. the last valid byte. 355 */ 356 # define __KERNEL_TSS_LIMIT \ 357 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 358 sizeof(unsigned long) - 1) 359 #else 360 # define __KERNEL_TSS_LIMIT \ 361 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 362 #endif 363 364 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 365 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 366 367 struct entry_stack { 368 char stack[PAGE_SIZE]; 369 }; 370 371 struct entry_stack_page { 372 struct entry_stack stack; 373 } __aligned(PAGE_SIZE); 374 375 /* 376 * All IO bitmap related data stored in the TSS: 377 */ 378 struct x86_io_bitmap { 379 /* The sequence number of the last active bitmap. */ 380 u64 prev_sequence; 381 382 /* 383 * Store the dirty size of the last io bitmap offender. The next 384 * one will have to do the cleanup as the switch out to a non io 385 * bitmap user will just set x86_tss.io_bitmap_base to a value 386 * outside of the TSS limit. So for sane tasks there is no need to 387 * actually touch the io_bitmap at all. 388 */ 389 unsigned int prev_max; 390 391 /* 392 * The extra 1 is there because the CPU will access an 393 * additional byte beyond the end of the IO permission 394 * bitmap. The extra byte must be all 1 bits, and must 395 * be within the limit. 396 */ 397 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 398 399 /* 400 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 401 * except the additional byte at the end. 402 */ 403 unsigned long mapall[IO_BITMAP_LONGS + 1]; 404 }; 405 406 struct tss_struct { 407 /* 408 * The fixed hardware portion. This must not cross a page boundary 409 * at risk of violating the SDM's advice and potentially triggering 410 * errata. 411 */ 412 struct x86_hw_tss x86_tss; 413 414 struct x86_io_bitmap io_bitmap; 415 } __aligned(PAGE_SIZE); 416 417 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 418 419 /* Per CPU interrupt stacks */ 420 struct irq_stack { 421 char stack[IRQ_STACK_SIZE]; 422 } __aligned(IRQ_STACK_SIZE); 423 424 DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, hardirq_stack_ptr); 425 #ifdef CONFIG_X86_64 426 DECLARE_PER_CPU_CACHE_HOT(bool, hardirq_stack_inuse); 427 #else 428 DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, softirq_stack_ptr); 429 #endif 430 431 DECLARE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack); 432 /* const-qualified alias provided by the linker. */ 433 DECLARE_PER_CPU_CACHE_HOT(const unsigned long __percpu_seg_override, 434 const_cpu_current_top_of_stack); 435 436 #ifdef CONFIG_X86_64 437 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 438 { 439 #ifdef CONFIG_SMP 440 return per_cpu_offset(cpu); 441 #else 442 return 0; 443 #endif 444 } 445 446 extern asmlinkage void entry_SYSCALL32_ignore(void); 447 448 /* Save actual FS/GS selectors and bases to current->thread */ 449 void current_save_fsgs(void); 450 #endif /* X86_64 */ 451 452 struct perf_event; 453 454 struct thread_struct { 455 /* Cached TLS descriptors: */ 456 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 457 #ifdef CONFIG_X86_32 458 unsigned long sp0; 459 #endif 460 unsigned long sp; 461 #ifdef CONFIG_X86_32 462 unsigned long sysenter_cs; 463 #else 464 unsigned short es; 465 unsigned short ds; 466 unsigned short fsindex; 467 unsigned short gsindex; 468 #endif 469 470 #ifdef CONFIG_X86_64 471 unsigned long fsbase; 472 unsigned long gsbase; 473 #else 474 /* 475 * XXX: this could presumably be unsigned short. Alternatively, 476 * 32-bit kernels could be taught to use fsindex instead. 477 */ 478 unsigned long fs; 479 unsigned long gs; 480 #endif 481 482 /* Save middle states of ptrace breakpoints */ 483 struct perf_event *ptrace_bps[HBP_NUM]; 484 /* Debug status used for traps, single steps, etc... */ 485 unsigned long virtual_dr6; 486 /* Keep track of the exact dr7 value set by the user */ 487 unsigned long ptrace_dr7; 488 /* Fault info: */ 489 unsigned long cr2; 490 unsigned long trap_nr; 491 unsigned long error_code; 492 #ifdef CONFIG_VM86 493 /* Virtual 86 mode info */ 494 struct vm86 *vm86; 495 #endif 496 /* IO permissions: */ 497 struct io_bitmap *io_bitmap; 498 499 /* 500 * IOPL. Privilege level dependent I/O permission which is 501 * emulated via the I/O bitmap to prevent user space from disabling 502 * interrupts. 503 */ 504 unsigned long iopl_emul; 505 506 unsigned int iopl_warn:1; 507 508 /* 509 * Protection Keys Register for Userspace. Loaded immediately on 510 * context switch. Store it in thread_struct to avoid a lookup in 511 * the tasks's FPU xstate buffer. This value is only valid when a 512 * task is scheduled out. For 'current' the authoritative source of 513 * PKRU is the hardware itself. 514 */ 515 u32 pkru; 516 517 #ifdef CONFIG_X86_USER_SHADOW_STACK 518 unsigned long features; 519 unsigned long features_locked; 520 521 struct thread_shstk shstk; 522 #endif 523 }; 524 525 #ifdef CONFIG_X86_DEBUG_FPU 526 extern struct fpu *x86_task_fpu(struct task_struct *task); 527 #else 528 # define x86_task_fpu(task) ((struct fpu *)((void *)(task) + sizeof(*(task)))) 529 #endif 530 531 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 532 533 static inline void arch_thread_struct_whitelist(unsigned long *offset, 534 unsigned long *size) 535 { 536 fpu_thread_struct_whitelist(offset, size); 537 } 538 539 static inline void 540 native_load_sp0(unsigned long sp0) 541 { 542 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 543 } 544 545 static __always_inline void native_swapgs(void) 546 { 547 #ifdef CONFIG_X86_64 548 asm volatile("swapgs" ::: "memory"); 549 #endif 550 } 551 552 static __always_inline unsigned long current_top_of_stack(void) 553 { 554 /* 555 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 556 * and around vm86 mode and sp0 on x86_64 is special because of the 557 * entry trampoline. 558 */ 559 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT)) 560 return this_cpu_read_const(const_cpu_current_top_of_stack); 561 562 return this_cpu_read_stable(cpu_current_top_of_stack); 563 } 564 565 static __always_inline bool on_thread_stack(void) 566 { 567 return (unsigned long)(current_top_of_stack() - 568 current_stack_pointer) < THREAD_SIZE; 569 } 570 571 #ifdef CONFIG_PARAVIRT_XXL 572 #include <asm/paravirt.h> 573 #else 574 575 static inline void load_sp0(unsigned long sp0) 576 { 577 native_load_sp0(sp0); 578 } 579 580 #endif /* CONFIG_PARAVIRT_XXL */ 581 582 unsigned long __get_wchan(struct task_struct *p); 583 584 extern void select_idle_routine(void); 585 extern void amd_e400_c1e_apic_setup(void); 586 587 extern unsigned long boot_option_idle_override; 588 589 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 590 IDLE_POLL}; 591 592 extern void enable_sep_cpu(void); 593 594 595 /* Defined in head.S */ 596 extern struct desc_ptr early_gdt_descr; 597 598 extern void switch_gdt_and_percpu_base(int); 599 extern void load_direct_gdt(int); 600 extern void load_fixmap_gdt(int); 601 extern void cpu_init(void); 602 extern void cpu_init_exception_handling(bool boot_cpu); 603 extern void cpu_init_replace_early_idt(void); 604 extern void cr4_init(void); 605 606 extern void set_task_blockstep(struct task_struct *task, bool on); 607 608 /* Boot loader type from the setup header: */ 609 extern int bootloader_type; 610 extern int bootloader_version; 611 612 extern char ignore_fpu_irq; 613 614 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 615 #define ARCH_HAS_PREFETCHW 616 617 #ifdef CONFIG_X86_32 618 # define BASE_PREFETCH "" 619 # define ARCH_HAS_PREFETCH 620 #else 621 # define BASE_PREFETCH "prefetcht0 %1" 622 #endif 623 624 /* 625 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 626 * 627 * It's not worth to care about 3dnow prefetches for the K6 628 * because they are microcoded there and very slow. 629 */ 630 static inline void prefetch(const void *x) 631 { 632 alternative_input(BASE_PREFETCH, "prefetchnta %1", 633 X86_FEATURE_XMM, 634 "m" (*(const char *)x)); 635 } 636 637 /* 638 * 3dnow prefetch to get an exclusive cache line. 639 * Useful for spinlocks to avoid one state transition in the 640 * cache coherency protocol: 641 */ 642 static __always_inline void prefetchw(const void *x) 643 { 644 alternative_input(BASE_PREFETCH, "prefetchw %1", 645 X86_FEATURE_3DNOWPREFETCH, 646 "m" (*(const char *)x)); 647 } 648 649 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 650 TOP_OF_KERNEL_STACK_PADDING) 651 652 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 653 654 #define task_pt_regs(task) \ 655 ({ \ 656 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 657 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 658 ((struct pt_regs *)__ptr) - 1; \ 659 }) 660 661 #ifdef CONFIG_X86_32 662 #define INIT_THREAD { \ 663 .sp0 = TOP_OF_INIT_STACK, \ 664 .sysenter_cs = __KERNEL_CS, \ 665 } 666 667 #else 668 extern unsigned long __top_init_kernel_stack[]; 669 670 #define INIT_THREAD { \ 671 .sp = (unsigned long)&__top_init_kernel_stack, \ 672 } 673 674 #endif /* CONFIG_X86_64 */ 675 676 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 677 unsigned long new_sp); 678 679 /* 680 * This decides where the kernel will search for a free chunk of vm 681 * space during mmap's. 682 */ 683 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 684 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 685 686 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 687 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 688 689 /* Get/set a process' ability to use the timestamp counter instruction */ 690 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 691 #define SET_TSC_CTL(val) set_tsc_mode((val)) 692 693 extern int get_tsc_mode(unsigned long adr); 694 extern int set_tsc_mode(unsigned int val); 695 696 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 697 698 static inline u32 per_cpu_llc_id(unsigned int cpu) 699 { 700 return per_cpu(cpu_info.topo.llc_id, cpu); 701 } 702 703 static inline u32 per_cpu_l2c_id(unsigned int cpu) 704 { 705 return per_cpu(cpu_info.topo.l2c_id, cpu); 706 } 707 708 static inline u32 per_cpu_core_id(unsigned int cpu) 709 { 710 return per_cpu(cpu_info.topo.core_id, cpu); 711 } 712 713 #ifdef CONFIG_CPU_SUP_AMD 714 /* 715 * Issue a DIV 0/1 insn to clear any division data from previous DIV 716 * operations. 717 */ 718 static __always_inline void amd_clear_divider(void) 719 { 720 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0) 721 :: "a" (0), "d" (0), "r" (1)); 722 } 723 724 extern void amd_check_microcode(void); 725 #else 726 static inline void amd_clear_divider(void) { } 727 static inline void amd_check_microcode(void) { } 728 #endif 729 730 extern unsigned long arch_align_stack(unsigned long sp); 731 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 732 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 733 734 void default_idle(void); 735 #ifdef CONFIG_XEN 736 bool xen_set_default_idle(void); 737 #else 738 #define xen_set_default_idle 0 739 #endif 740 741 void __noreturn stop_this_cpu(void *dummy); 742 extern bool x86_hypervisor_present; 743 void microcode_check(struct cpuinfo_x86 *prev_info); 744 void store_cpu_caps(struct cpuinfo_x86 *info); 745 746 DECLARE_PER_CPU(bool, cache_state_incoherent); 747 748 enum l1tf_mitigations { 749 L1TF_MITIGATION_OFF, 750 L1TF_MITIGATION_AUTO, 751 L1TF_MITIGATION_FLUSH_NOWARN, 752 L1TF_MITIGATION_FLUSH, 753 L1TF_MITIGATION_FLUSH_NOSMT, 754 L1TF_MITIGATION_FULL, 755 L1TF_MITIGATION_FULL_FORCE 756 }; 757 758 extern enum l1tf_mitigations l1tf_mitigation; 759 760 enum mds_mitigations { 761 MDS_MITIGATION_OFF, 762 MDS_MITIGATION_AUTO, 763 MDS_MITIGATION_FULL, 764 MDS_MITIGATION_VMWERV, 765 }; 766 767 extern bool gds_ucode_mitigated(void); 768 769 /* 770 * Make previous memory operations globally visible before 771 * a WRMSR. 772 * 773 * MFENCE makes writes visible, but only affects load/store 774 * instructions. WRMSR is unfortunately not a load/store 775 * instruction and is unaffected by MFENCE. The LFENCE ensures 776 * that the WRMSR is not reordered. 777 * 778 * Most WRMSRs are full serializing instructions themselves and 779 * do not require this barrier. This is only required for the 780 * IA32_TSC_DEADLINE and X2APIC MSRs. 781 */ 782 static inline void weak_wrmsr_fence(void) 783 { 784 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 785 } 786 787 #endif /* _ASM_X86_PROCESSOR_H */ 788