1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * dmm32at.c
4 * Diamond Systems Diamond-MM-32-AT Comedi driver
5 *
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 */
9
10 /*
11 * Driver: dmm32at
12 * Description: Diamond Systems Diamond-MM-32-AT
13 * Devices: [Diamond Systems] Diamond-MM-32-AT (dmm32at)
14 * Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
15 * Updated: Fri Jun 4 09:13:24 CDT 2004
16 * Status: experimental
17 *
18 * Configuration Options:
19 * comedi_config /dev/comedi0 dmm32at baseaddr,irq
20 *
21 * This driver is for the Diamond Systems MM-32-AT board
22 * http://www.diamondsystems.com/products/diamondmm32at
23 *
24 * It is being used on several projects inside NASA, without
25 * problems so far. For analog input commands, TRIG_EXT is not
26 * yet supported.
27 */
28
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/comedi/comedidev.h>
33 #include <linux/comedi/comedi_8255.h>
34
35 /* Board register addresses */
36 #define DMM32AT_AI_START_CONV_REG 0x00
37 #define DMM32AT_AI_LSB_REG 0x00
38 #define DMM32AT_AUX_DOUT_REG 0x01
39 #define DMM32AT_AUX_DOUT2 BIT(2) /* J3.42 - OUT2 (OUT2EN) */
40 #define DMM32AT_AUX_DOUT1 BIT(1) /* J3.43 */
41 #define DMM32AT_AUX_DOUT0 BIT(0) /* J3.44 - OUT0 (OUT0EN) */
42 #define DMM32AT_AI_MSB_REG 0x01
43 #define DMM32AT_AI_LO_CHAN_REG 0x02
44 #define DMM32AT_AI_HI_CHAN_REG 0x03
45 #define DMM32AT_AUX_DI_REG 0x04
46 #define DMM32AT_AUX_DI_DACBUSY BIT(7)
47 #define DMM32AT_AUX_DI_CALBUSY BIT(6)
48 #define DMM32AT_AUX_DI3 BIT(3) /* J3.45 - ADCLK (CLKSEL) */
49 #define DMM32AT_AUX_DI2 BIT(2) /* J3.46 - GATE12 (GT12EN) */
50 #define DMM32AT_AUX_DI1 BIT(1) /* J3.47 - GATE0 (GT0EN) */
51 #define DMM32AT_AUX_DI0 BIT(0) /* J3.48 - CLK0 (SRC0) */
52 #define DMM32AT_AO_LSB_REG 0x04
53 #define DMM32AT_AO_MSB_REG 0x05
54 #define DMM32AT_AO_MSB_DACH(x) ((x) << 6)
55 #define DMM32AT_FIFO_DEPTH_REG 0x06
56 #define DMM32AT_FIFO_CTRL_REG 0x07
57 #define DMM32AT_FIFO_CTRL_FIFOEN BIT(3)
58 #define DMM32AT_FIFO_CTRL_SCANEN BIT(2)
59 #define DMM32AT_FIFO_CTRL_FIFORST BIT(1)
60 #define DMM32AT_FIFO_STATUS_REG 0x07
61 #define DMM32AT_FIFO_STATUS_EF BIT(7)
62 #define DMM32AT_FIFO_STATUS_HF BIT(6)
63 #define DMM32AT_FIFO_STATUS_FF BIT(5)
64 #define DMM32AT_FIFO_STATUS_OVF BIT(4)
65 #define DMM32AT_FIFO_STATUS_FIFOEN BIT(3)
66 #define DMM32AT_FIFO_STATUS_SCANEN BIT(2)
67 #define DMM32AT_FIFO_STATUS_PAGE_MASK (3 << 0)
68 #define DMM32AT_CTRL_REG 0x08
69 #define DMM32AT_CTRL_RESETA BIT(5)
70 #define DMM32AT_CTRL_RESETD BIT(4)
71 #define DMM32AT_CTRL_INTRST BIT(3)
72 #define DMM32AT_CTRL_PAGE(x) ((x) << 0)
73 #define DMM32AT_CTRL_PAGE_8254 DMM32AT_CTRL_PAGE(0)
74 #define DMM32AT_CTRL_PAGE_8255 DMM32AT_CTRL_PAGE(1)
75 #define DMM32AT_CTRL_PAGE_CALIB DMM32AT_CTRL_PAGE(3)
76 #define DMM32AT_AI_STATUS_REG 0x08
77 #define DMM32AT_AI_STATUS_STS BIT(7)
78 #define DMM32AT_AI_STATUS_SD1 BIT(6)
79 #define DMM32AT_AI_STATUS_SD0 BIT(5)
80 #define DMM32AT_AI_STATUS_ADCH_MASK (0x1f << 0)
81 #define DMM32AT_INTCLK_REG 0x09
82 #define DMM32AT_INTCLK_ADINT BIT(7)
83 #define DMM32AT_INTCLK_DINT BIT(6)
84 #define DMM32AT_INTCLK_TINT BIT(5)
85 #define DMM32AT_INTCLK_CLKEN BIT(1) /* 1=see below 0=software */
86 #define DMM32AT_INTCLK_CLKSEL BIT(0) /* 1=OUT2 0=EXTCLK */
87 #define DMM32AT_CTRDIO_CFG_REG 0x0a
88 #define DMM32AT_CTRDIO_CFG_FREQ12 BIT(7) /* CLK12 1=100KHz 0=10MHz */
89 #define DMM32AT_CTRDIO_CFG_FREQ0 BIT(6) /* CLK0 1=10KHz 0=10MHz */
90 #define DMM32AT_CTRDIO_CFG_OUT2EN BIT(5) /* J3.42 1=OUT2 is DOUT2 */
91 #define DMM32AT_CTRDIO_CFG_OUT0EN BIT(4) /* J3,44 1=OUT0 is DOUT0 */
92 #define DMM32AT_CTRDIO_CFG_GT0EN BIT(2) /* J3.47 1=DIN1 is GATE0 */
93 #define DMM32AT_CTRDIO_CFG_SRC0 BIT(1) /* CLK0 is 0=FREQ0 1=J3.48 */
94 #define DMM32AT_CTRDIO_CFG_GT12EN BIT(0) /* J3.46 1=DIN2 is GATE12 */
95 #define DMM32AT_AI_CFG_REG 0x0b
96 #define DMM32AT_AI_CFG_SCINT(x) ((x) << 4)
97 #define DMM32AT_AI_CFG_SCINT_20US DMM32AT_AI_CFG_SCINT(0)
98 #define DMM32AT_AI_CFG_SCINT_15US DMM32AT_AI_CFG_SCINT(1)
99 #define DMM32AT_AI_CFG_SCINT_10US DMM32AT_AI_CFG_SCINT(2)
100 #define DMM32AT_AI_CFG_SCINT_5US DMM32AT_AI_CFG_SCINT(3)
101 #define DMM32AT_AI_CFG_RANGE BIT(3) /* 0=5V 1=10V */
102 #define DMM32AT_AI_CFG_ADBU BIT(2) /* 0=bipolar 1=unipolar */
103 #define DMM32AT_AI_CFG_GAIN(x) ((x) << 0)
104 #define DMM32AT_AI_READBACK_REG 0x0b
105 #define DMM32AT_AI_READBACK_WAIT BIT(7) /* DMM32AT_AI_STATUS_STS */
106 #define DMM32AT_AI_READBACK_RANGE BIT(3)
107 #define DMM32AT_AI_READBACK_ADBU BIT(2)
108 #define DMM32AT_AI_READBACK_GAIN_MASK (3 << 0)
109
110 #define DMM32AT_CLK1 0x0d
111 #define DMM32AT_CLK2 0x0e
112 #define DMM32AT_CLKCT 0x0f
113
114 #define DMM32AT_8255_IOBASE 0x0c /* Page 1 registers */
115
116 /* Board register values. */
117
118 /* DMM32AT_AI_CFG_REG 0x0b */
119 #define DMM32AT_RANGE_U10 0x0c
120 #define DMM32AT_RANGE_U5 0x0d
121 #define DMM32AT_RANGE_B10 0x08
122 #define DMM32AT_RANGE_B5 0x00
123
124 /* DMM32AT_CLKCT 0x0f */
125 #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
126 #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
127
128 /* board AI ranges in comedi structure */
129 static const struct comedi_lrange dmm32at_airanges = {
130 4, {
131 UNI_RANGE(10),
132 UNI_RANGE(5),
133 BIP_RANGE(10),
134 BIP_RANGE(5)
135 }
136 };
137
138 /* register values for above ranges */
139 static const unsigned char dmm32at_rangebits[] = {
140 DMM32AT_RANGE_U10,
141 DMM32AT_RANGE_U5,
142 DMM32AT_RANGE_B10,
143 DMM32AT_RANGE_B5,
144 };
145
146 /* only one of these ranges is valid, as set by a jumper on the
147 * board. The application should only use the range set by the jumper
148 */
149 static const struct comedi_lrange dmm32at_aoranges = {
150 4, {
151 UNI_RANGE(10),
152 UNI_RANGE(5),
153 BIP_RANGE(10),
154 BIP_RANGE(5)
155 }
156 };
157
dmm32at_ai_set_chanspec(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec,int nchan)158 static void dmm32at_ai_set_chanspec(struct comedi_device *dev,
159 struct comedi_subdevice *s,
160 unsigned int chanspec, int nchan)
161 {
162 unsigned int chan = CR_CHAN(chanspec);
163 unsigned int range = CR_RANGE(chanspec);
164 unsigned int last_chan = (chan + nchan - 1) % s->n_chan;
165
166 outb(DMM32AT_FIFO_CTRL_FIFORST, dev->iobase + DMM32AT_FIFO_CTRL_REG);
167
168 if (nchan > 1)
169 outb(DMM32AT_FIFO_CTRL_SCANEN,
170 dev->iobase + DMM32AT_FIFO_CTRL_REG);
171
172 outb(chan, dev->iobase + DMM32AT_AI_LO_CHAN_REG);
173 outb(last_chan, dev->iobase + DMM32AT_AI_HI_CHAN_REG);
174 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AI_CFG_REG);
175 }
176
dmm32at_ai_get_sample(struct comedi_device * dev,struct comedi_subdevice * s)177 static unsigned int dmm32at_ai_get_sample(struct comedi_device *dev,
178 struct comedi_subdevice *s)
179 {
180 unsigned int val;
181
182 val = inb(dev->iobase + DMM32AT_AI_LSB_REG);
183 val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8);
184
185 /* munge two's complement value to offset binary */
186 return comedi_offset_munge(s, val);
187 }
188
dmm32at_ai_status(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned long context)189 static int dmm32at_ai_status(struct comedi_device *dev,
190 struct comedi_subdevice *s,
191 struct comedi_insn *insn,
192 unsigned long context)
193 {
194 unsigned char status;
195
196 status = inb(dev->iobase + context);
197 if ((status & DMM32AT_AI_STATUS_STS) == 0)
198 return 0;
199 return -EBUSY;
200 }
201
dmm32at_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)202 static int dmm32at_ai_insn_read(struct comedi_device *dev,
203 struct comedi_subdevice *s,
204 struct comedi_insn *insn,
205 unsigned int *data)
206 {
207 int ret;
208 int i;
209
210 dmm32at_ai_set_chanspec(dev, s, insn->chanspec, 1);
211
212 /* wait for circuit to settle */
213 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status,
214 DMM32AT_AI_READBACK_REG);
215 if (ret)
216 return ret;
217
218 for (i = 0; i < insn->n; i++) {
219 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
220
221 ret = comedi_timeout(dev, s, insn, dmm32at_ai_status,
222 DMM32AT_AI_STATUS_REG);
223 if (ret)
224 return ret;
225
226 data[i] = dmm32at_ai_get_sample(dev, s);
227 }
228
229 return insn->n;
230 }
231
dmm32at_ai_check_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)232 static int dmm32at_ai_check_chanlist(struct comedi_device *dev,
233 struct comedi_subdevice *s,
234 struct comedi_cmd *cmd)
235 {
236 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
237 unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
238 int i;
239
240 for (i = 1; i < cmd->chanlist_len; i++) {
241 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
242 unsigned int range = CR_RANGE(cmd->chanlist[i]);
243
244 if (chan != (chan0 + i) % s->n_chan) {
245 dev_dbg(dev->class_dev,
246 "entries in chanlist must be consecutive channels, counting upwards\n");
247 return -EINVAL;
248 }
249 if (range != range0) {
250 dev_dbg(dev->class_dev,
251 "entries in chanlist must all have the same gain\n");
252 return -EINVAL;
253 }
254 }
255
256 return 0;
257 }
258
dmm32at_ai_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)259 static int dmm32at_ai_cmdtest(struct comedi_device *dev,
260 struct comedi_subdevice *s,
261 struct comedi_cmd *cmd)
262 {
263 int err = 0;
264 unsigned int arg;
265
266 /* Step 1 : check if triggers are trivially valid */
267
268 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
269 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
270 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
271 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
272 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
273
274 if (err)
275 return 1;
276
277 /* Step 2a : make sure trigger sources are unique */
278
279 err |= comedi_check_trigger_is_unique(cmd->stop_src);
280
281 /* Step 2b : and mutually compatible */
282
283 if (err)
284 return 2;
285
286 /* Step 3: check if arguments are trivially valid */
287
288 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
289
290 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, 1000000);
291 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 1000000000);
292
293 if (cmd->convert_arg >= 17500)
294 cmd->convert_arg = 20000;
295 else if (cmd->convert_arg >= 12500)
296 cmd->convert_arg = 15000;
297 else if (cmd->convert_arg >= 7500)
298 cmd->convert_arg = 10000;
299 else
300 cmd->convert_arg = 5000;
301
302 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
303 cmd->chanlist_len);
304
305 if (cmd->stop_src == TRIG_COUNT)
306 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
307 else /* TRIG_NONE */
308 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
309
310 if (err)
311 return 3;
312
313 /* Step 4: fix up any arguments */
314
315 arg = cmd->convert_arg * cmd->scan_end_arg;
316 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, arg);
317
318 if (err)
319 return 4;
320
321 /* Step 5: check channel list if it exists */
322 if (cmd->chanlist && cmd->chanlist_len > 0)
323 err |= dmm32at_ai_check_chanlist(dev, s, cmd);
324
325 if (err)
326 return 5;
327
328 return 0;
329 }
330
dmm32at_setaitimer(struct comedi_device * dev,unsigned int nansec)331 static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
332 {
333 unsigned long irq_flags;
334 unsigned char lo1, lo2, hi2;
335 unsigned short both2;
336
337 /* based on 10mhz clock */
338 lo1 = 200;
339 both2 = nansec / 20000;
340 hi2 = (both2 & 0xff00) >> 8;
341 lo2 = both2 & 0x00ff;
342
343 /* set counter clocks to 10MHz, disable all aux dio */
344 outb(0, dev->iobase + DMM32AT_CTRDIO_CFG_REG);
345
346 /* serialize access to control register and paged registers */
347 spin_lock_irqsave(&dev->spinlock, irq_flags);
348
349 /* get access to the clock regs */
350 outb(DMM32AT_CTRL_PAGE_8254, dev->iobase + DMM32AT_CTRL_REG);
351
352 /* write the counter 1 control word and low byte to counter */
353 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
354 outb(lo1, dev->iobase + DMM32AT_CLK1);
355
356 /* write the counter 2 control word and low byte then to counter */
357 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
358 outb(lo2, dev->iobase + DMM32AT_CLK2);
359 outb(hi2, dev->iobase + DMM32AT_CLK2);
360
361 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
362
363 /* enable the ai conversion interrupt and the clock to start scans */
364 outb(DMM32AT_INTCLK_ADINT |
365 DMM32AT_INTCLK_CLKEN | DMM32AT_INTCLK_CLKSEL,
366 dev->iobase + DMM32AT_INTCLK_REG);
367 }
368
dmm32at_ai_cmd(struct comedi_device * dev,struct comedi_subdevice * s)369 static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
370 {
371 struct comedi_cmd *cmd = &s->async->cmd;
372 unsigned long irq_flags;
373 int ret;
374
375 dmm32at_ai_set_chanspec(dev, s, cmd->chanlist[0], cmd->chanlist_len);
376
377 /* serialize access to control register and paged registers */
378 spin_lock_irqsave(&dev->spinlock, irq_flags);
379
380 /* reset the interrupt just in case */
381 outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG);
382
383 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
384
385 /*
386 * wait for circuit to settle
387 * we don't have the 'insn' here but it's not needed
388 */
389 ret = comedi_timeout(dev, s, NULL, dmm32at_ai_status,
390 DMM32AT_AI_READBACK_REG);
391 if (ret)
392 return ret;
393
394 if (cmd->stop_src == TRIG_NONE || cmd->stop_arg > 1) {
395 /* start the clock and enable the interrupts */
396 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
397 } else {
398 /* start the interrupts and initiate a single scan */
399 outb(DMM32AT_INTCLK_ADINT, dev->iobase + DMM32AT_INTCLK_REG);
400 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
401 }
402
403 return 0;
404 }
405
dmm32at_ai_cancel(struct comedi_device * dev,struct comedi_subdevice * s)406 static int dmm32at_ai_cancel(struct comedi_device *dev,
407 struct comedi_subdevice *s)
408 {
409 /* disable further interrupts and clocks */
410 outb(0x0, dev->iobase + DMM32AT_INTCLK_REG);
411 return 0;
412 }
413
dmm32at_isr(int irq,void * d)414 static irqreturn_t dmm32at_isr(int irq, void *d)
415 {
416 struct comedi_device *dev = d;
417 unsigned char intstat;
418 unsigned short val;
419 int i;
420
421 if (!dev->attached) {
422 dev_err(dev->class_dev, "spurious interrupt\n");
423 return IRQ_HANDLED;
424 }
425
426 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG);
427
428 if (intstat & DMM32AT_INTCLK_ADINT) {
429 struct comedi_subdevice *s = dev->read_subdev;
430 struct comedi_cmd *cmd = &s->async->cmd;
431
432 for (i = 0; i < cmd->chanlist_len; i++) {
433 val = dmm32at_ai_get_sample(dev, s);
434 comedi_buf_write_samples(s, &val, 1);
435 }
436
437 if (cmd->stop_src == TRIG_COUNT &&
438 s->async->scans_done >= cmd->stop_arg)
439 s->async->events |= COMEDI_CB_EOA;
440
441 comedi_handle_events(dev, s);
442 }
443
444 /* serialize access to control register and paged registers */
445 spin_lock(&dev->spinlock);
446
447 /* reset the interrupt */
448 outb(DMM32AT_CTRL_INTRST, dev->iobase + DMM32AT_CTRL_REG);
449
450 spin_unlock(&dev->spinlock);
451 return IRQ_HANDLED;
452 }
453
dmm32at_ao_eoc(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned long context)454 static int dmm32at_ao_eoc(struct comedi_device *dev,
455 struct comedi_subdevice *s,
456 struct comedi_insn *insn,
457 unsigned long context)
458 {
459 unsigned char status;
460
461 status = inb(dev->iobase + DMM32AT_AUX_DI_REG);
462 if ((status & DMM32AT_AUX_DI_DACBUSY) == 0)
463 return 0;
464 return -EBUSY;
465 }
466
dmm32at_ao_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)467 static int dmm32at_ao_insn_write(struct comedi_device *dev,
468 struct comedi_subdevice *s,
469 struct comedi_insn *insn,
470 unsigned int *data)
471 {
472 unsigned int chan = CR_CHAN(insn->chanspec);
473 int i;
474
475 for (i = 0; i < insn->n; i++) {
476 unsigned int val = data[i];
477 int ret;
478
479 /* write LSB then MSB + chan to load DAC */
480 outb(val & 0xff, dev->iobase + DMM32AT_AO_LSB_REG);
481 outb((val >> 8) | DMM32AT_AO_MSB_DACH(chan),
482 dev->iobase + DMM32AT_AO_MSB_REG);
483
484 /* wait for circuit to settle */
485 ret = comedi_timeout(dev, s, insn, dmm32at_ao_eoc, 0);
486 if (ret)
487 return ret;
488
489 /* dummy read to update DAC */
490 inb(dev->iobase + DMM32AT_AO_MSB_REG);
491
492 s->readback[chan] = val;
493 }
494
495 return insn->n;
496 }
497
dmm32at_8255_io(struct comedi_device * dev,int dir,int port,int data,unsigned long regbase)498 static int dmm32at_8255_io(struct comedi_device *dev,
499 int dir, int port, int data, unsigned long regbase)
500 {
501 unsigned long irq_flags;
502 int ret;
503
504 /* serialize access to control register and paged registers */
505 spin_lock_irqsave(&dev->spinlock, irq_flags);
506
507 /* get access to the DIO regs */
508 outb(DMM32AT_CTRL_PAGE_8255, dev->iobase + DMM32AT_CTRL_REG);
509
510 if (dir) {
511 outb(data, dev->iobase + regbase + port);
512 ret = 0;
513 } else {
514 ret = inb(dev->iobase + regbase + port);
515 }
516
517 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
518
519 return ret;
520 }
521
522 /* Make sure the board is there and put it to a known state */
dmm32at_reset(struct comedi_device * dev)523 static int dmm32at_reset(struct comedi_device *dev)
524 {
525 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
526
527 /* reset the board */
528 outb(DMM32AT_CTRL_RESETA, dev->iobase + DMM32AT_CTRL_REG);
529
530 /* allow a millisecond to reset */
531 usleep_range(1000, 3000);
532
533 /* zero scan and fifo control */
534 outb(0x0, dev->iobase + DMM32AT_FIFO_CTRL_REG);
535
536 /* zero interrupt and clock control */
537 outb(0x0, dev->iobase + DMM32AT_INTCLK_REG);
538
539 /* write a test channel range, the high 3 bits should drop */
540 outb(0x80, dev->iobase + DMM32AT_AI_LO_CHAN_REG);
541 outb(0xff, dev->iobase + DMM32AT_AI_HI_CHAN_REG);
542
543 /* set the range at 10v unipolar */
544 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AI_CFG_REG);
545
546 /* should take 10 us to settle, here's a hundred */
547 usleep_range(100, 200);
548
549 /* read back the values */
550 ailo = inb(dev->iobase + DMM32AT_AI_LO_CHAN_REG);
551 aihi = inb(dev->iobase + DMM32AT_AI_HI_CHAN_REG);
552 fifostat = inb(dev->iobase + DMM32AT_FIFO_STATUS_REG);
553 aistat = inb(dev->iobase + DMM32AT_AI_STATUS_REG);
554 intstat = inb(dev->iobase + DMM32AT_INTCLK_REG);
555 airback = inb(dev->iobase + DMM32AT_AI_READBACK_REG);
556
557 /*
558 * NOTE: The (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0)
559 * test makes this driver only work if the board is configured
560 * with all A/D channels set for single-ended operation.
561 */
562 if (ailo != 0x00 || aihi != 0x1f ||
563 fifostat != DMM32AT_FIFO_STATUS_EF ||
564 aistat != (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) ||
565 intstat != 0x00 || airback != 0x0c)
566 return -EIO;
567
568 return 0;
569 }
570
dmm32at_attach(struct comedi_device * dev,struct comedi_devconfig * it)571 static int dmm32at_attach(struct comedi_device *dev,
572 struct comedi_devconfig *it)
573 {
574 struct comedi_subdevice *s;
575 int ret;
576
577 ret = comedi_request_region(dev, it->options[0], 0x10);
578 if (ret)
579 return ret;
580
581 ret = dmm32at_reset(dev);
582 if (ret) {
583 dev_err(dev->class_dev, "board detection failed\n");
584 return ret;
585 }
586
587 if (it->options[1]) {
588 ret = request_irq(it->options[1], dmm32at_isr, 0,
589 dev->board_name, dev);
590 if (ret == 0)
591 dev->irq = it->options[1];
592 }
593
594 ret = comedi_alloc_subdevices(dev, 3);
595 if (ret)
596 return ret;
597
598 /* Analog Input subdevice */
599 s = &dev->subdevices[0];
600 s->type = COMEDI_SUBD_AI;
601 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
602 s->n_chan = 32;
603 s->maxdata = 0xffff;
604 s->range_table = &dmm32at_airanges;
605 s->insn_read = dmm32at_ai_insn_read;
606 if (dev->irq) {
607 dev->read_subdev = s;
608 s->subdev_flags |= SDF_CMD_READ;
609 s->len_chanlist = s->n_chan;
610 s->do_cmd = dmm32at_ai_cmd;
611 s->do_cmdtest = dmm32at_ai_cmdtest;
612 s->cancel = dmm32at_ai_cancel;
613 }
614
615 /* Analog Output subdevice */
616 s = &dev->subdevices[1];
617 s->type = COMEDI_SUBD_AO;
618 s->subdev_flags = SDF_WRITABLE;
619 s->n_chan = 4;
620 s->maxdata = 0x0fff;
621 s->range_table = &dmm32at_aoranges;
622 s->insn_write = dmm32at_ao_insn_write;
623
624 ret = comedi_alloc_subdev_readback(s);
625 if (ret)
626 return ret;
627
628 /* Digital I/O subdevice */
629 s = &dev->subdevices[2];
630 return subdev_8255_cb_init(dev, s, dmm32at_8255_io,
631 DMM32AT_8255_IOBASE);
632 }
633
634 static struct comedi_driver dmm32at_driver = {
635 .driver_name = "dmm32at",
636 .module = THIS_MODULE,
637 .attach = dmm32at_attach,
638 .detach = comedi_legacy_detach,
639 };
640 module_comedi_driver(dmm32at_driver);
641
642 MODULE_AUTHOR("Comedi https://www.comedi.org");
643 MODULE_DESCRIPTION("Comedi: Diamond Systems Diamond-MM-32-AT");
644 MODULE_LICENSE("GPL");
645