1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8dxl.dtsi" 9 10/ { 11 model = "Freescale i.MX8DXL EVK"; 12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; 13 14 aliases { 15 i2c2 = &i2c2; 16 mmc0 = &usdhc1; 17 mmc1 = &usdhc2; 18 serial0 = &lpuart0; 19 serial1 = &lpuart1; 20 serial6 = &cm40_lpuart; 21 }; 22 23 chosen { 24 stdout-path = &lpuart0; 25 }; 26 27 imx8dxl-cm4 { 28 compatible = "fsl,imx8qxp-cm4"; 29 clocks = <&clk_dummy>; 30 mbox-names = "tx", "rx", "rxdb"; 31 mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; 32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 33 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 36 fsl,entry-address = <0x34fe0000>; 37 }; 38 39 40 memory@80000000 { 41 device_type = "memory"; 42 reg = <0x00000000 0x80000000 0 0x40000000>; 43 }; 44 45 reserved-memory { 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 /* 51 * Memory reserved for optee usage. Please do not use. 52 * This will be automatically added to dtb if OP-TEE is installed. 53 * optee@96000000 { 54 * reg = <0 0x96000000 0 0x2000000>; 55 * no-map; 56 * }; 57 */ 58 59 /* global autoconfigured region for contiguous allocations */ 60 linux,cma { 61 compatible = "shared-dma-pool"; 62 reusable; 63 size = <0 0x14000000>; 64 alloc-ranges = <0 0x98000000 0 0x14000000>; 65 linux,cma-default; 66 }; 67 68 vdev0vring0: memory0@90000000 { 69 reg = <0 0x90000000 0 0x8000>; 70 no-map; 71 }; 72 73 vdev0vring1: memory@90008000 { 74 reg = <0 0x90008000 0 0x8000>; 75 no-map; 76 }; 77 78 vdev1vring0: memory@90010000 { 79 reg = <0 0x90010000 0 0x8000>; 80 no-map; 81 }; 82 83 vdev1vring1: memory@90018000 { 84 reg = <0 0x90018000 0 0x8000>; 85 no-map; 86 }; 87 88 rsc_table: memory-rsc-table@900ff000 { 89 reg = <0 0x900ff000 0 0x1000>; 90 no-map; 91 }; 92 93 vdevbuffer: memory-vdevbuffer@90400000 { 94 compatible = "shared-dma-pool"; 95 reg = <0 0x90400000 0 0x100000>; 96 no-map; 97 }; 98 }; 99 100 m2_uart1_sel: regulator-m2uart1sel { 101 compatible = "regulator-fixed"; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 regulator-name = "m2_uart1_sel"; 105 gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 regulator-always-on; 108 }; 109 110 mux3_en: regulator-0 { 111 compatible = "regulator-fixed"; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 regulator-name = "mux3_en"; 115 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>; 116 regulator-always-on; 117 }; 118 119 reg_fec1_sel: regulator-1 { 120 compatible = "regulator-fixed"; 121 regulator-name = "fec1_supply"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; 125 regulator-always-on; 126 status = "disabled"; 127 }; 128 129 reg_fec1_io: regulator-2 { 130 compatible = "regulator-fixed"; 131 regulator-name = "fec1_io_supply"; 132 regulator-min-microvolt = <1800000>; 133 regulator-max-microvolt = <1800000>; 134 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 135 enable-active-high; 136 regulator-always-on; 137 status = "disabled"; 138 }; 139 140 reg_can0_stby: regulator-4 { 141 compatible = "regulator-fixed"; 142 regulator-name = "can0-stby"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; 146 enable-active-high; 147 }; 148 149 reg_can1_stby: regulator-5 { 150 compatible = "regulator-fixed"; 151 regulator-name = "can1-stby"; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; 155 enable-active-high; 156 }; 157 158 reg_usdhc2_vmmc: regulator-3 { 159 compatible = "regulator-fixed"; 160 regulator-name = "SD1_SPWR"; 161 regulator-min-microvolt = <3000000>; 162 regulator-max-microvolt = <3000000>; 163 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; 164 enable-active-high; 165 off-on-delay-us = <3480>; 166 }; 167 168 reg_vref_1v8: regulator-adc-vref { 169 compatible = "regulator-fixed"; 170 regulator-name = "vref_1v8"; 171 regulator-min-microvolt = <1800000>; 172 regulator-max-microvolt = <1800000>; 173 }; 174 175 mii_select: regulator-4 { 176 compatible = "regulator-fixed"; 177 regulator-name = "mii-select"; 178 regulator-min-microvolt = <3300000>; 179 regulator-max-microvolt = <3300000>; 180 gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>; 181 enable-active-high; 182 regulator-always-on; 183 }; 184 185 reg_pcieb: regulator-pcieb { 186 compatible = "regulator-fixed"; 187 regulator-max-microvolt = <3300000>; 188 regulator-min-microvolt = <3300000>; 189 regulator-name = "reg_pcieb"; 190 gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; 191 enable-active-high; 192 }; 193 194 reg_audio_5v: regulator-audio-pwr { 195 compatible = "regulator-fixed"; 196 regulator-name = "audio-5v"; 197 regulator-min-microvolt = <5000000>; 198 regulator-max-microvolt = <5000000>; 199 regulator-always-on; 200 regulator-boot-on; 201 }; 202 203 reg_audio_3v3: regulator-audio-3v3 { 204 compatible = "regulator-fixed"; 205 regulator-name = "audio-3v3"; 206 regulator-min-microvolt = <3300000>; 207 regulator-max-microvolt = <3300000>; 208 regulator-always-on; 209 regulator-boot-on; 210 }; 211 212 reg_audio_1v8: regulator-audio-1v8 { 213 compatible = "regulator-fixed"; 214 regulator-name = "audio-1v8"; 215 regulator-min-microvolt = <1800000>; 216 regulator-max-microvolt = <1800000>; 217 regulator-always-on; 218 regulator-boot-on; 219 }; 220 221 bt_sco_codec: audio-codec-bt { 222 compatible = "linux,bt-sco"; 223 #sound-dai-cells = <1>; 224 }; 225 226 sound-bt-sco { 227 compatible = "simple-audio-card"; 228 simple-audio-card,name = "bt-sco-audio"; 229 simple-audio-card,format = "dsp_a"; 230 simple-audio-card,bitclock-inversion; 231 simple-audio-card,frame-master = <&btcpu>; 232 simple-audio-card,bitclock-master = <&btcpu>; 233 234 btcpu: simple-audio-card,cpu { 235 sound-dai = <&sai0>; 236 dai-tdm-slot-num = <2>; 237 dai-tdm-slot-width = <16>; 238 }; 239 240 simple-audio-card,codec { 241 sound-dai = <&bt_sco_codec 1>; 242 }; 243 }; 244 245 sound-wm8960-1 { 246 compatible = "fsl,imx-audio-wm8960"; 247 model = "wm8960-audio"; 248 audio-cpu = <&sai1>; 249 audio-codec = <&wm8960_1>; 250 audio-asrc = <&asrc0>; 251 audio-routing = "Headphone Jack", "HP_L", 252 "Headphone Jack", "HP_R", 253 "Ext Spk", "SPK_LP", 254 "Ext Spk", "SPK_LN", 255 "Ext Spk", "SPK_RP", 256 "Ext Spk", "SPK_RN", 257 "LINPUT1", "Mic Jack", 258 "Mic Jack", "MICB"; 259 }; 260 261 sound-wm8960-2 { 262 compatible = "fsl,imx-audio-wm8960"; 263 model = "wm8960-audio-2"; 264 audio-cpu = <&sai2>; 265 audio-codec = <&wm8960_2>; 266 audio-routing = "Headphone Jack", "HP_L", 267 "Headphone Jack", "HP_R", 268 "Ext Spk", "SPK_LP", 269 "Ext Spk", "SPK_LN", 270 "Ext Spk", "SPK_RP", 271 "Ext Spk", "SPK_RN", 272 "LINPUT1", "Mic Jack", 273 "Mic Jack", "MICB"; 274 }; 275 276 sound-wm8960-3 { 277 compatible = "fsl,imx-audio-wm8960"; 278 model = "wm8960-audio-3"; 279 audio-cpu = <&sai3>; 280 audio-codec = <&wm8960_3>; 281 audio-routing = "Headphone Jack", "HP_L", 282 "Headphone Jack", "HP_R", 283 "Ext Spk", "SPK_LP", 284 "Ext Spk", "SPK_LN", 285 "Ext Spk", "SPK_RP", 286 "Ext Spk", "SPK_RN", 287 "LINPUT1", "Mic Jack", 288 "Mic Jack", "MICB"; 289 }; 290}; 291 292&adc0 { 293 vref-supply = <®_vref_1v8>; 294 status = "okay"; 295}; 296 297&asrc0 { 298 fsl,asrc-rate = <48000>; 299 status = "okay"; 300}; 301 302&eqos { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_eqos>; 305 phy-mode = "rgmii-id"; 306 phy-handle = <ðphy0>; 307 nvmem-cells = <&fec_mac1>; 308 nvmem-cell-names = "mac-address"; 309 status = "okay"; 310 311 mdio { 312 compatible = "snps,dwmac-mdio"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 316 ethphy0: ethernet-phy@0 { 317 compatible = "ethernet-phy-ieee802.3-c22"; 318 reg = <0>; 319 eee-broken-1000t; 320 qca,disable-smarteee; 321 qca,disable-hibernation-mode; 322 reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; 323 reset-assert-us = <20>; 324 reset-deassert-us = <200000>; 325 vddio-supply = <&vddio0>; 326 327 vddio0: vddio-regulator { 328 regulator-min-microvolt = <1800000>; 329 regulator-max-microvolt = <1800000>; 330 }; 331 }; 332 }; 333}; 334 335/* 336 * fec1 shares the some PINs with usdhc2. 337 * by default usdhc2 is enabled in this dts. 338 * Please disable usdhc2 to enable fec1 339 */ 340&fec1 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_fec1>; 343 phy-mode = "rgmii-txid"; 344 phy-handle = <ðphy1>; 345 fsl,magic-packet; 346 rx-internal-delay-ps = <2000>; 347 nvmem-cells = <&fec_mac0>; 348 nvmem-cell-names = "mac-address"; 349 status = "disabled"; 350 351 mdio { 352 #address-cells = <1>; 353 #size-cells = <0>; 354 355 ethphy1: ethernet-phy@1 { 356 compatible = "ethernet-phy-ieee802.3-c22"; 357 reg = <1>; 358 reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; 359 reset-assert-us = <10000>; 360 qca,disable-smarteee; 361 vddio-supply = <&vddio1>; 362 363 vddio1: vddio-regulator { 364 regulator-min-microvolt = <1800000>; 365 regulator-max-microvolt = <1800000>; 366 }; 367 }; 368 }; 369}; 370 371&flexspi0 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_flexspi0>; 374 status = "okay"; 375 376 mt35xu512aba0: flash@0 { 377 reg = <0>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 compatible = "jedec,spi-nor"; 381 spi-max-frequency = <133000000>; 382 spi-tx-bus-width = <8>; 383 spi-rx-bus-width = <8>; 384 }; 385}; 386 387&i2c2 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 clock-frequency = <100000>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_i2c2>; 393 status = "okay"; 394 395 pca6416_1: gpio@20 { 396 compatible = "ti,tca6416"; 397 reg = <0x20>; 398 gpio-controller; 399 #gpio-cells = <2>; 400 }; 401 402 pca6416_2: gpio@21 { 403 compatible = "ti,tca6416"; 404 reg = <0x21>; 405 gpio-controller; 406 #gpio-cells = <2>; 407 }; 408 409 pca9548_1: i2c-mux@70 { 410 compatible = "nxp,pca9548"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0x70>; 414 415 i2c@0 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <0x0>; 419 420 max7322: gpio@68 { 421 compatible = "maxim,max7322"; 422 reg = <0x68>; 423 gpio-controller; 424 #gpio-cells = <2>; 425 status = "disabled"; 426 }; 427 }; 428 429 i2c@1 { 430 #address-cells = <1>; 431 #size-cells = <0>; 432 reg = <0x1>; 433 434 wm8960_1: audio-codec@1a { 435 compatible = "wlf,wm8960"; 436 reg = <0x1a>; 437 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 438 clock-names = "mclk"; 439 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 440 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 441 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 442 <&mclkout1_lpcg IMX_LPCG_CLK_0>; 443 assigned-clock-rates = <786432000>, 444 <49152000>, 445 <12288000>, 446 <12288000>; 447 wlf,shared-lrclk; 448 wlf,hp-cfg = <2 2 3>; 449 wlf,gpio-cfg = <1 3>; 450 AVDD-supply = <®_audio_3v3>; 451 DBVDD-supply = <®_audio_1v8>; 452 DCVDD-supply = <®_audio_1v8>; 453 SPKVDD1-supply = <®_audio_5v>; 454 SPKVDD2-supply = <®_audio_5v>; 455 }; 456 }; 457 458 i2c@2 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0x2>; 462 463 wm8960_2: audio-codec@1a { 464 compatible = "wlf,wm8960"; 465 reg = <0x1a>; 466 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 467 clock-names = "mclk"; 468 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 469 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 470 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 471 <&mclkout1_lpcg IMX_LPCG_CLK_0>; 472 assigned-clock-rates = <786432000>, 473 <49152000>, 474 <12288000>, 475 <12288000>; 476 wlf,shared-lrclk; 477 wlf,hp-cfg = <2 2 3>; 478 wlf,gpio-cfg = <1 3>; 479 AVDD-supply = <®_audio_3v3>; 480 DBVDD-supply = <®_audio_1v8>; 481 DCVDD-supply = <®_audio_1v8>; 482 SPKVDD1-supply = <®_audio_5v>; 483 SPKVDD2-supply = <®_audio_5v>; 484 }; 485 }; 486 487 i2c@3 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 reg = <0x3>; 491 492 wm8960_3: audio-codec@1a { 493 compatible = "wlf,wm8960"; 494 reg = <0x1a>; 495 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 496 clock-names = "mclk"; 497 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 498 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 499 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 500 <&mclkout1_lpcg IMX_LPCG_CLK_0>; 501 assigned-clock-rates = <786432000>, 502 <49152000>, 503 <12288000>, 504 <12288000>; 505 wlf,shared-lrclk; 506 wlf,hp-cfg = <2 2 3>; 507 wlf,gpio-cfg = <1 3>; 508 AVDD-supply = <®_audio_3v3>; 509 DBVDD-supply = <®_audio_1v8>; 510 DCVDD-supply = <®_audio_1v8>; 511 SPKVDD1-supply = <®_audio_5v>; 512 SPKVDD2-supply = <®_audio_5v>; 513 }; 514 }; 515 516 i2c@4 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <0x4>; 520 }; 521 522 i2c@5 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 reg = <0x5>; 526 }; 527 528 i2c@6 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0x6>; 532 }; 533 }; 534}; 535 536&i2c3 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 clock-frequency = <100000>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_i2c3>; 542 status = "okay"; 543 544 pca6416_3: gpio@20 { 545 compatible = "ti,tca6416"; 546 reg = <0x20>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-parent = <&lsio_gpio2>; 550 interrupts = <5 IRQ_TYPE_EDGE_RISING>; 551 }; 552 553 pca9548_2: i2c-mux@70 { 554 compatible = "nxp,pca9548"; 555 reg = <0x70>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 i2c@0 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <0x0>; 563 }; 564 565 i2c@1 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 reg = <0x1>; 569 }; 570 571 i2c@2 { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 reg = <0x2>; 575 }; 576 577 i2c@3 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 reg = <0x3>; 581 }; 582 583 i2c@4 { 584 #address-cells = <1>; 585 #size-cells = <0>; 586 reg = <0x4>; 587 }; 588 }; 589}; 590 591&lpuart0 { 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_lpuart0>; 594 status = "okay"; 595}; 596 597&lpuart1 { 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_lpuart1>; 600 status = "okay"; 601}; 602 603&lsio_mu5 { 604 status = "okay"; 605}; 606 607&flexcan2 { 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pinctrl_flexcan2>; 610 xceiver-supply = <®_can0_stby>; 611 status = "okay"; 612}; 613 614&flexcan3 { 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pinctrl_flexcan3>; 617 xceiver-supply = <®_can1_stby>; 618 status = "okay"; 619}; 620 621&hsio_phy { 622 fsl,hsio-cfg = "pciea-x2-pcieb"; 623 fsl,refclk-pad-mode = "output"; 624 status = "okay"; 625}; 626 627&cm40_intmux { 628 status = "disabled"; 629}; 630 631&cm40_lpuart { 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_cm40_lpuart>; 634 status = "disabled"; 635}; 636 637&lsio_gpio4 { 638 status = "okay"; 639}; 640 641&lsio_gpio5 { 642 status = "okay"; 643}; 644 645&pcie0 { 646 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 647 phy-names = "pcie-phy"; 648 pinctrl-0 = <&pinctrl_pcieb>; 649 pinctrl-names = "default"; 650 reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 651 vpcie-supply = <®_pcieb>; 652 status = "okay"; 653}; 654 655&pcie0_ep{ 656 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 657 phy-names = "pcie-phy"; 658 pinctrl-0 = <&pinctrl_pcieb>; 659 pinctrl-names = "default"; 660 reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 661 vpcie-supply = <®_pcieb>; 662 status = "disabled"; 663}; 664 665&sai0 { 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_sai0>; 668 #sound-dai-cells = <0>; 669 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 670 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 671 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 672 <&sai0_lpcg IMX_LPCG_CLK_0>; 673 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 674 status = "okay"; 675}; 676 677&sai1 { 678 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 679 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 680 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 681 <&sai1_lpcg IMX_LPCG_CLK_0>; 682 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_sai1>; 685 status = "okay"; 686}; 687 688&sai2 { 689 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 690 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 691 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 692 <&sai2_lpcg IMX_LPCG_CLK_0>; 693 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&pinctrl_sai2>; 696 fsl,sai-asynchronous; 697 status = "okay"; 698}; 699 700&sai3 { 701 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 702 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 703 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 704 <&sai3_lpcg IMX_LPCG_CLK_0>; 705 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_sai3>; 708 fsl,sai-asynchronous; 709 status = "okay"; 710}; 711 712&thermal_zones { 713 pmic-thermal { 714 polling-delay-passive = <250>; 715 polling-delay = <2000>; 716 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 717 718 trips { 719 pmic_alert0: trip0 { 720 temperature = <110000>; 721 hysteresis = <2000>; 722 type = "passive"; 723 }; 724 725 pmic_crit0: trip1 { 726 temperature = <125000>; 727 hysteresis = <2000>; 728 type = "critical"; 729 }; 730 }; 731 732 cooling-maps { 733 map0 { 734 trip = <&pmic_alert0>; 735 cooling-device = 736 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 737 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 738 }; 739 }; 740 }; 741}; 742 743&usbphy1 { 744 /* USB eye diagram tests result */ 745 fsl,tx-d-cal = <114>; 746 status = "okay"; 747}; 748 749&usbotg1 { 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pinctrl_usbotg1>; 752 srp-disable; 753 hnp-disable; 754 adp-disable; 755 power-active-high; 756 disable-over-current; 757 status = "okay"; 758}; 759 760&usbphy2 { 761 /* USB eye diagram tests result */ 762 fsl,tx-d-cal = <111>; 763 status = "okay"; 764}; 765 766&usbotg2 { 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pinctrl_usbotg2>; 769 srp-disable; 770 hnp-disable; 771 adp-disable; 772 power-active-high; 773 disable-over-current; 774 status = "okay"; 775}; 776 777&usdhc1 { 778 pinctrl-names = "default"; 779 pinctrl-0 = <&pinctrl_usdhc1>; 780 bus-width = <8>; 781 no-sd; 782 no-sdio; 783 non-removable; 784 status = "okay"; 785}; 786 787&usdhc2 { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 790 bus-width = <4>; 791 vmmc-supply = <®_usdhc2_vmmc>; 792 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; 793 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; 794 status = "okay"; 795}; 796 797&lpspi3 { 798 fsl,spi-only-use-cs1-sel; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_lpspi3>; 801 status = "okay"; 802}; 803 804&iomuxc { 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_hog>; 807 808 pinctrl_hog: hoggrp { 809 fsl,pins = < 810 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 811 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 812 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c 813 IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c 814 >; 815 }; 816 817 pinctrl_usbotg1: usbotg1grp { 818 fsl,pins = < 819 IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 820 >; 821 }; 822 823 pinctrl_usbotg2: usbotg2grp { 824 fsl,pins = < 825 IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 826 >; 827 }; 828 829 pinctrl_eqos: eqosgrp { 830 fsl,pins = < 831 IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 832 IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 833 IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 834 IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 835 IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 836 IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 837 IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 838 IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 839 IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 840 IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 841 IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 842 IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 843 IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 844 IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 845 >; 846 }; 847 848 pinctrl_flexspi0: flexspi0grp { 849 fsl,pins = < 850 IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 851 IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 852 IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 853 IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 854 IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 855 IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 856 IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 857 IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 858 IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 859 IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 860 IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 861 IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 862 IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 863 IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 864 >; 865 }; 866 867 pinctrl_flexcan2: flexcan2grp { 868 fsl,pins = < 869 IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 870 IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 871 >; 872 }; 873 874 pinctrl_flexcan3: flexcan3grp { 875 fsl,pins = < 876 IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 877 IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 878 >; 879 }; 880 881 pinctrl_fec1: fec1grp { 882 fsl,pins = < 883 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 884 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 885 IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 886 IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 887 IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 888 IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 889 IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 890 IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 891 IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 892 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 893 IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 894 IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 895 IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 896 IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 897 IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 898 IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 899 >; 900 }; 901 902 pinctrl_lpspi3: lpspi3grp { 903 fsl,pins = < 904 IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 905 IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 906 IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 907 IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 908 >; 909 }; 910 911 pinctrl_i2c2: i2c2grp { 912 fsl,pins = < 913 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 914 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 915 >; 916 }; 917 918 pinctrl_cm40_lpuart: cm40lpuartgrp { 919 fsl,pins = < 920 IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 921 IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 922 >; 923 }; 924 925 pinctrl_i2c3: i2c3grp { 926 fsl,pins = < 927 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 928 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 929 >; 930 }; 931 932 pinctrl_lpuart0: lpuart0grp { 933 fsl,pins = < 934 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 935 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 936 >; 937 }; 938 939 pinctrl_lpuart1: lpuart1grp { 940 fsl,pins = < 941 IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 942 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 943 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 944 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 945 >; 946 }; 947 948 pinctrl_pcieb: pcieagrp { 949 fsl,pins = < 950 IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 951 IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 952 IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 953 >; 954 }; 955 956 pinctrl_sai0: sai0grp { 957 fsl,pins = < 958 IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 959 IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040 960 IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060 961 IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 962 IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 963 >; 964 }; 965 966 pinctrl_sai1: sai1grp { 967 fsl,pins = < 968 IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 969 IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 970 IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 971 IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 972 >; 973 }; 974 975 pinctrl_sai2: sai2grp { 976 fsl,pins = < 977 IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 978 IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 979 IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 980 >; 981 }; 982 983 pinctrl_sai3: sai3grp { 984 fsl,pins = < 985 IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 986 IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 987 IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 988 >; 989 }; 990 991 pinctrl_usdhc1: usdhc1grp { 992 fsl,pins = < 993 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 994 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 995 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 996 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 997 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 998 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 999 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 1000 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 1001 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 1002 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 1003 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 1004 >; 1005 }; 1006 1007 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 1008 fsl,pins = < 1009 IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ 1010 IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ 1011 IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ 1012 >; 1013 }; 1014 1015 pinctrl_usdhc2: usdhc2grp { 1016 fsl,pins = < 1017 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 1018 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 1019 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 1020 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 1021 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 1022 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 1023 IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 1024 >; 1025 }; 1026}; 1027