1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13 #include <linux/ethtool.h>
14
15 #include "rvu_struct.h"
16 #include "common.h"
17 #include "cn20k/struct.h"
18
19 #define MBOX_SIZE SZ_64K
20
21 #define MBOX_DOWN_MSG 1
22 #define MBOX_UP_MSG 2
23
24 /* AF/PF: PF initiated, PF/VF VF initiated */
25 #define MBOX_DOWN_RX_START 0
26 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
27 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
28 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
29 /* AF/PF: AF initiated, PF/VF PF initiated */
30 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
31 #define MBOX_UP_RX_SIZE SZ_1K
32 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
33 #define MBOX_UP_TX_SIZE SZ_1K
34
35 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
36 # error "incorrect mailbox area sizes"
37 #endif
38
39 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
40
41 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
42
43 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
44
45 /* Mailbox directions */
46 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
47 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
48 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
49 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
50 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
51 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
52 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
53 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
54
55 enum {
56 NPC_MCAM_KEY_X1 = 0,
57 NPC_MCAM_KEY_DYN = NPC_MCAM_KEY_X1,
58 NPC_MCAM_KEY_X2,
59 NPC_MCAM_KEY_X4,
60 NPC_MCAM_KEY_MAX,
61 };
62
63 enum {
64 TYPE_AFVF,
65 TYPE_AFPF,
66 };
67
68 struct otx2_mbox_dev {
69 void *mbase; /* This dev's mbox region */
70 void *hwbase;
71 spinlock_t mbox_lock;
72 u16 msg_size; /* Total msg size to be sent */
73 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
74 u16 num_msgs; /* No of msgs sent or waiting for response */
75 u16 msgs_acked; /* No of msgs for which response is received */
76 };
77
78 struct otx2_mbox {
79 struct pci_dev *pdev;
80 void *hwbase; /* Mbox region advertised by HW */
81 void *reg_base;/* CSR base for this dev */
82 u64 trigger; /* Trigger mbox notification */
83 u16 tr_shift; /* Mbox trigger shift */
84 u64 rx_start; /* Offset of Rx region in mbox memory */
85 u64 tx_start; /* Offset of Tx region in mbox memory */
86 u16 rx_size; /* Size of Rx region */
87 u16 tx_size; /* Size of Tx region */
88 u16 ndevs; /* The number of peers */
89 struct otx2_mbox_dev *dev;
90 };
91
92 /* Header which precedes all mbox messages */
93 struct mbox_hdr {
94 u64 msg_size; /* Total msgs size embedded */
95 u16 num_msgs; /* No of msgs embedded */
96 u16 opt_msg;
97 u8 sig;
98 };
99
100 /* Header which precedes every msg and is also part of it */
101 struct mbox_msghdr {
102 u16 pcifunc; /* Who's sending this msg */
103 u16 id; /* Mbox message ID */
104 #define OTX2_MBOX_REQ_SIG (0xdead)
105 #define OTX2_MBOX_RSP_SIG (0xbeef)
106 u16 sig; /* Signature, for validating corrupted msgs */
107 #define OTX2_MBOX_VERSION (0x000a)
108 u16 ver; /* Version of msg's structure for this ID */
109 u16 next_msgoff; /* Offset of next msg within mailbox region */
110 int rc; /* Msg process'ed response code */
111 };
112
113 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
114 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
115 void otx2_mbox_destroy(struct otx2_mbox *mbox);
116 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
117 struct pci_dev *pdev, void __force *reg_base,
118 int direction, int ndevs);
119
120 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
121 struct pci_dev *pdev, void __force *reg_base,
122 int direction, int ndevs, unsigned long *bmap);
123 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
124 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
125 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
126 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
127 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
128 int size, int size_rsp);
129 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
130 struct mbox_msghdr *msg);
131 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
132 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
133 u16 pcifunc, u16 id);
134 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
135 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)136 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
137 int devid, int size)
138 {
139 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
140 }
141
142 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
143
144 /* Mailbox message types */
145 #define MBOX_MSG_MASK 0xFFFF
146 #define MBOX_MSG_INVALID 0xFFFE
147 #define MBOX_MSG_MAX 0xFFFF
148
149 #define MBOX_MESSAGES \
150 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
151 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
152 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
153 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
154 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
155 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
156 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
157 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
158 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
159 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
160 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
161 msg_rsp) \
162 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
163 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
164 M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \
165 M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \
166 M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \
167 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
168 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
169 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
170 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
171 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
172 cgx_mac_addr_set_or_get) \
173 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
174 cgx_mac_addr_set_or_get) \
175 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
176 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
177 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
178 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
179 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
180 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
181 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
182 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
183 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
184 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
185 cgx_pause_frm_cfg) \
186 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
187 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
188 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
189 cgx_mac_addr_add_rsp) \
190 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
191 msg_rsp) \
192 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
193 cgx_max_dmac_entries_get_rsp) \
194 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
195 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
196 cgx_set_link_mode_rsp) \
197 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
198 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
199 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
200 cgx_features_info_msg) \
201 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
202 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
203 msg_rsp) \
204 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
205 cgx_mac_addr_update_rsp) \
206 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
207 cgx_pfc_rsp) \
208 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
209 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
210 npa_lf_alloc_req, npa_lf_alloc_rsp) \
211 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
212 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
213 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
214 M(NPA_CN20K_AQ_ENQ, 0x404, npa_cn20k_aq_enq, npa_cn20k_aq_enq_req, \
215 npa_cn20k_aq_enq_rsp) \
216 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
217 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
218 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
219 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
220 msg_rsp) \
221 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
222 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
223 cpt_rd_wr_reg_msg) \
224 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
225 cpt_inline_ipsec_cfg_msg, msg_rsp) \
226 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
227 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
228 msg_rsp) \
229 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
230 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
231 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
232 cpt_flt_eng_info_rsp) \
233 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
234 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
235 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
236 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
237 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
238 npc_mcam_alloc_entry_rsp) \
239 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
240 npc_mcam_free_entry_req, msg_rsp) \
241 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
242 npc_mcam_write_entry_req, msg_rsp) \
243 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
244 npc_mcam_ena_dis_entry_req, msg_rsp) \
245 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
246 npc_mcam_ena_dis_entry_req, msg_rsp) \
247 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
248 npc_mcam_shift_entry_rsp) \
249 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
250 npc_mcam_alloc_counter_req, \
251 npc_mcam_alloc_counter_rsp) \
252 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
253 npc_mcam_oper_counter_req, msg_rsp) \
254 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
255 npc_mcam_unmap_counter_req, msg_rsp) \
256 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
257 npc_mcam_oper_counter_req, msg_rsp) \
258 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
259 npc_mcam_oper_counter_req, \
260 npc_mcam_oper_counter_rsp) \
261 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
262 npc_mcam_alloc_and_write_entry_req, \
263 npc_mcam_alloc_and_write_entry_rsp) \
264 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
265 msg_req, npc_get_kex_cfg_rsp) \
266 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
267 npc_install_flow_req, npc_install_flow_rsp) \
268 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
269 npc_delete_flow_req, npc_delete_flow_rsp) \
270 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
271 npc_mcam_read_entry_req, \
272 npc_mcam_read_entry_rsp) \
273 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
274 npc_set_pkind, msg_rsp) \
275 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
276 msg_req, npc_mcam_read_base_rule_rsp) \
277 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
278 npc_mcam_get_stats_req, \
279 npc_mcam_get_stats_rsp) \
280 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
281 npc_get_field_hash_info_req, \
282 npc_get_field_hash_info_rsp) \
283 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
284 npc_get_field_status_req, \
285 npc_get_field_status_rsp) \
286 M(NPC_MCAM_DEFRAG, 0x6016, npc_defrag, \
287 msg_req, \
288 msg_rsp) \
289 M(NPC_CN20K_GET_KEX_CFG, 0x6017, npc_cn20k_get_kex_cfg, \
290 msg_req, npc_cn20k_get_kex_cfg_rsp) \
291 M(NPC_CN20K_MCAM_GET_FREE_COUNT, 0x6018, npc_cn20k_get_fcnt, \
292 msg_req, npc_cn20k_get_fcnt_rsp) \
293 M(NPC_CN20K_MCAM_WRITE_ENTRY, 0x6019, npc_cn20k_mcam_write_entry, \
294 npc_cn20k_mcam_write_entry_req, msg_rsp) \
295 M(NPC_CN20K_MCAM_ALLOC_AND_WRITE_ENTRY, 0x601a, npc_cn20k_mcam_alloc_and_write_entry, \
296 npc_cn20k_mcam_alloc_and_write_entry_req, \
297 npc_mcam_alloc_and_write_entry_rsp) \
298 M(NPC_CN20K_MCAM_READ_ENTRY, 0x601b, npc_cn20k_mcam_read_entry, \
299 npc_mcam_read_entry_req, \
300 npc_cn20k_mcam_read_entry_rsp) \
301 M(NPC_CN20K_MCAM_READ_BASE_RULE, 0x601c, npc_cn20k_read_base_steer_rule, \
302 msg_req, npc_cn20k_mcam_read_base_rule_rsp) \
303 M(NPC_MCAM_GET_NUM_KWS, 0x601d, npc_get_num_kws, \
304 npc_get_num_kws_req, \
305 npc_get_num_kws_rsp) \
306 M(NPC_MCAM_GET_DFT_RL_IDXS, 0x601e, npc_get_dft_rl_idxs, \
307 msg_req, \
308 npc_get_dft_rl_idxs_rsp)\
309 M(NPC_MCAM_GET_NPC_PFL_INFO, 0x601f, npc_get_pfl_info, \
310 msg_req, \
311 npc_get_pfl_info_rsp) \
312 M(NPC_MCAM_READ_DEFAULT_RULE, 0x6021, npc_read_default_rule, msg_req, \
313 npc_mcam_read_base_rule_rsp) \
314 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
315 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
316 nix_lf_alloc_req, nix_lf_alloc_rsp) \
317 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
318 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
319 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
320 hwctx_disable_req, msg_rsp) \
321 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
322 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
323 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
324 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
325 nix_txschq_config) \
326 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
327 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
328 nix_vtag_config_rsp) \
329 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
330 nix_rss_flowkey_cfg, \
331 nix_rss_flowkey_cfg_rsp) \
332 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
333 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
334 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
335 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
336 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
337 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
338 nix_mark_format_cfg, \
339 nix_mark_format_cfg_rsp) \
340 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
341 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
342 nix_lso_format_cfg, \
343 nix_lso_format_cfg_rsp) \
344 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
345 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
346 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
347 nix_bp_cfg_rsp) \
348 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
349 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
350 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
351 nix_inline_ipsec_cfg, msg_rsp) \
352 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
353 nix_inline_ipsec_lf_cfg, msg_rsp) \
354 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
355 nix_cn10k_aq_enq_rsp) \
356 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
357 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
358 nix_bandprof_alloc_rsp) \
359 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
360 msg_rsp) \
361 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
362 nix_bandprof_get_hwinfo_rsp) \
363 M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \
364 nix_bp_cfg_rsp) \
365 M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \
366 msg_rsp) \
367 M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \
368 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
369 msg_req, nix_inline_ipsec_cfg) \
370 M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
371 nix_mcast_grp_create_rsp) \
372 M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
373 msg_rsp) \
374 M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
375 nix_mcast_grp_update_req, \
376 nix_mcast_grp_update_rsp) \
377 M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \
378 M(NIX_CN20K_AQ_ENQ, 0x802f, nix_cn20k_aq_enq, nix_cn20k_aq_enq_req, \
379 nix_cn20k_aq_enq_rsp) \
380 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
381 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
382 mcs_alloc_rsrc_rsp) \
383 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
384 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
385 msg_rsp) \
386 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
387 msg_rsp) \
388 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
389 msg_rsp) \
390 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
391 msg_rsp) \
392 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
393 msg_rsp) \
394 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
395 msg_rsp) \
396 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
397 msg_rsp) \
398 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
399 msg_rsp) \
400 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
401 msg_rsp) \
402 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
403 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
404 mcs_flowid_stats) \
405 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
406 mcs_secy_stats) \
407 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
408 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
409 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
410 mcs_port_stats) \
411 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
412 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
413 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
414 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
415 msg_rsp) \
416 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
417 mcs_alloc_ctrl_pkt_rule_req, \
418 mcs_alloc_ctrl_pkt_rule_rsp) \
419 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
420 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
421 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
422 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
423 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
424 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
425 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
426 mcs_port_cfg_get_rsp) \
427 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
428 mcs_custom_tag_cfg_get_req, \
429 mcs_custom_tag_cfg_get_rsp)
430
431 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
432 #define MBOX_UP_CGX_MESSAGES \
433 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
434
435 #define MBOX_UP_CPT_MESSAGES \
436 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
437
438 #define MBOX_UP_MCS_MESSAGES \
439 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
440
441 #define MBOX_UP_REP_MESSAGES \
442 M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \
443
444 enum {
445 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
446 MBOX_MESSAGES
447 MBOX_UP_CGX_MESSAGES
448 MBOX_UP_CPT_MESSAGES
449 MBOX_UP_MCS_MESSAGES
450 MBOX_UP_REP_MESSAGES
451 #undef M
452 };
453
454 /* Mailbox message formats */
455
456 #define RVU_DEFAULT_PF_FUNC 0xFFFF
457
458 /* Generic request msg used for those mbox messages which
459 * don't send any data in the request.
460 */
461 struct msg_req {
462 struct mbox_msghdr hdr;
463 };
464
465 /* Generic response msg used an ack or response for those mbox
466 * messages which don't have a specific rsp msg format.
467 */
468 struct msg_rsp {
469 struct mbox_msghdr hdr;
470 };
471
472 /* RVU mailbox error codes
473 * Range 256 - 300.
474 */
475 enum rvu_af_status {
476 RVU_INVALID_VF_ID = -256,
477 };
478
479 struct ready_msg_rsp {
480 struct mbox_msghdr hdr;
481 u16 sclk_freq; /* SCLK frequency (in MHz) */
482 u16 rclk_freq; /* RCLK frequency (in MHz) */
483 };
484
485 /* Structure for requesting resource provisioning.
486 * 'modify' flag to be used when either requesting more
487 * or to detach partial of a certain resource type.
488 * Rest of the fields specify how many of what type to
489 * be attached.
490 * To request LFs from two blocks of same type this mailbox
491 * can be sent twice as below:
492 * struct rsrc_attach *attach;
493 * .. Allocate memory for message ..
494 * attach->cptlfs = 3; <3 LFs from CPT0>
495 * .. Send message ..
496 * .. Allocate memory for message ..
497 * attach->modify = 1;
498 * attach->cpt_blkaddr = BLKADDR_CPT1;
499 * attach->cptlfs = 2; <2 LFs from CPT1>
500 * .. Send message ..
501 */
502 struct rsrc_attach {
503 struct mbox_msghdr hdr;
504 u8 modify:1;
505 u8 npalf:1;
506 u8 nixlf:1;
507 u16 sso;
508 u16 ssow;
509 u16 timlfs;
510 u16 cptlfs;
511 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
512 };
513
514 /* Structure for relinquishing resources.
515 * 'partial' flag to be used when relinquishing all resources
516 * but only of a certain type. If not set, all resources of all
517 * types provisioned to the RVU function will be detached.
518 */
519 struct rsrc_detach {
520 struct mbox_msghdr hdr;
521 u8 partial:1;
522 u8 npalf:1;
523 u8 nixlf:1;
524 u8 sso:1;
525 u8 ssow:1;
526 u8 timlfs:1;
527 u8 cptlfs:1;
528 };
529
530 /* Number of resources available to the caller.
531 * In reply to MBOX_MSG_FREE_RSRC_CNT.
532 */
533 struct free_rsrcs_rsp {
534 struct mbox_msghdr hdr;
535 u16 schq[NIX_TXSCH_LVL_CNT];
536 u16 sso;
537 u16 tim;
538 u16 ssow;
539 u16 cpt;
540 u8 npa;
541 u8 nix;
542 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
543 u8 nix1;
544 u8 cpt1;
545 u8 ree0;
546 u8 ree1;
547 };
548
549 #define MSIX_VECTOR_INVALID 0xFFFF
550 #define MAX_RVU_BLKLF_CNT 256
551
552 struct msix_offset_rsp {
553 struct mbox_msghdr hdr;
554 u16 npa_msixoff;
555 u16 nix_msixoff;
556 u16 sso;
557 u16 ssow;
558 u16 timlfs;
559 u16 cptlfs;
560 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
561 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
562 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
563 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
564 u16 cpt1_lfs;
565 u16 ree0_lfs;
566 u16 ree1_lfs;
567 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
568 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
569 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
570 };
571
572 struct get_hw_cap_rsp {
573 struct mbox_msghdr hdr;
574 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
575 u8 nix_shaping; /* Is shaping and coloring supported */
576 u8 npc_hash_extract; /* Is hash extract supported */
577 #define HW_CAP_MACSEC BIT_ULL(1)
578 u64 hw_caps;
579 };
580
581 /* CGX mbox message formats */
582
583 struct cgx_stats_rsp {
584 struct mbox_msghdr hdr;
585 #define CGX_RX_STATS_COUNT 9
586 #define CGX_TX_STATS_COUNT 18
587 u64 rx_stats[CGX_RX_STATS_COUNT];
588 u64 tx_stats[CGX_TX_STATS_COUNT];
589 };
590
591 struct cgx_fec_stats_rsp {
592 struct mbox_msghdr hdr;
593 u64 fec_corr_blks;
594 u64 fec_uncorr_blks;
595 };
596 /* Structure for requesting the operation for
597 * setting/getting mac address in the CGX interface
598 */
599 struct cgx_mac_addr_set_or_get {
600 struct mbox_msghdr hdr;
601 u8 mac_addr[ETH_ALEN];
602 u32 index;
603 };
604
605 /* Structure for requesting the operation to
606 * add DMAC filter entry into CGX interface
607 */
608 struct cgx_mac_addr_add_req {
609 struct mbox_msghdr hdr;
610 u8 mac_addr[ETH_ALEN];
611 };
612
613 /* Structure for response against the operation to
614 * add DMAC filter entry into CGX interface
615 */
616 struct cgx_mac_addr_add_rsp {
617 struct mbox_msghdr hdr;
618 u32 index;
619 };
620
621 /* Structure for requesting the operation to
622 * delete DMAC filter entry from CGX interface
623 */
624 struct cgx_mac_addr_del_req {
625 struct mbox_msghdr hdr;
626 u32 index;
627 };
628
629 /* Structure for response against the operation to
630 * get maximum supported DMAC filter entries
631 */
632 struct cgx_max_dmac_entries_get_rsp {
633 struct mbox_msghdr hdr;
634 u32 max_dmac_filters;
635 };
636
637 struct cgx_link_user_info {
638 uint64_t link_up:1;
639 uint64_t full_duplex:1;
640 uint64_t lmac_type_id:4;
641 uint64_t speed:20; /* speed in Mbps */
642 uint64_t an:1; /* AN supported or not */
643 uint64_t fec:2; /* FEC type if enabled else 0 */
644 #define LMACTYPE_STR_LEN 16
645 char lmac_type[LMACTYPE_STR_LEN];
646 };
647
648 struct cgx_link_info_msg {
649 struct mbox_msghdr hdr;
650 struct cgx_link_user_info link_info;
651 };
652
653 struct cgx_pause_frm_cfg {
654 struct mbox_msghdr hdr;
655 u8 set;
656 /* set = 1 if the request is to config pause frames */
657 /* set = 0 if the request is to fetch pause frames config */
658 u8 rx_pause;
659 u8 tx_pause;
660 };
661
662 enum fec_type {
663 OTX2_FEC_NONE,
664 OTX2_FEC_BASER,
665 OTX2_FEC_RS,
666 OTX2_FEC_STATS_CNT = 2,
667 OTX2_FEC_OFF,
668 };
669
670 struct fec_mode {
671 struct mbox_msghdr hdr;
672 int fec;
673 };
674
675 struct sfp_eeprom_s {
676 #define SFP_EEPROM_SIZE 256
677 u16 sff_id;
678 u8 buf[SFP_EEPROM_SIZE];
679 u64 reserved;
680 };
681
682 struct phy_s {
683 struct {
684 u64 can_change_mod_type:1;
685 u64 mod_type:1;
686 u64 has_fec_stats:1;
687 } misc;
688 struct fec_stats_s {
689 u32 rsfec_corr_cws;
690 u32 rsfec_uncorr_cws;
691 u32 brfec_corr_blks;
692 u32 brfec_uncorr_blks;
693 } fec_stats;
694 };
695
696 struct cgx_lmac_fwdata_s {
697 u16 rw_valid;
698 u64 supported_fec;
699 u64 supported_an;
700 u64 supported_link_modes;
701 /* only applicable if AN is supported */
702 u64 advertised_fec;
703 u64 advertised_link_modes_own:1; /* CGX_CMD_OWN */
704 u64 advertised_link_modes:63;
705 /* Only applicable if SFP/QSFP slot is present */
706 struct sfp_eeprom_s sfp_eeprom;
707 struct phy_s phy;
708 u32 lmac_type;
709 u32 portm_idx;
710 u64 mgmt_port:1;
711 u64 advertised_an:1;
712 u64 port;
713 #define LMAC_FWDATA_RESERVED_MEM 1018
714 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
715 };
716
717 struct cgx_fw_data {
718 struct mbox_msghdr hdr;
719 struct cgx_lmac_fwdata_s fwdata;
720 };
721
722 struct cgx_set_link_mode_args {
723 u32 speed;
724 u8 duplex;
725 u8 an;
726 u8 mode_baseidx;
727 u8 multimode;
728 u64 mode;
729 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
730 };
731
732 struct cgx_set_link_mode_req {
733 struct mbox_msghdr hdr;
734 struct cgx_set_link_mode_args args;
735 };
736
737 struct cgx_set_link_mode_rsp {
738 struct mbox_msghdr hdr;
739 int status;
740 };
741
742 struct cgx_mac_addr_reset_req {
743 struct mbox_msghdr hdr;
744 u32 index;
745 };
746
747 struct cgx_mac_addr_update_req {
748 struct mbox_msghdr hdr;
749 u8 mac_addr[ETH_ALEN];
750 u32 index;
751 };
752
753 struct cgx_mac_addr_update_rsp {
754 struct mbox_msghdr hdr;
755 u32 index;
756 };
757
758 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
759 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
760 /* flow control from physical link higig2 messages */
761 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
762 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
763 #define RVU_MAC_VERSION BIT_ULL(4)
764 #define RVU_MAC_CGX BIT_ULL(5)
765 #define RVU_MAC_RPM BIT_ULL(6)
766
767 struct cgx_features_info_msg {
768 struct mbox_msghdr hdr;
769 u64 lmac_features;
770 };
771
772 struct rpm_stats_rsp {
773 struct mbox_msghdr hdr;
774 #define RPM_RX_STATS_COUNT 43
775 #define RPM_TX_STATS_COUNT 34
776 u64 rx_stats[RPM_RX_STATS_COUNT];
777 u64 tx_stats[RPM_TX_STATS_COUNT];
778 };
779
780 struct cgx_pfc_cfg {
781 struct mbox_msghdr hdr;
782 u8 rx_pause;
783 u8 tx_pause;
784 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
785 };
786
787 struct cgx_pfc_rsp {
788 struct mbox_msghdr hdr;
789 u8 rx_pause;
790 u8 tx_pause;
791 };
792
793 /* NPA mbox message formats */
794
795 struct npc_set_pkind {
796 struct mbox_msghdr hdr;
797 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
798 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
799 u64 mode;
800 #define PKIND_TX BIT_ULL(0)
801 #define PKIND_RX BIT_ULL(1)
802 u8 dir;
803 u8 pkind; /* valid only in case custom flag */
804 u8 var_len_off; /* Offset of custom header length field.
805 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
806 */
807 u8 var_len_off_mask; /* Mask for length with in offset */
808 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
809 u8 skip_size; /* l2 size to skip */
810 };
811
812 /* NPA mbox message formats */
813
814 /* NPA mailbox error codes
815 * Range 301 - 400.
816 */
817 enum npa_af_status {
818 NPA_AF_ERR_PARAM = -301,
819 NPA_AF_ERR_AQ_FULL = -302,
820 NPA_AF_ERR_AQ_ENQUEUE = -303,
821 NPA_AF_ERR_AF_LF_INVALID = -304,
822 NPA_AF_ERR_AF_LF_ALLOC = -305,
823 NPA_AF_ERR_LF_RESET = -306,
824 };
825
826 /* For NPA LF context alloc and init */
827 struct npa_lf_alloc_req {
828 struct mbox_msghdr hdr;
829 int node;
830 int aura_sz; /* No of auras */
831 u32 nr_pools; /* No of pools */
832 u64 way_mask;
833 };
834
835 struct npa_lf_alloc_rsp {
836 struct mbox_msghdr hdr;
837 u32 stack_pg_ptrs; /* No of ptrs per stack page */
838 u32 stack_pg_bytes; /* Size of stack page */
839 u16 qints; /* NPA_AF_CONST::QINTS */
840 u8 cache_lines; /*BATCH ALLOC DMA */
841 };
842
843 /* NPA AQ enqueue msg */
844 struct npa_aq_enq_req {
845 struct mbox_msghdr hdr;
846 u32 aura_id;
847 u8 ctype;
848 u8 op;
849 union {
850 /* Valid when op == WRITE/INIT and ctype == AURA.
851 * LF fills the pool_id in aura.pool_addr. AF will translate
852 * the pool_id to pool context pointer.
853 */
854 struct npa_aura_s aura;
855 /* Valid when op == WRITE/INIT and ctype == POOL */
856 struct npa_pool_s pool;
857 };
858 /* Mask data when op == WRITE (1=write, 0=don't write) */
859 union {
860 /* Valid when op == WRITE and ctype == AURA */
861 struct npa_aura_s aura_mask;
862 /* Valid when op == WRITE and ctype == POOL */
863 struct npa_pool_s pool_mask;
864 };
865 };
866
867 struct npa_aq_enq_rsp {
868 struct mbox_msghdr hdr;
869 union {
870 /* Valid when op == READ and ctype == AURA */
871 struct npa_aura_s aura;
872 /* Valid when op == READ and ctype == POOL */
873 struct npa_pool_s pool;
874 };
875 };
876
877 struct npa_cn20k_aq_enq_req {
878 struct mbox_msghdr hdr;
879 u32 aura_id;
880 u8 ctype;
881 u8 op;
882 union {
883 /* Valid when op == WRITE/INIT and ctype == AURA.
884 * LF fills the pool_id in aura.pool_addr. AF will translate
885 * the pool_id to pool context pointer.
886 */
887 struct npa_cn20k_aura_s aura;
888 /* Valid when op == WRITE/INIT and ctype == POOL */
889 struct npa_cn20k_pool_s pool;
890 };
891 /* Mask data when op == WRITE (1=write, 0=don't write) */
892 union {
893 /* Valid when op == WRITE and ctype == AURA */
894 struct npa_cn20k_aura_s aura_mask;
895 /* Valid when op == WRITE and ctype == POOL */
896 struct npa_cn20k_pool_s pool_mask;
897 };
898 };
899
900 struct npa_cn20k_aq_enq_rsp {
901 struct mbox_msghdr hdr;
902 union {
903 /* Valid when op == READ and ctype == AURA */
904 struct npa_cn20k_aura_s aura;
905 /* Valid when op == READ and ctype == POOL */
906 struct npa_cn20k_pool_s pool;
907 };
908 };
909
910 /* Disable all contexts of type 'ctype' */
911 struct hwctx_disable_req {
912 struct mbox_msghdr hdr;
913 u8 ctype;
914 };
915
916 /* NIX mbox message formats */
917
918 /* NIX mailbox error codes
919 * Range 401 - 500.
920 */
921 enum nix_af_status {
922 NIX_AF_ERR_PARAM = -401,
923 NIX_AF_ERR_AQ_FULL = -402,
924 NIX_AF_ERR_AQ_ENQUEUE = -403,
925 NIX_AF_ERR_AF_LF_INVALID = -404,
926 NIX_AF_ERR_AF_LF_ALLOC = -405,
927 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
928 NIX_AF_ERR_TLX_INVALID = -407,
929 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
930 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
931 NIX_AF_ERR_FRS_INVALID = -410,
932 NIX_AF_ERR_RX_LINK_INVALID = -411,
933 NIX_AF_INVAL_TXSCHQ_CFG = -412,
934 NIX_AF_SMQ_FLUSH_FAILED = -413,
935 NIX_AF_ERR_LF_RESET = -414,
936 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
937 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
938 NIX_AF_ERR_MARK_CFG_FAIL = -417,
939 NIX_AF_ERR_LSO_CFG_FAIL = -418,
940 NIX_AF_INVAL_NPA_PF_FUNC = -419,
941 NIX_AF_INVAL_SSO_PF_FUNC = -420,
942 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
943 NIX_AF_ERR_RX_VTAG_INUSE = -422,
944 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
945 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
946 NIX_AF_ERR_INVALID_NIXBLK = -425,
947 NIX_AF_ERR_INVALID_BANDPROF = -426,
948 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
949 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
950 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
951 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
952 NIX_AF_ERR_LINK_CREDITS = -431,
953 NIX_AF_ERR_INVALID_BPID = -434,
954 NIX_AF_ERR_INVALID_BPID_REQ = -435,
955 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
956 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
957 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
958 NIX_AF_ERR_RX_SW_SYNC_FAIL = -439,
959 };
960
961 /* For NIX RX vtag action */
962 enum nix_rx_vtag0_type {
963 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
964 NIX_AF_LFX_RX_VTAG_TYPE1,
965 NIX_AF_LFX_RX_VTAG_TYPE2,
966 NIX_AF_LFX_RX_VTAG_TYPE3,
967 NIX_AF_LFX_RX_VTAG_TYPE4,
968 NIX_AF_LFX_RX_VTAG_TYPE5,
969 NIX_AF_LFX_RX_VTAG_TYPE6,
970 NIX_AF_LFX_RX_VTAG_TYPE7,
971 };
972
973 /* For NIX LF context alloc and init */
974 struct nix_lf_alloc_req {
975 struct mbox_msghdr hdr;
976 int node;
977 u32 rq_cnt; /* No of receive queues */
978 u32 sq_cnt; /* No of send queues */
979 u32 cq_cnt; /* No of completion queues */
980 u8 xqe_sz;
981 u16 rss_sz;
982 u8 rss_grps;
983 u16 npa_func;
984 u16 sso_func;
985 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
986 u64 way_mask;
987 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
988 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
989 u64 flags;
990 };
991
992 struct nix_lf_alloc_rsp {
993 struct mbox_msghdr hdr;
994 u16 sqb_size;
995 u16 rx_chan_base;
996 u16 tx_chan_base;
997 u8 rx_chan_cnt; /* total number of RX channels */
998 u8 tx_chan_cnt; /* total number of TX channels */
999 u8 lso_tsov4_idx;
1000 u8 lso_tsov6_idx;
1001 u8 mac_addr[ETH_ALEN];
1002 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
1003 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
1004 u16 cints; /* NIX_AF_CONST2::CINTS */
1005 u16 qints; /* NIX_AF_CONST2::QINTS */
1006 u8 cgx_links; /* No. of CGX links present in HW */
1007 u8 lbk_links; /* No. of LBK links present in HW */
1008 u8 sdp_links; /* No. of SDP links present in HW */
1009 u8 tx_link; /* Transmit channel link number */
1010 };
1011
1012 struct nix_lf_free_req {
1013 struct mbox_msghdr hdr;
1014 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
1015 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
1016 #define NIX_LF_DONT_FREE_DFT_IDXS BIT_ULL(2)
1017 u64 flags;
1018 };
1019
1020 /* CN20K NIX AQ enqueue msg */
1021 struct nix_cn20k_aq_enq_req {
1022 struct mbox_msghdr hdr;
1023 u32 qidx;
1024 u8 ctype;
1025 u8 op;
1026 union {
1027 struct nix_cn20k_rq_ctx_s rq;
1028 struct nix_cn20k_sq_ctx_s sq;
1029 struct nix_cn20k_cq_ctx_s cq;
1030 struct nix_rsse_s rss;
1031 struct nix_rx_mce_s mce;
1032 struct nix_bandprof_s prof;
1033 };
1034 union {
1035 struct nix_cn20k_rq_ctx_s rq_mask;
1036 struct nix_cn20k_sq_ctx_s sq_mask;
1037 struct nix_cn20k_cq_ctx_s cq_mask;
1038 struct nix_rsse_s rss_mask;
1039 struct nix_rx_mce_s mce_mask;
1040 struct nix_bandprof_s prof_mask;
1041 };
1042 };
1043
1044 struct nix_cn20k_aq_enq_rsp {
1045 struct mbox_msghdr hdr;
1046 union {
1047 struct nix_cn20k_rq_ctx_s rq;
1048 struct nix_cn20k_sq_ctx_s sq;
1049 struct nix_cn20k_cq_ctx_s cq;
1050 struct nix_rsse_s rss;
1051 struct nix_rx_mce_s mce;
1052 struct nix_bandprof_s prof;
1053 };
1054 };
1055
1056 /* CN10K NIX AQ enqueue msg */
1057 struct nix_cn10k_aq_enq_req {
1058 struct mbox_msghdr hdr;
1059 u32 qidx;
1060 u8 ctype;
1061 u8 op;
1062 union {
1063 struct nix_cn10k_rq_ctx_s rq;
1064 struct nix_cn10k_sq_ctx_s sq;
1065 struct nix_cq_ctx_s cq;
1066 struct nix_rsse_s rss;
1067 struct nix_rx_mce_s mce;
1068 struct nix_bandprof_s prof;
1069 };
1070 union {
1071 struct nix_cn10k_rq_ctx_s rq_mask;
1072 struct nix_cn10k_sq_ctx_s sq_mask;
1073 struct nix_cq_ctx_s cq_mask;
1074 struct nix_rsse_s rss_mask;
1075 struct nix_rx_mce_s mce_mask;
1076 struct nix_bandprof_s prof_mask;
1077 };
1078 };
1079
1080 struct nix_cn10k_aq_enq_rsp {
1081 struct mbox_msghdr hdr;
1082 union {
1083 struct nix_cn10k_rq_ctx_s rq;
1084 struct nix_cn10k_sq_ctx_s sq;
1085 struct nix_cq_ctx_s cq;
1086 struct nix_rsse_s rss;
1087 struct nix_rx_mce_s mce;
1088 struct nix_bandprof_s prof;
1089 };
1090 };
1091
1092 /* NIX AQ enqueue msg */
1093 struct nix_aq_enq_req {
1094 struct mbox_msghdr hdr;
1095 u32 qidx;
1096 u8 ctype;
1097 u8 op;
1098 union {
1099 struct nix_rq_ctx_s rq;
1100 struct nix_sq_ctx_s sq;
1101 struct nix_cq_ctx_s cq;
1102 struct nix_rsse_s rss;
1103 struct nix_rx_mce_s mce;
1104 struct nix_bandprof_s prof;
1105 };
1106 union {
1107 struct nix_rq_ctx_s rq_mask;
1108 struct nix_sq_ctx_s sq_mask;
1109 struct nix_cq_ctx_s cq_mask;
1110 struct nix_rsse_s rss_mask;
1111 struct nix_rx_mce_s mce_mask;
1112 struct nix_bandprof_s prof_mask;
1113 };
1114 };
1115
1116 struct nix_aq_enq_rsp {
1117 struct mbox_msghdr hdr;
1118 union {
1119 struct nix_rq_ctx_s rq;
1120 struct nix_sq_ctx_s sq;
1121 struct nix_cq_ctx_s cq;
1122 struct nix_rsse_s rss;
1123 struct nix_rx_mce_s mce;
1124 struct nix_bandprof_s prof;
1125 };
1126 };
1127
1128 /* Tx scheduler/shaper mailbox messages */
1129
1130 #define MAX_TXSCHQ_PER_FUNC 128
1131
1132 struct nix_txsch_alloc_req {
1133 struct mbox_msghdr hdr;
1134 /* Scheduler queue count request at each level */
1135 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
1136 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
1137 };
1138
1139 struct nix_txsch_alloc_rsp {
1140 struct mbox_msghdr hdr;
1141 /* Scheduler queue count allocated at each level */
1142 u16 schq_contig[NIX_TXSCH_LVL_CNT];
1143 u16 schq[NIX_TXSCH_LVL_CNT];
1144 /* Scheduler queue list allocated at each level */
1145 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1146 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1147 u8 aggr_level; /* Traffic aggregation scheduler level */
1148 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
1149 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1150 };
1151
1152 struct nix_txsch_free_req {
1153 struct mbox_msghdr hdr;
1154 #define TXSCHQ_FREE_ALL BIT_ULL(0)
1155 u16 flags;
1156 /* Scheduler queue level to be freed */
1157 u16 schq_lvl;
1158 /* List of scheduler queues to be freed */
1159 u16 schq;
1160 };
1161
1162 struct nix_txschq_config {
1163 struct mbox_msghdr hdr;
1164 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1165 u8 read;
1166 #define TXSCHQ_IDX_SHIFT 16
1167 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1168 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1169 u8 num_regs;
1170 #define MAX_REGS_PER_MBOX_MSG 20
1171 u64 reg[MAX_REGS_PER_MBOX_MSG];
1172 u64 regval[MAX_REGS_PER_MBOX_MSG];
1173 /* All 0's => overwrite with new value */
1174 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1175 };
1176
1177 struct nix_vtag_config {
1178 struct mbox_msghdr hdr;
1179 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1180 u8 vtag_size;
1181 /* cfg_type is '0' for tx vlan cfg
1182 * cfg_type is '1' for rx vlan cfg
1183 */
1184 u8 cfg_type;
1185 union {
1186 /* valid when cfg_type is '0' */
1187 struct {
1188 u64 vtag0;
1189 u64 vtag1;
1190
1191 /* cfg_vtag0 & cfg_vtag1 fields are valid
1192 * when free_vtag0 & free_vtag1 are '0's.
1193 */
1194 /* cfg_vtag0 = 1 to configure vtag0 */
1195 u8 cfg_vtag0 :1;
1196 /* cfg_vtag1 = 1 to configure vtag1 */
1197 u8 cfg_vtag1 :1;
1198
1199 /* vtag0_idx & vtag1_idx are only valid when
1200 * both cfg_vtag0 & cfg_vtag1 are '0's,
1201 * these fields are used along with free_vtag0
1202 * & free_vtag1 to free the nix lf's tx_vlan
1203 * configuration.
1204 *
1205 * Denotes the indices of tx_vtag def registers
1206 * that needs to be cleared and freed.
1207 */
1208 int vtag0_idx;
1209 int vtag1_idx;
1210
1211 /* free_vtag0 & free_vtag1 fields are valid
1212 * when cfg_vtag0 & cfg_vtag1 are '0's.
1213 */
1214 /* free_vtag0 = 1 clears vtag0 configuration
1215 * vtag0_idx denotes the index to be cleared.
1216 */
1217 u8 free_vtag0 :1;
1218 /* free_vtag1 = 1 clears vtag1 configuration
1219 * vtag1_idx denotes the index to be cleared.
1220 */
1221 u8 free_vtag1 :1;
1222 } tx;
1223
1224 /* valid when cfg_type is '1' */
1225 struct {
1226 /* rx vtag type index, valid values are in 0..7 range */
1227 u8 vtag_type;
1228 /* rx vtag strip */
1229 u8 strip_vtag :1;
1230 /* rx vtag capture */
1231 u8 capture_vtag :1;
1232 } rx;
1233 };
1234 };
1235
1236 struct nix_vtag_config_rsp {
1237 struct mbox_msghdr hdr;
1238 int vtag0_idx;
1239 int vtag1_idx;
1240 /* Indices of tx_vtag def registers used to configure
1241 * tx vtag0 & vtag1 headers, these indices are valid
1242 * when nix_vtag_config mbox requested for vtag0 and/
1243 * or vtag1 configuration.
1244 */
1245 };
1246
1247 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1248
1249 struct nix_rss_flowkey_cfg {
1250 struct mbox_msghdr hdr;
1251 int mcam_index; /* MCAM entry index to modify */
1252 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1253 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1254 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1255 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1256 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1257 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1258 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1259 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1260 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1261 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1262 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1263 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1264 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1265 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1266 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1267 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1268 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1269 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1270 #define NIX_FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
1271 #define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1272 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1273 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1274 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
1275 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1276 #define NIX_FLOW_KEY_TYPE_ROCEV2 BIT(24)
1277 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1278 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1279 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1280 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1281 u32 flowkey_cfg; /* Flowkey types selected */
1282 u8 group; /* RSS context or group */
1283 };
1284
1285 struct nix_rss_flowkey_cfg_rsp {
1286 struct mbox_msghdr hdr;
1287 u8 alg_idx; /* Selected algo index */
1288 };
1289
1290 struct nix_set_mac_addr {
1291 struct mbox_msghdr hdr;
1292 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1293 };
1294
1295 struct nix_get_mac_addr_rsp {
1296 struct mbox_msghdr hdr;
1297 u8 mac_addr[ETH_ALEN];
1298 };
1299
1300 struct nix_mark_format_cfg {
1301 struct mbox_msghdr hdr;
1302 u8 offset;
1303 u8 y_mask;
1304 u8 y_val;
1305 u8 r_mask;
1306 u8 r_val;
1307 };
1308
1309 struct nix_mark_format_cfg_rsp {
1310 struct mbox_msghdr hdr;
1311 u8 mark_format_idx;
1312 };
1313
1314 struct nix_rx_mode {
1315 struct mbox_msghdr hdr;
1316 #define NIX_RX_MODE_UCAST BIT(0)
1317 #define NIX_RX_MODE_PROMISC BIT(1)
1318 #define NIX_RX_MODE_ALLMULTI BIT(2)
1319 #define NIX_RX_MODE_USE_MCE BIT(3)
1320 u16 mode;
1321 };
1322
1323 struct nix_rx_cfg {
1324 struct mbox_msghdr hdr;
1325 #define NIX_RX_OL3_VERIFY BIT(0)
1326 #define NIX_RX_OL4_VERIFY BIT(1)
1327 #define NIX_RX_DROP_RE BIT(2)
1328 u8 len_verify; /* Outer L3/L4 len check */
1329 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1330 u8 csum_verify; /* Outer L4 checksum verification */
1331 };
1332
1333 struct nix_frs_cfg {
1334 struct mbox_msghdr hdr;
1335 u8 update_smq; /* Update SMQ's min/max lens */
1336 u8 update_minlen; /* Set minlen also */
1337 u8 sdp_link; /* Set SDP RX link */
1338 u16 maxlen;
1339 u16 minlen;
1340 };
1341
1342 struct nix_lso_format_cfg {
1343 struct mbox_msghdr hdr;
1344 u64 field_mask;
1345 #define NIX_LSO_FIELD_MAX 8
1346 u64 fields[NIX_LSO_FIELD_MAX];
1347 };
1348
1349 struct nix_lso_format_cfg_rsp {
1350 struct mbox_msghdr hdr;
1351 u8 lso_format_idx;
1352 };
1353
1354 struct nix_bp_cfg_req {
1355 struct mbox_msghdr hdr;
1356 u16 chan_base; /* Starting channel number */
1357 u8 chan_cnt; /* Number of channels */
1358 u8 bpid_per_chan;
1359 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1360 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1361 };
1362
1363 /* Maximum channels any single NIX interface can have */
1364 #define NIX_MAX_BPID_CHAN 256
1365 struct nix_bp_cfg_rsp {
1366 struct mbox_msghdr hdr;
1367 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1368 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1369 };
1370
1371 struct nix_mcast_grp_create_req {
1372 struct mbox_msghdr hdr;
1373 #define NIX_MCAST_INGRESS 0
1374 #define NIX_MCAST_EGRESS 1
1375 u8 dir;
1376 u8 reserved[11];
1377 /* Reserving few bytes for future requirement */
1378 };
1379
1380 struct nix_mcast_grp_create_rsp {
1381 struct mbox_msghdr hdr;
1382 /* This mcast_grp_idx should be passed during MCAM
1383 * write entry for multicast. AF will identify the
1384 * corresponding multicast table index associated
1385 * with the group id and program the same to MCAM entry.
1386 * This group id is also needed during group delete
1387 * and update request.
1388 */
1389 u32 mcast_grp_idx;
1390 };
1391
1392 struct nix_mcast_grp_destroy_req {
1393 struct mbox_msghdr hdr;
1394 /* Group id returned by nix_mcast_grp_create_rsp */
1395 u32 mcast_grp_idx;
1396 /* If AF is requesting for destroy, then set
1397 * it to '1'. Otherwise keep it to '0'
1398 */
1399 u8 is_af;
1400 };
1401
1402 struct nix_mcast_grp_update_req {
1403 struct mbox_msghdr hdr;
1404 /* Group id returned by nix_mcast_grp_create_rsp */
1405 u32 mcast_grp_idx;
1406 /* Number of multicast/mirror entries requested */
1407 u32 num_mce_entry;
1408 #define NIX_MCE_ENTRY_MAX 64
1409 #define NIX_RX_RQ 0
1410 #define NIX_RX_RSS 1
1411 /* Receive queue or RSS index within pf_func */
1412 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1413 /* pcifunc is required for both ingress and egress multicast */
1414 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1415 /* channel is required for egress multicast */
1416 u16 channel[NIX_MCE_ENTRY_MAX];
1417 #define NIX_MCAST_OP_ADD_ENTRY 0
1418 #define NIX_MCAST_OP_DEL_ENTRY 1
1419 /* Destination type. 0:Receive queue, 1:RSS*/
1420 u8 dest_type[NIX_MCE_ENTRY_MAX];
1421 u8 op;
1422 /* If AF is requesting for update, then set
1423 * it to '1'. Otherwise keep it to '0'
1424 */
1425 u8 is_af;
1426 };
1427
1428 struct nix_mcast_grp_update_rsp {
1429 struct mbox_msghdr hdr;
1430 u32 mce_start_index;
1431 };
1432
1433 /* Global NIX inline IPSec configuration */
1434 struct nix_inline_ipsec_cfg {
1435 struct mbox_msghdr hdr;
1436 u32 cpt_credit;
1437 struct {
1438 u8 egrp;
1439 u16 opcode;
1440 u16 param1;
1441 u16 param2;
1442 } gen_cfg;
1443 struct {
1444 u16 cpt_pf_func;
1445 u8 cpt_slot;
1446 } inst_qsel;
1447 u8 enable;
1448 u16 bpid;
1449 u32 credit_th;
1450 };
1451
1452 /* Per NIX LF inline IPSec configuration */
1453 struct nix_inline_ipsec_lf_cfg {
1454 struct mbox_msghdr hdr;
1455 u64 sa_base_addr;
1456 struct {
1457 u32 tag_const;
1458 u16 lenm1_max;
1459 u8 sa_pow2_size;
1460 u8 tt;
1461 } ipsec_cfg0;
1462 struct {
1463 u32 sa_idx_max;
1464 u8 sa_idx_w;
1465 } ipsec_cfg1;
1466 u8 enable;
1467 };
1468
1469 struct nix_hw_info {
1470 struct mbox_msghdr hdr;
1471 u16 vwqe_delay;
1472 u16 max_mtu;
1473 u16 min_mtu;
1474 u32 rpm_dwrr_mtu;
1475 u32 sdp_dwrr_mtu;
1476 u32 lbk_dwrr_mtu;
1477 u32 rsvd32[1];
1478 u64 rsvd[15]; /* Add reserved fields for future expansion */
1479 };
1480
1481 struct nix_bandprof_alloc_req {
1482 struct mbox_msghdr hdr;
1483 /* Count of profiles needed per layer */
1484 u16 prof_count[BAND_PROF_NUM_LAYERS];
1485 };
1486
1487 struct nix_bandprof_alloc_rsp {
1488 struct mbox_msghdr hdr;
1489 u16 prof_count[BAND_PROF_NUM_LAYERS];
1490
1491 /* There is no need to allocate morethan 1 bandwidth profile
1492 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1493 * profiles to 64 per PF_FUNC.
1494 */
1495 #define MAX_BANDPROF_PER_PFFUNC 64
1496 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1497 };
1498
1499 struct nix_bandprof_free_req {
1500 struct mbox_msghdr hdr;
1501 u8 free_all;
1502 u16 prof_count[BAND_PROF_NUM_LAYERS];
1503 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1504 };
1505
1506 struct nix_bandprof_get_hwinfo_rsp {
1507 struct mbox_msghdr hdr;
1508 u16 prof_count[BAND_PROF_NUM_LAYERS];
1509 u32 policer_timeunit;
1510 };
1511
1512 struct nix_stats_req {
1513 struct mbox_msghdr hdr;
1514 u8 reset;
1515 u16 pcifunc;
1516 u64 rsvd;
1517 };
1518
1519 struct nix_stats_rsp {
1520 struct mbox_msghdr hdr;
1521 u16 pcifunc;
1522 struct {
1523 u64 octs;
1524 u64 ucast;
1525 u64 bcast;
1526 u64 mcast;
1527 u64 drop;
1528 u64 drop_octs;
1529 u64 drop_mcast;
1530 u64 drop_bcast;
1531 u64 err;
1532 u64 rsvd[5];
1533 } rx;
1534 struct {
1535 u64 ucast;
1536 u64 bcast;
1537 u64 mcast;
1538 u64 drop;
1539 u64 octs;
1540 } tx;
1541 };
1542
1543 /* NPC mbox message structs */
1544
1545 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1546 #define NPC_MCAM_INVALID_MAP 0xFFFF
1547
1548 /* NPC mailbox error codes
1549 * Range 701 - 800.
1550 */
1551 enum npc_af_status {
1552 NPC_MCAM_INVALID_REQ = -701,
1553 NPC_MCAM_ALLOC_DENIED = -702,
1554 NPC_MCAM_ALLOC_FAILED = -703,
1555 NPC_MCAM_PERM_DENIED = -704,
1556 NPC_FLOW_INTF_INVALID = -707,
1557 NPC_FLOW_CHAN_INVALID = -708,
1558 NPC_FLOW_NO_NIXLF = -709,
1559 NPC_FLOW_NOT_SUPPORTED = -710,
1560 NPC_FLOW_VF_PERM_DENIED = -711,
1561 NPC_FLOW_VF_NOT_INIT = -712,
1562 NPC_FLOW_VF_OVERLAP = -713,
1563 };
1564
1565 struct npc_mcam_alloc_entry_req {
1566 struct mbox_msghdr hdr;
1567 #define NPC_MAX_NONCONTIG_ENTRIES 256
1568 u8 contig; /* Contiguous entries ? */
1569 #define NPC_MCAM_ANY_PRIO 0
1570 #define NPC_MCAM_LOWER_PRIO 1
1571 #define NPC_MCAM_HIGHER_PRIO 2
1572 u8 ref_prio; /* Lower or higher w.r.t ref_entry */
1573 u16 ref_entry;
1574 u16 count; /* Number of entries requested */
1575 u8 kw_type; /* entry key type, valid for cn20k */
1576 u8 virt; /* Request virtual index */
1577 };
1578
1579 struct npc_mcam_alloc_entry_rsp {
1580 struct mbox_msghdr hdr;
1581 u16 entry; /* Entry allocated or start index if contiguous.
1582 * Invalid incase of non-contiguous.
1583 */
1584 u16 count; /* Number of entries allocated */
1585 u16 free_count; /* Number of entries available */
1586 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1587 };
1588
1589 struct npc_mcam_free_entry_req {
1590 struct mbox_msghdr hdr;
1591 u16 entry; /* Entry index to be freed */
1592 u8 all; /* If all entries allocated to this PFVF to be freed */
1593 };
1594
1595 struct mcam_entry_mdata {
1596 u64 *kw;
1597 u64 *kw_mask;
1598 u64 *action;
1599 u64 *vtag_action;
1600 u8 max_kw;
1601 };
1602
1603 enum npc_kws_in_key_sz {
1604 NPC_KWS_IN_KEY_SZ_7 = 7,
1605 NPC_KWS_IN_KEY_SZ_8 = 8,
1606 NPC_KWS_IN_KEY_SZ_MAX,
1607 };
1608
1609 struct mcam_entry {
1610 u64 kw[NPC_KWS_IN_KEY_SZ_7];
1611 u64 kw_mask[NPC_KWS_IN_KEY_SZ_7];
1612 u64 action;
1613 u64 vtag_action;
1614 };
1615
1616 struct cn20k_mcam_entry {
1617 u64 kw[NPC_KWS_IN_KEY_SZ_8];
1618 u64 kw_mask[NPC_KWS_IN_KEY_SZ_8];
1619 u64 action;
1620 u64 vtag_action;
1621 u64 action2;
1622 };
1623
1624 struct npc_cn20k_mcam_write_entry_req {
1625 struct mbox_msghdr hdr;
1626 struct cn20k_mcam_entry entry_data;
1627 u16 entry; /* MCAM entry to write this match key */
1628 u16 cntr; /* Counter for this MCAM entry */
1629 u8 intf; /* Rx or Tx interface */
1630 u8 enable_entry;/* Enable this MCAM entry ? */
1631 u8 hw_prio; /* hardware priority, valid for cn20k */
1632 u8 req_kw_type; /* Type of kw which should be written */
1633 u64 reserved; /* reserved for future use */
1634 };
1635
1636 struct npc_mcam_write_entry_req {
1637 struct mbox_msghdr hdr;
1638 struct mcam_entry entry_data;
1639 u16 entry; /* MCAM entry to write this match key */
1640 u16 cntr; /* Counter for this MCAM entry */
1641 u8 intf; /* Rx or Tx interface */
1642 u8 enable_entry;/* Enable this MCAM entry ? */
1643 u8 set_cntr; /* Set counter for this entry ? */
1644 u8 hw_prio; /* hardware priority, valid for cn20k */
1645 u64 reserved; /* reserved for future use */
1646 };
1647
1648 /* Enable/Disable a given entry */
1649 struct npc_mcam_ena_dis_entry_req {
1650 struct mbox_msghdr hdr;
1651 u16 entry;
1652 };
1653
1654 struct npc_mcam_shift_entry_req {
1655 struct mbox_msghdr hdr;
1656 #define NPC_MCAM_MAX_SHIFTS 64
1657 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1658 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1659 u16 shift_count; /* Number of entries to shift */
1660 };
1661
1662 struct npc_mcam_shift_entry_rsp {
1663 struct mbox_msghdr hdr;
1664 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1665 };
1666
1667 struct npc_mcam_alloc_counter_req {
1668 struct mbox_msghdr hdr;
1669 u8 contig; /* Contiguous counters ? */
1670 #define NPC_MAX_NONCONTIG_COUNTERS 64
1671 u16 count; /* Number of counters requested */
1672 };
1673
1674 struct npc_mcam_alloc_counter_rsp {
1675 struct mbox_msghdr hdr;
1676 u16 cntr; /* Counter allocated or start index if contiguous.
1677 * Invalid incase of non-contiguous.
1678 */
1679 u16 count; /* Number of counters allocated */
1680 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1681 };
1682
1683 struct npc_mcam_oper_counter_req {
1684 struct mbox_msghdr hdr;
1685 u16 cntr; /* Free a counter or clear/fetch it's stats */
1686 };
1687
1688 struct npc_mcam_oper_counter_rsp {
1689 struct mbox_msghdr hdr;
1690 u64 stat; /* valid only while fetching counter's stats */
1691 };
1692
1693 struct npc_mcam_unmap_counter_req {
1694 struct mbox_msghdr hdr;
1695 u16 cntr;
1696 u16 entry; /* Entry and counter to be unmapped */
1697 u8 all; /* Unmap all entries using this counter ? */
1698 };
1699
1700 struct npc_mcam_alloc_and_write_entry_req {
1701 struct mbox_msghdr hdr;
1702 struct mcam_entry entry_data;
1703 u16 ref_entry;
1704 u8 ref_prio; /* Lower or higher w.r.t ref_entry */
1705 u8 intf; /* Rx or Tx interface */
1706 u8 enable_entry;/* Enable this MCAM entry ? */
1707 u8 alloc_cntr; /* Allocate counter and map ? */
1708 };
1709
1710 struct npc_cn20k_mcam_alloc_and_write_entry_req {
1711 struct mbox_msghdr hdr;
1712 struct cn20k_mcam_entry entry_data;
1713 u16 ref_entry;
1714 u8 ref_prio; /* Lower or higher w.r.t ref_entry */
1715 u8 intf; /* Rx or Tx interface */
1716 u8 enable_entry;/* Enable this MCAM entry ? */
1717 u8 hw_prio; /* hardware priority, valid for cn20k */
1718 u8 virt; /* Allocate virtual index */
1719 u8 req_kw_type; /* Key type to be written */
1720 u16 reserved[4]; /* reserved for future use */
1721 };
1722
1723 struct npc_cn20k_mcam_read_entry_rsp {
1724 struct mbox_msghdr hdr;
1725 struct cn20k_mcam_entry entry_data;
1726 u8 intf;
1727 u8 enable;
1728 u8 hw_prio; /* valid for cn20k */
1729 };
1730
1731 struct npc_cn20k_mcam_read_base_rule_rsp {
1732 struct mbox_msghdr hdr;
1733 struct cn20k_mcam_entry entry;
1734 };
1735
1736 struct npc_mcam_alloc_and_write_entry_rsp {
1737 struct mbox_msghdr hdr;
1738 u16 entry;
1739 u16 cntr;
1740 };
1741
1742 struct npc_get_kex_cfg_rsp {
1743 struct mbox_msghdr hdr;
1744 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1745 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1746 #define NPC_MAX_INTF 2
1747 #define NPC_MAX_LID 8
1748 #define NPC_MAX_LT 16
1749 #define NPC_MAX_LD 2
1750 #define NPC_MAX_LFL 16
1751 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1752 u64 kex_ld_flags[NPC_MAX_LD];
1753 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1754 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1755 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1756 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1757 #define MKEX_NAME_LEN 128
1758 u8 mkex_pfl_name[MKEX_NAME_LEN];
1759 };
1760
1761 struct npc_cn20k_get_kex_cfg_rsp {
1762 struct mbox_msghdr hdr;
1763 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1764 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1765 #define NPC_MAX_EXTRACTOR 24
1766 /* MKEX Extractor data */
1767 u64 intf_extr_lid[NPC_MAX_INTF][NPC_MAX_EXTRACTOR];
1768 /* KEX configuration per extractor */
1769 u64 intf_extr_lt[NPC_MAX_INTF][NPC_MAX_EXTRACTOR][NPC_MAX_LT];
1770 #define MKEX_NAME_LEN 128
1771 u8 mkex_pfl_name[MKEX_NAME_LEN];
1772 };
1773
1774 struct ptp_get_cap_rsp {
1775 struct mbox_msghdr hdr;
1776 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1777 u64 cap;
1778 };
1779
1780 struct get_rep_cnt_rsp {
1781 struct mbox_msghdr hdr;
1782 u16 rep_cnt;
1783 u16 rep_pf_map[64];
1784 u64 rsvd;
1785 };
1786
1787 struct esw_cfg_req {
1788 struct mbox_msghdr hdr;
1789 u8 ena;
1790 u64 rsvd;
1791 };
1792
1793 struct rep_evt_data {
1794 u8 port_state;
1795 u8 vf_state;
1796 u16 rx_mode;
1797 u16 rx_flags;
1798 u16 mtu;
1799 u8 mac[ETH_ALEN];
1800 u64 rsvd[5];
1801 };
1802
1803 struct rep_event {
1804 struct mbox_msghdr hdr;
1805 u16 pcifunc;
1806 #define RVU_EVENT_PORT_STATE BIT_ULL(0)
1807 #define RVU_EVENT_PFVF_STATE BIT_ULL(1)
1808 #define RVU_EVENT_MTU_CHANGE BIT_ULL(2)
1809 #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3)
1810 #define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4)
1811 u16 event;
1812 struct rep_evt_data evt_data;
1813 };
1814
1815 struct flow_msg {
1816 unsigned char dmac[6];
1817 unsigned char smac[6];
1818 __be16 etype;
1819 __be16 vlan_etype;
1820 __be16 vlan_tci;
1821 union {
1822 __be32 ip4src;
1823 __be32 ip6src[4];
1824 };
1825 union {
1826 __be32 ip4dst;
1827 __be32 ip6dst[4];
1828 };
1829 union {
1830 __be32 spi;
1831 };
1832
1833 u8 tos;
1834 u8 ip_ver;
1835 u8 ip_proto;
1836 u8 tc;
1837 __be16 sport;
1838 __be16 dport;
1839 union {
1840 u8 ip_flag;
1841 u8 next_header;
1842 };
1843 __be16 vlan_itci;
1844 #define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1845 #define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1846 #define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1847 #define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1848 #define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1849 u32 mpls_lse[4];
1850 u8 icmp_type;
1851 u8 icmp_code;
1852 __be16 tcp_flags;
1853 u16 sq_id;
1854 };
1855
1856 struct npc_install_flow_req {
1857 struct mbox_msghdr hdr;
1858 struct flow_msg packet;
1859 struct flow_msg mask;
1860 u64 features;
1861 u16 entry;
1862 u16 channel;
1863 u16 chan_mask;
1864 u8 intf;
1865 u8 set_cntr; /* If counter is available set counter for this entry ? */
1866 u8 default_rule;
1867 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1868 u16 vf;
1869 /* action */
1870 u32 index;
1871 u16 match_id;
1872 u8 flow_key_alg;
1873 u8 op;
1874 /* vtag rx action */
1875 u8 vtag0_type;
1876 u8 vtag0_valid;
1877 u8 vtag1_type;
1878 u8 vtag1_valid;
1879 /* vtag tx action */
1880 u16 vtag0_def;
1881 u8 vtag0_op;
1882 u16 vtag1_def;
1883 u8 vtag1_op;
1884 /* old counter value */
1885 u16 cntr_val;
1886 u8 hw_prio;
1887 u8 req_kw_type; /* Key type to be written */
1888 u8 alloc_entry; /* only for cn20k */
1889 /* For now use any priority, once AF driver is changed to
1890 * allocate least priority entry instead of mid zone then make
1891 * NPC_MCAM_LEAST_PRIO as 3
1892 */
1893 #define NPC_MCAM_LEAST_PRIO NPC_MCAM_ANY_PRIO
1894 u16 ref_prio;
1895 u16 ref_entry;
1896 };
1897
1898 struct npc_install_flow_rsp {
1899 struct mbox_msghdr hdr;
1900 int counter; /* negative if no counter else counter number */
1901 u16 entry;
1902 u8 kw_type;
1903 };
1904
1905 struct npc_get_num_kws_req {
1906 struct mbox_msghdr hdr;
1907 struct npc_install_flow_req fl;
1908 u32 rsvd[4];
1909 };
1910
1911 struct npc_get_num_kws_rsp {
1912 struct mbox_msghdr hdr;
1913 int kws;
1914 u32 rsvd[4];
1915 };
1916
1917 struct npc_get_dft_rl_idxs_rsp {
1918 struct mbox_msghdr hdr;
1919 u16 bcast;
1920 u16 mcast;
1921 u16 promisc;
1922 u16 ucast;
1923 u16 vf_ucast;
1924 u16 rsvd[7];
1925 };
1926
1927 struct npc_get_pfl_info_rsp {
1928 struct mbox_msghdr hdr;
1929 u16 x4_slots;
1930 u8 kw_type;
1931 u8 rsvd1[3];
1932 u32 rsvd2[4];
1933 };
1934
1935 struct npc_delete_flow_req {
1936 struct mbox_msghdr hdr;
1937 u16 entry;
1938 u16 start;/*Disable range of entries */
1939 u16 end;
1940 u8 all; /* PF + VFs */
1941 };
1942
1943 struct npc_delete_flow_rsp {
1944 struct mbox_msghdr hdr;
1945 u16 cntr_val;
1946 };
1947
1948 struct npc_mcam_read_entry_req {
1949 struct mbox_msghdr hdr;
1950 u16 entry; /* MCAM entry to read */
1951 };
1952
1953 struct npc_mcam_read_entry_rsp {
1954 struct mbox_msghdr hdr;
1955 struct mcam_entry entry_data;
1956 u8 intf;
1957 u8 enable;
1958 u8 hw_prio; /* valid for cn20k */
1959 };
1960
1961 /* Available entries to use */
1962 struct npc_cn20k_get_fcnt_rsp {
1963 struct mbox_msghdr hdr;
1964 int free_x2;
1965 int free_x4;
1966 int free_subbanks;
1967 };
1968
1969 struct npc_mcam_read_base_rule_rsp {
1970 struct mbox_msghdr hdr;
1971 struct mcam_entry entry;
1972 };
1973
1974 struct npc_mcam_get_stats_req {
1975 struct mbox_msghdr hdr;
1976 u16 entry; /* mcam entry */
1977 };
1978
1979 struct npc_mcam_get_stats_rsp {
1980 struct mbox_msghdr hdr;
1981 u64 stat; /* counter stats */
1982 u8 stat_ena; /* enabled */
1983 };
1984
1985 struct npc_get_field_hash_info_req {
1986 struct mbox_msghdr hdr;
1987 u8 intf;
1988 };
1989
1990 struct npc_get_field_hash_info_rsp {
1991 struct mbox_msghdr hdr;
1992 u64 secret_key[3];
1993 #define NPC_MAX_HASH 2
1994 #define NPC_MAX_HASH_MASK 2
1995 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1996 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1997 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1998 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1999 };
2000
2001 enum ptp_op {
2002 PTP_OP_ADJFINE = 0,
2003 PTP_OP_GET_CLOCK = 1,
2004 PTP_OP_GET_TSTMP = 2,
2005 PTP_OP_SET_THRESH = 3,
2006 PTP_OP_PPS_ON = 4,
2007 PTP_OP_ADJTIME = 5,
2008 PTP_OP_SET_CLOCK = 6,
2009 };
2010
2011 struct ptp_req {
2012 struct mbox_msghdr hdr;
2013 u8 op;
2014 s64 scaled_ppm;
2015 u64 thresh;
2016 u64 period;
2017 int pps_on;
2018 s64 delta;
2019 u64 clk;
2020 };
2021
2022 struct ptp_rsp {
2023 struct mbox_msghdr hdr;
2024 u64 clk;
2025 u64 tsc;
2026 };
2027
2028 struct npc_get_field_status_req {
2029 struct mbox_msghdr hdr;
2030 u8 intf;
2031 u8 field;
2032 };
2033
2034 struct npc_get_field_status_rsp {
2035 struct mbox_msghdr hdr;
2036 u8 enable;
2037 };
2038
2039 struct set_vf_perm {
2040 struct mbox_msghdr hdr;
2041 u16 vf;
2042 #define RESET_VF_PERM BIT_ULL(0)
2043 #define VF_TRUSTED BIT_ULL(1)
2044 u64 flags;
2045 };
2046
2047 struct lmtst_tbl_setup_req {
2048 struct mbox_msghdr hdr;
2049 u64 dis_sched_early_comp :1;
2050 u64 sch_ena :1;
2051 u64 dis_line_pref :1;
2052 u64 ssow_pf_func :13;
2053 u16 base_pcifunc;
2054 u8 use_local_lmt_region;
2055 u64 lmt_iova;
2056 u64 rsvd[4];
2057 };
2058
2059 struct ndc_sync_op {
2060 struct mbox_msghdr hdr;
2061 u8 nix_lf_tx_sync;
2062 u8 nix_lf_rx_sync;
2063 u8 npa_lf_sync;
2064 };
2065
2066 /* CPT mailbox error codes
2067 * Range 901 - 1000.
2068 */
2069 enum cpt_af_status {
2070 CPT_AF_ERR_PARAM = -901,
2071 CPT_AF_ERR_GRP_INVALID = -902,
2072 CPT_AF_ERR_LF_INVALID = -903,
2073 CPT_AF_ERR_ACCESS_DENIED = -904,
2074 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
2075 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
2076 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
2077 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
2078 };
2079
2080 /* CPT mbox message formats */
2081 struct cpt_rd_wr_reg_msg {
2082 struct mbox_msghdr hdr;
2083 u64 reg_offset;
2084 u64 *ret_val;
2085 u64 val;
2086 u8 is_write;
2087 int blkaddr;
2088 };
2089
2090 struct cpt_lf_alloc_req_msg {
2091 struct mbox_msghdr hdr;
2092 u16 nix_pf_func;
2093 u16 sso_pf_func;
2094 u16 eng_grpmsk;
2095 u8 blkaddr;
2096 u8 ctx_ilen_valid : 1;
2097 u8 ctx_ilen : 7;
2098 };
2099
2100 #define CPT_INLINE_INBOUND 0
2101 #define CPT_INLINE_OUTBOUND 1
2102
2103 /* Mailbox message request format for CPT IPsec
2104 * inline inbound and outbound configuration.
2105 */
2106 struct cpt_inline_ipsec_cfg_msg {
2107 struct mbox_msghdr hdr;
2108 u8 enable;
2109 u8 slot;
2110 u8 dir;
2111 u8 sso_pf_func_ovrd;
2112 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
2113 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
2114 };
2115
2116 /* Mailbox message request and response format for CPT stats. */
2117 struct cpt_sts_req {
2118 struct mbox_msghdr hdr;
2119 u8 blkaddr;
2120 };
2121
2122 struct cpt_sts_rsp {
2123 struct mbox_msghdr hdr;
2124 u64 inst_req_pc;
2125 u64 inst_lat_pc;
2126 u64 rd_req_pc;
2127 u64 rd_lat_pc;
2128 u64 rd_uc_pc;
2129 u64 active_cycles_pc;
2130 u64 ctx_mis_pc;
2131 u64 ctx_hit_pc;
2132 u64 ctx_aop_pc;
2133 u64 ctx_aop_lat_pc;
2134 u64 ctx_ifetch_pc;
2135 u64 ctx_ifetch_lat_pc;
2136 u64 ctx_ffetch_pc;
2137 u64 ctx_ffetch_lat_pc;
2138 u64 ctx_wback_pc;
2139 u64 ctx_wback_lat_pc;
2140 u64 ctx_psh_pc;
2141 u64 ctx_psh_lat_pc;
2142 u64 ctx_err;
2143 u64 ctx_enc_id;
2144 u64 ctx_flush_timer;
2145 u64 rxc_time;
2146 u64 rxc_time_cfg;
2147 u64 rxc_active_sts;
2148 u64 rxc_zombie_sts;
2149 u64 busy_sts_ae;
2150 u64 free_sts_ae;
2151 u64 busy_sts_se;
2152 u64 free_sts_se;
2153 u64 busy_sts_ie;
2154 u64 free_sts_ie;
2155 u64 exe_err_info;
2156 u64 cptclk_cnt;
2157 u64 diag;
2158 u64 rxc_dfrg;
2159 u64 x2p_link_cfg0;
2160 u64 x2p_link_cfg1;
2161 };
2162
2163 /* Mailbox message request format to configure reassembly timeout. */
2164 struct cpt_rxc_time_cfg_req {
2165 struct mbox_msghdr hdr;
2166 int blkaddr;
2167 u32 step;
2168 u16 zombie_thres;
2169 u16 zombie_limit;
2170 u16 active_thres;
2171 u16 active_limit;
2172 };
2173
2174 /* Mailbox message request format to request for CPT_INST_S lmtst. */
2175 struct cpt_inst_lmtst_req {
2176 struct mbox_msghdr hdr;
2177 u64 inst[8];
2178 u64 rsvd;
2179 };
2180
2181 /* Mailbox message format to request for CPT LF reset */
2182 struct cpt_lf_rst_req {
2183 struct mbox_msghdr hdr;
2184 u32 slot;
2185 u32 rsvd;
2186 };
2187
2188 /* Mailbox message format to request for CPT faulted engines */
2189 struct cpt_flt_eng_info_req {
2190 struct mbox_msghdr hdr;
2191 int blkaddr;
2192 bool reset;
2193 u32 rsvd;
2194 };
2195
2196 struct cpt_flt_eng_info_rsp {
2197 struct mbox_msghdr hdr;
2198 #define CPT_AF_MAX_FLT_INT_VECS 3
2199 u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS];
2200 u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS];
2201 u64 rsvd;
2202 };
2203
2204 struct sdp_node_info {
2205 /* Node to which this PF belons to */
2206 u8 node_id;
2207 u8 max_vfs;
2208 u8 num_pf_rings;
2209 u8 pf_srn;
2210 #define SDP_MAX_VFS 128
2211 u8 vf_rings[SDP_MAX_VFS];
2212 };
2213
2214 struct sdp_chan_info_msg {
2215 struct mbox_msghdr hdr;
2216 struct sdp_node_info info;
2217 };
2218
2219 struct sdp_get_chan_info_msg {
2220 struct mbox_msghdr hdr;
2221 u16 chan_base;
2222 u16 num_chan;
2223 };
2224
2225 /* CGX mailbox error codes
2226 * Range 1101 - 1200.
2227 */
2228 enum cgx_af_status {
2229 LMAC_AF_ERR_INVALID_PARAM = -1101,
2230 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
2231 LMAC_AF_ERR_PERM_DENIED = -1103,
2232 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
2233 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
2234 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
2235 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
2236 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
2237 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
2238 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
2239 };
2240
2241 enum mcs_direction {
2242 MCS_RX,
2243 MCS_TX,
2244 };
2245
2246 enum mcs_rsrc_type {
2247 MCS_RSRC_TYPE_FLOWID,
2248 MCS_RSRC_TYPE_SECY,
2249 MCS_RSRC_TYPE_SC,
2250 MCS_RSRC_TYPE_SA,
2251 };
2252
2253 struct mcs_alloc_rsrc_req {
2254 struct mbox_msghdr hdr;
2255 u8 rsrc_type;
2256 u8 rsrc_cnt; /* Resources count */
2257 u8 mcs_id; /* MCS block ID */
2258 u8 dir; /* Macsec ingress or egress side */
2259 u8 all; /* Allocate all resource type one each */
2260 u64 rsvd;
2261 };
2262
2263 struct mcs_alloc_rsrc_rsp {
2264 struct mbox_msghdr hdr;
2265 u8 flow_ids[128]; /* Index of reserved entries */
2266 u8 secy_ids[128];
2267 u8 sc_ids[128];
2268 u8 sa_ids[256];
2269 u8 rsrc_type;
2270 u8 rsrc_cnt; /* No of entries reserved */
2271 u8 mcs_id;
2272 u8 dir;
2273 u8 all;
2274 u8 rsvd[256]; /* reserved fields for future expansion */
2275 };
2276
2277 struct mcs_free_rsrc_req {
2278 struct mbox_msghdr hdr;
2279 u8 rsrc_id; /* Index of the entry to be freed */
2280 u8 rsrc_type;
2281 u8 mcs_id;
2282 u8 dir;
2283 u8 all; /* Free all the cam resources */
2284 u64 rsvd;
2285 };
2286
2287 struct mcs_flowid_entry_write_req {
2288 struct mbox_msghdr hdr;
2289 u64 data[4];
2290 u64 mask[4];
2291 u64 sci; /* CNF10K-B for tx_secy_mem_map */
2292 u8 flow_id;
2293 u8 secy_id; /* secyid for which flowid is mapped */
2294 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
2295 u8 ena; /* Enable tcam entry */
2296 u8 ctrl_pkt;
2297 u8 mcs_id;
2298 u8 dir;
2299 u64 rsvd;
2300 };
2301
2302 struct mcs_secy_plcy_write_req {
2303 struct mbox_msghdr hdr;
2304 u64 plcy;
2305 u8 secy_id;
2306 u8 mcs_id;
2307 u8 dir;
2308 u64 rsvd;
2309 };
2310
2311 /* RX SC_CAM mapping */
2312 struct mcs_rx_sc_cam_write_req {
2313 struct mbox_msghdr hdr;
2314 u64 sci; /* SCI */
2315 u64 secy_id; /* secy index mapped to SC */
2316 u8 sc_id; /* SC CAM entry index */
2317 u8 mcs_id;
2318 u64 rsvd;
2319 };
2320
2321 struct mcs_sa_plcy_write_req {
2322 struct mbox_msghdr hdr;
2323 u64 plcy[2][9]; /* Support 2 SA policy */
2324 u8 sa_index[2];
2325 u8 sa_cnt;
2326 u8 mcs_id;
2327 u8 dir;
2328 u64 rsvd;
2329 };
2330
2331 struct mcs_tx_sc_sa_map {
2332 struct mbox_msghdr hdr;
2333 u8 sa_index0;
2334 u8 sa_index1;
2335 u8 rekey_ena;
2336 u8 sa_index0_vld;
2337 u8 sa_index1_vld;
2338 u8 tx_sa_active;
2339 u64 sectag_sci;
2340 u8 sc_id; /* used as index for SA_MEM_MAP */
2341 u8 mcs_id;
2342 u64 rsvd;
2343 };
2344
2345 struct mcs_rx_sc_sa_map {
2346 struct mbox_msghdr hdr;
2347 u8 sa_index;
2348 u8 sa_in_use;
2349 u8 sc_id;
2350 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
2351 u8 mcs_id;
2352 u64 rsvd;
2353 };
2354
2355 struct mcs_flowid_ena_dis_entry {
2356 struct mbox_msghdr hdr;
2357 u8 flow_id;
2358 u8 ena;
2359 u8 mcs_id;
2360 u8 dir;
2361 u64 rsvd;
2362 };
2363
2364 struct mcs_pn_table_write_req {
2365 struct mbox_msghdr hdr;
2366 u64 next_pn;
2367 u8 pn_id;
2368 u8 mcs_id;
2369 u8 dir;
2370 u64 rsvd;
2371 };
2372
2373 struct mcs_hw_info {
2374 struct mbox_msghdr hdr;
2375 u8 num_mcs_blks; /* Number of MCS blocks */
2376 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2377 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2378 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2379 u16 sa_entries; /* PN table entries = SA entries */
2380 u64 rsvd[16];
2381 };
2382
2383 struct mcs_set_active_lmac {
2384 struct mbox_msghdr hdr;
2385 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2386 u8 mcs_id;
2387 u16 chan_base; /* MCS channel base */
2388 u64 rsvd;
2389 };
2390
2391 struct mcs_set_lmac_mode {
2392 struct mbox_msghdr hdr;
2393 u8 mode; /* 1:Bypass 0:Operational */
2394 u8 lmac_id;
2395 u8 mcs_id;
2396 u64 rsvd;
2397 };
2398
2399 struct mcs_port_reset_req {
2400 struct mbox_msghdr hdr;
2401 u8 reset;
2402 u8 mcs_id;
2403 u8 port_id;
2404 u64 rsvd;
2405 };
2406
2407 struct mcs_port_cfg_set_req {
2408 struct mbox_msghdr hdr;
2409 u8 cstm_tag_rel_mode_sel;
2410 u8 custom_hdr_enb;
2411 u8 fifo_skid;
2412 u8 port_mode;
2413 u8 port_id;
2414 u8 mcs_id;
2415 u64 rsvd;
2416 };
2417
2418 struct mcs_port_cfg_get_req {
2419 struct mbox_msghdr hdr;
2420 u8 port_id;
2421 u8 mcs_id;
2422 u64 rsvd;
2423 };
2424
2425 struct mcs_port_cfg_get_rsp {
2426 struct mbox_msghdr hdr;
2427 u8 cstm_tag_rel_mode_sel;
2428 u8 custom_hdr_enb;
2429 u8 fifo_skid;
2430 u8 port_mode;
2431 u8 port_id;
2432 u8 mcs_id;
2433 u64 rsvd;
2434 };
2435
2436 struct mcs_custom_tag_cfg_get_req {
2437 struct mbox_msghdr hdr;
2438 u8 mcs_id;
2439 u8 dir;
2440 u64 rsvd;
2441 };
2442
2443 struct mcs_custom_tag_cfg_get_rsp {
2444 struct mbox_msghdr hdr;
2445 u16 cstm_etype[8];
2446 u8 cstm_indx[8];
2447 u8 cstm_etype_en;
2448 u8 mcs_id;
2449 u8 dir;
2450 u64 rsvd;
2451 };
2452
2453 /* MCS mailbox error codes
2454 * Range 1201 - 1300.
2455 */
2456 enum mcs_af_status {
2457 MCS_AF_ERR_INVALID_MCSID = -1201,
2458 MCS_AF_ERR_NOT_MAPPED = -1202,
2459 };
2460
2461 struct mcs_set_pn_threshold {
2462 struct mbox_msghdr hdr;
2463 u64 threshold;
2464 u8 xpn; /* '1' for setting xpn threshold */
2465 u8 mcs_id;
2466 u8 dir;
2467 u64 rsvd;
2468 };
2469
2470 enum mcs_ctrl_pkt_rulew_type {
2471 MCS_CTRL_PKT_RULE_TYPE_ETH,
2472 MCS_CTRL_PKT_RULE_TYPE_DA,
2473 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2474 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2475 MCS_CTRL_PKT_RULE_TYPE_MAC,
2476 };
2477
2478 struct mcs_alloc_ctrl_pkt_rule_req {
2479 struct mbox_msghdr hdr;
2480 u8 rule_type;
2481 u8 mcs_id; /* MCS block ID */
2482 u8 dir; /* Macsec ingress or egress side */
2483 u64 rsvd;
2484 };
2485
2486 struct mcs_alloc_ctrl_pkt_rule_rsp {
2487 struct mbox_msghdr hdr;
2488 u8 rule_idx;
2489 u8 rule_type;
2490 u8 mcs_id;
2491 u8 dir;
2492 u64 rsvd;
2493 };
2494
2495 struct mcs_free_ctrl_pkt_rule_req {
2496 struct mbox_msghdr hdr;
2497 u8 rule_idx;
2498 u8 rule_type;
2499 u8 mcs_id;
2500 u8 dir;
2501 u8 all;
2502 u64 rsvd;
2503 };
2504
2505 struct mcs_ctrl_pkt_rule_write_req {
2506 struct mbox_msghdr hdr;
2507 u64 data0;
2508 u64 data1;
2509 u64 data2;
2510 u8 rule_idx;
2511 u8 rule_type;
2512 u8 mcs_id;
2513 u8 dir;
2514 u64 rsvd;
2515 };
2516
2517 struct mcs_stats_req {
2518 struct mbox_msghdr hdr;
2519 u8 id;
2520 u8 mcs_id;
2521 u8 dir;
2522 u64 rsvd;
2523 };
2524
2525 struct mcs_flowid_stats {
2526 struct mbox_msghdr hdr;
2527 u64 tcam_hit_cnt;
2528 u64 rsvd;
2529 };
2530
2531 struct mcs_secy_stats {
2532 struct mbox_msghdr hdr;
2533 u64 ctl_pkt_bcast_cnt;
2534 u64 ctl_pkt_mcast_cnt;
2535 u64 ctl_pkt_ucast_cnt;
2536 u64 ctl_octet_cnt;
2537 u64 unctl_pkt_bcast_cnt;
2538 u64 unctl_pkt_mcast_cnt;
2539 u64 unctl_pkt_ucast_cnt;
2540 u64 unctl_octet_cnt;
2541 /* Valid only for RX */
2542 u64 octet_decrypted_cnt;
2543 u64 octet_validated_cnt;
2544 u64 pkt_port_disabled_cnt;
2545 u64 pkt_badtag_cnt;
2546 u64 pkt_nosa_cnt;
2547 u64 pkt_nosaerror_cnt;
2548 u64 pkt_tagged_ctl_cnt;
2549 u64 pkt_untaged_cnt;
2550 u64 pkt_ctl_cnt; /* CN10K-B */
2551 u64 pkt_notag_cnt; /* CNF10K-B */
2552 /* Valid only for TX */
2553 u64 octet_encrypted_cnt;
2554 u64 octet_protected_cnt;
2555 u64 pkt_noactivesa_cnt;
2556 u64 pkt_toolong_cnt;
2557 u64 pkt_untagged_cnt;
2558 u64 rsvd[4];
2559 };
2560
2561 struct mcs_port_stats {
2562 struct mbox_msghdr hdr;
2563 u64 tcam_miss_cnt;
2564 u64 parser_err_cnt;
2565 u64 preempt_err_cnt; /* CNF10K-B */
2566 u64 sectag_insert_err_cnt;
2567 u64 rsvd[4];
2568 };
2569
2570 /* Only for CN10K-B */
2571 struct mcs_sa_stats {
2572 struct mbox_msghdr hdr;
2573 /* RX */
2574 u64 pkt_invalid_cnt;
2575 u64 pkt_nosaerror_cnt;
2576 u64 pkt_notvalid_cnt;
2577 u64 pkt_ok_cnt;
2578 u64 pkt_nosa_cnt;
2579 /* TX */
2580 u64 pkt_encrypt_cnt;
2581 u64 pkt_protected_cnt;
2582 u64 rsvd[4];
2583 };
2584
2585 struct mcs_sc_stats {
2586 struct mbox_msghdr hdr;
2587 /* RX */
2588 u64 hit_cnt;
2589 u64 pkt_invalid_cnt;
2590 u64 pkt_late_cnt;
2591 u64 pkt_notvalid_cnt;
2592 u64 pkt_unchecked_cnt;
2593 u64 pkt_delay_cnt; /* CNF10K-B */
2594 u64 pkt_ok_cnt; /* CNF10K-B */
2595 u64 octet_decrypt_cnt; /* CN10K-B */
2596 u64 octet_validate_cnt; /* CN10K-B */
2597 /* TX */
2598 u64 pkt_encrypt_cnt;
2599 u64 pkt_protected_cnt;
2600 u64 octet_encrypt_cnt; /* CN10K-B */
2601 u64 octet_protected_cnt; /* CN10K-B */
2602 u64 rsvd[4];
2603 };
2604
2605 struct mcs_clear_stats {
2606 struct mbox_msghdr hdr;
2607 #define MCS_FLOWID_STATS 0
2608 #define MCS_SECY_STATS 1
2609 #define MCS_SC_STATS 2
2610 #define MCS_SA_STATS 3
2611 #define MCS_PORT_STATS 4
2612 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2613 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2614 u8 mcs_id;
2615 u8 dir;
2616 u8 all; /* All resources stats mapped to PF are cleared */
2617 };
2618
2619 struct mcs_intr_cfg {
2620 struct mbox_msghdr hdr;
2621 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2622 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2623 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2624 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2625 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2626 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2627 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2628 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2629 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2630 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2631 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2632 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2633 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2634 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2635 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2636 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2637 u64 intr_mask; /* Interrupt enable mask */
2638 u8 mcs_id;
2639 u8 lmac_id;
2640 u64 rsvd;
2641 };
2642
2643 struct mcs_intr_info {
2644 struct mbox_msghdr hdr;
2645 u64 intr_mask;
2646 int sa_id;
2647 u8 mcs_id;
2648 u8 lmac_id;
2649 u64 rsvd;
2650 };
2651
2652 #endif /* MBOX_H */
2653