1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/module.h>
4 #include <linux/phy.h>
5
6 #include "mtk.h"
7
8 #define MTK_GPHY_ID_MT7530 0x03a29412
9 #define MTK_GPHY_ID_MT7531 0x03a29441
10
11 #define MTK_PHY_PAGE_EXTENDED_2 0x0002
12 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
13 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
14
15 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
16
17 /* Registers on Token Ring debug nodes */
18 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
19 #define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
20
21 /* Registers on MDIO_MMD_VEND1 */
22 #define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
23 #define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
24 #define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
25 #define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
26
27 #define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
28 #define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
29
30 #define MTK_PHY_RXADC_CTRL_RG7 0xc6
31 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
32
33 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
34 #define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
35 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
36
mtk_gephy_config_init(struct phy_device * phydev)37 static void mtk_gephy_config_init(struct phy_device *phydev)
38 {
39 /* Enable HW auto downshift */
40 phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
41 MTK_PHY_AUX_CTRL_AND_STATUS,
42 0, MTK_PHY_ENABLE_DOWNSHIFT);
43
44 /* Increase SlvDPSready time */
45 mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
46 FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
47
48 /* Adjust 100_mse_threshold */
49 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
50 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
51 MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
52 MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
53 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
54 0xff) |
55 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
56 0xff));
57
58 /* If echo time is narrower than 0x3, it will be regarded as noise */
59 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
60 MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
61 MTK_MCC_NEARECHO_OFFSET_MASK,
62 FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
63 }
64
mt7530_phy_probe(struct phy_device * phydev)65 static int mt7530_phy_probe(struct phy_device *phydev)
66 {
67 /* The MT7530 internal GE PHY has broken EEE: with EEE advertised,
68 * some link partners fail to establish a stable link (on a 2-pair
69 * cable, 1000BASE-T training fails and the port loops instead of
70 * falling back). MediaTek recommends disabling EEE on this PHY.
71 * Clear the advertisement as early as possible, before anything
72 * can negotiate EEE with the link partner.
73 */
74 return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
75 }
76
mt7530_phy_config_init(struct phy_device * phydev)77 static int mt7530_phy_config_init(struct phy_device *phydev)
78 {
79 int ret;
80
81 mtk_gephy_config_init(phydev);
82
83 /* The probe() clear alone is not durable: phy_init_hw() replays only
84 * ->config_init after a PHY reset, with the register back at its
85 * EEE-advertising hardware default, and phy_probe() zeroes
86 * eee_disabled_modes (of_set_phy_eee_broken()) after ->probe already
87 * ran. Clear the advertisement again and mark EEE disabled, so that
88 * neither phylib nor userspace can re-enable it; dp83867 disables
89 * broken EEE from config_init() the same way.
90 */
91 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
92 if (ret)
93 return ret;
94
95 phy_disable_eee(phydev);
96
97 /* Increase post_update_timer */
98 phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
99 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
100
101 return 0;
102 }
103
mt7531_phy_config_init(struct phy_device * phydev)104 static int mt7531_phy_config_init(struct phy_device *phydev)
105 {
106 mtk_gephy_config_init(phydev);
107
108 /* PHY link down power saving enable */
109 phy_set_bits(phydev, 0x17, BIT(4));
110 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
111 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
112 FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
113
114 /* Set TX Pair delay selection */
115 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
116 MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
117 FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
118 FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
119 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
120 MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
121 FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
122 FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
123
124 return 0;
125 }
126
127 static struct phy_driver mtk_gephy_driver[] = {
128 {
129 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
130 .name = "MediaTek MT7530 PHY",
131 .probe = mt7530_phy_probe,
132 .config_init = mt7530_phy_config_init,
133 /* Interrupts are handled by the switch, not the PHY
134 * itself.
135 */
136 .config_intr = genphy_no_config_intr,
137 .handle_interrupt = genphy_handle_interrupt_no_ack,
138 .suspend = genphy_suspend,
139 .resume = genphy_resume,
140 .read_page = mtk_phy_read_page,
141 .write_page = mtk_phy_write_page,
142 },
143 {
144 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
145 .name = "MediaTek MT7531 PHY",
146 .config_init = mt7531_phy_config_init,
147 /* Interrupts are handled by the switch, not the PHY
148 * itself.
149 */
150 .config_intr = genphy_no_config_intr,
151 .handle_interrupt = genphy_handle_interrupt_no_ack,
152 .suspend = genphy_suspend,
153 .resume = genphy_resume,
154 .read_page = mtk_phy_read_page,
155 .write_page = mtk_phy_write_page,
156 },
157 };
158
159 module_phy_driver(mtk_gephy_driver);
160
161 static const struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
162 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
163 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
164 { }
165 };
166
167 MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
168 MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
169 MODULE_LICENSE("GPL");
170
171 MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
172