1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7 #include <linux/aperture.h>
8 #include <linux/component.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_platform.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/dma-mapping.h>
15
16 #include <drm/clients/drm_client_setup.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_fbdev_dma.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_gem.h>
23 #include <drm/drm_gem_dma_helper.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
25 #include <drm/drm_ioctl.h>
26 #include <drm/drm_of.h>
27 #include <drm/drm_probe_helper.h>
28 #include <drm/drm_vblank.h>
29
30 #include "mtk_crtc.h"
31 #include "mtk_ddp_comp.h"
32 #include "mtk_disp_drv.h"
33 #include "mtk_drm_drv.h"
34
35 #define DRIVER_NAME "mediatek"
36 #define DRIVER_DESC "Mediatek SoC DRM"
37 #define DRIVER_MAJOR 1
38 #define DRIVER_MINOR 0
39
40 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
41 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
42 };
43
44 static struct drm_framebuffer *
mtk_drm_mode_fb_create(struct drm_device * dev,struct drm_file * file,const struct drm_format_info * info,const struct drm_mode_fb_cmd2 * cmd)45 mtk_drm_mode_fb_create(struct drm_device *dev,
46 struct drm_file *file,
47 const struct drm_format_info *info,
48 const struct drm_mode_fb_cmd2 *cmd)
49 {
50 if (info->num_planes != 1)
51 return ERR_PTR(-EINVAL);
52
53 return drm_gem_fb_create(dev, file, info, cmd);
54 }
55
56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
57 .fb_create = mtk_drm_mode_fb_create,
58 .atomic_check = drm_atomic_helper_check,
59 .atomic_commit = drm_atomic_helper_commit,
60 };
61
62 static const unsigned int mt2701_mtk_ddp_main[] = {
63 DDP_COMPONENT_OVL0,
64 DDP_COMPONENT_RDMA0,
65 DDP_COMPONENT_COLOR0,
66 DDP_COMPONENT_BLS,
67 DDP_COMPONENT_DSI0,
68 };
69
70 static const unsigned int mt2701_mtk_ddp_ext[] = {
71 DDP_COMPONENT_RDMA1,
72 DDP_COMPONENT_DPI0,
73 };
74
75 static const unsigned int mt7623_mtk_ddp_main[] = {
76 DDP_COMPONENT_OVL0,
77 DDP_COMPONENT_RDMA0,
78 DDP_COMPONENT_COLOR0,
79 DDP_COMPONENT_BLS,
80 DDP_COMPONENT_DPI0,
81 };
82
83 static const unsigned int mt7623_mtk_ddp_ext[] = {
84 DDP_COMPONENT_RDMA1,
85 DDP_COMPONENT_DSI0,
86 };
87
88 static const unsigned int mt2712_mtk_ddp_main[] = {
89 DDP_COMPONENT_OVL0,
90 DDP_COMPONENT_COLOR0,
91 DDP_COMPONENT_AAL0,
92 DDP_COMPONENT_OD0,
93 DDP_COMPONENT_RDMA0,
94 DDP_COMPONENT_DPI0,
95 DDP_COMPONENT_PWM0,
96 };
97
98 static const unsigned int mt2712_mtk_ddp_ext[] = {
99 DDP_COMPONENT_OVL1,
100 DDP_COMPONENT_COLOR1,
101 DDP_COMPONENT_AAL1,
102 DDP_COMPONENT_OD1,
103 DDP_COMPONENT_RDMA1,
104 DDP_COMPONENT_DPI1,
105 DDP_COMPONENT_PWM1,
106 };
107
108 static const unsigned int mt2712_mtk_ddp_third[] = {
109 DDP_COMPONENT_RDMA2,
110 DDP_COMPONENT_DSI3,
111 DDP_COMPONENT_PWM2,
112 };
113
114 static unsigned int mt8167_mtk_ddp_main[] = {
115 DDP_COMPONENT_OVL0,
116 DDP_COMPONENT_COLOR0,
117 DDP_COMPONENT_CCORR,
118 DDP_COMPONENT_AAL0,
119 DDP_COMPONENT_GAMMA,
120 DDP_COMPONENT_DITHER0,
121 DDP_COMPONENT_RDMA0,
122 DDP_COMPONENT_DSI0,
123 };
124
125 static const unsigned int mt8173_mtk_ddp_main[] = {
126 DDP_COMPONENT_OVL0,
127 DDP_COMPONENT_COLOR0,
128 DDP_COMPONENT_AAL0,
129 DDP_COMPONENT_OD0,
130 DDP_COMPONENT_RDMA0,
131 DDP_COMPONENT_UFOE,
132 DDP_COMPONENT_DSI0,
133 DDP_COMPONENT_PWM0,
134 };
135
136 static const unsigned int mt8173_mtk_ddp_ext[] = {
137 DDP_COMPONENT_OVL1,
138 DDP_COMPONENT_COLOR1,
139 DDP_COMPONENT_GAMMA,
140 DDP_COMPONENT_RDMA1,
141 DDP_COMPONENT_DPI0,
142 };
143
144 static const unsigned int mt8183_mtk_ddp_main[] = {
145 DDP_COMPONENT_OVL0,
146 DDP_COMPONENT_OVL_2L0,
147 DDP_COMPONENT_RDMA0,
148 DDP_COMPONENT_COLOR0,
149 DDP_COMPONENT_CCORR,
150 DDP_COMPONENT_AAL0,
151 DDP_COMPONENT_GAMMA,
152 DDP_COMPONENT_DITHER0,
153 DDP_COMPONENT_DSI0,
154 };
155
156 static const unsigned int mt8183_mtk_ddp_ext[] = {
157 DDP_COMPONENT_OVL_2L1,
158 DDP_COMPONENT_RDMA1,
159 DDP_COMPONENT_DPI0,
160 };
161
162 static const unsigned int mt8186_mtk_ddp_main[] = {
163 DDP_COMPONENT_OVL0,
164 DDP_COMPONENT_RDMA0,
165 DDP_COMPONENT_COLOR0,
166 DDP_COMPONENT_CCORR,
167 DDP_COMPONENT_AAL0,
168 DDP_COMPONENT_GAMMA,
169 DDP_COMPONENT_POSTMASK0,
170 DDP_COMPONENT_DITHER0,
171 DDP_COMPONENT_DSI0,
172 };
173
174 static const unsigned int mt8186_mtk_ddp_ext[] = {
175 DDP_COMPONENT_OVL_2L0,
176 DDP_COMPONENT_RDMA1,
177 DDP_COMPONENT_DPI0,
178 };
179
180 static const unsigned int mt8188_mtk_ddp_main[] = {
181 DDP_COMPONENT_OVL0,
182 DDP_COMPONENT_RDMA0,
183 DDP_COMPONENT_COLOR0,
184 DDP_COMPONENT_CCORR,
185 DDP_COMPONENT_AAL0,
186 DDP_COMPONENT_GAMMA,
187 DDP_COMPONENT_POSTMASK0,
188 DDP_COMPONENT_DITHER0,
189 };
190
191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
192 {0, DDP_COMPONENT_DP_INTF0},
193 {0, DDP_COMPONENT_DSI0},
194 };
195
196 static const unsigned int mt8192_mtk_ddp_main[] = {
197 DDP_COMPONENT_OVL0,
198 DDP_COMPONENT_OVL_2L0,
199 DDP_COMPONENT_RDMA0,
200 DDP_COMPONENT_COLOR0,
201 DDP_COMPONENT_CCORR,
202 DDP_COMPONENT_AAL0,
203 DDP_COMPONENT_GAMMA,
204 DDP_COMPONENT_POSTMASK0,
205 DDP_COMPONENT_DITHER0,
206 DDP_COMPONENT_DSI0,
207 };
208
209 static const unsigned int mt8192_mtk_ddp_ext[] = {
210 DDP_COMPONENT_OVL_2L2,
211 DDP_COMPONENT_RDMA4,
212 DDP_COMPONENT_DPI0,
213 };
214
215 static const unsigned int mt8195_mtk_ddp_main[] = {
216 DDP_COMPONENT_OVL0,
217 DDP_COMPONENT_RDMA0,
218 DDP_COMPONENT_COLOR0,
219 DDP_COMPONENT_CCORR,
220 DDP_COMPONENT_AAL0,
221 DDP_COMPONENT_GAMMA,
222 DDP_COMPONENT_DITHER0,
223 DDP_COMPONENT_DSC0,
224 DDP_COMPONENT_MERGE0,
225 DDP_COMPONENT_DP_INTF0,
226 };
227
228 static const unsigned int mt8195_mtk_ddp_ext[] = {
229 DDP_COMPONENT_DRM_OVL_ADAPTOR,
230 DDP_COMPONENT_MERGE5,
231 DDP_COMPONENT_DP_INTF1,
232 };
233
234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
235 .main_path = mt2701_mtk_ddp_main,
236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
237 .ext_path = mt2701_mtk_ddp_ext,
238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
239 .shadow_register = true,
240 .mmsys_dev_num = 1,
241 };
242
243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
244 .main_path = mt7623_mtk_ddp_main,
245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
246 .ext_path = mt7623_mtk_ddp_ext,
247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
248 .shadow_register = true,
249 .mmsys_dev_num = 1,
250 };
251
252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
253 .main_path = mt2712_mtk_ddp_main,
254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
255 .ext_path = mt2712_mtk_ddp_ext,
256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
257 .third_path = mt2712_mtk_ddp_third,
258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
259 .mmsys_dev_num = 1,
260 };
261
262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
263 .main_path = mt8167_mtk_ddp_main,
264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
265 .mmsys_dev_num = 1,
266 };
267
268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
269 .main_path = mt8173_mtk_ddp_main,
270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
271 .ext_path = mt8173_mtk_ddp_ext,
272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
273 .mmsys_dev_num = 1,
274 };
275
276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
277 .main_path = mt8183_mtk_ddp_main,
278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
279 .ext_path = mt8183_mtk_ddp_ext,
280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
281 .mmsys_dev_num = 1,
282 };
283
284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
285 .main_path = mt8186_mtk_ddp_main,
286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
287 .ext_path = mt8186_mtk_ddp_ext,
288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
289 .mmsys_dev_num = 1,
290 };
291
292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
293 .main_path = mt8188_mtk_ddp_main,
294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
295 .conn_routes = mt8188_mtk_ddp_main_routes,
296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
297 .mmsys_dev_num = 2,
298 .max_width = 8191,
299 .min_width = 1,
300 .min_height = 1,
301 };
302
303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
304 .main_path = mt8192_mtk_ddp_main,
305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
306 .ext_path = mt8192_mtk_ddp_ext,
307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
308 .mmsys_dev_num = 1,
309 };
310
311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
312 .main_path = mt8195_mtk_ddp_main,
313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
314 .mmsys_dev_num = 2,
315 .max_width = 8191,
316 .min_width = 1,
317 .min_height = 1,
318 };
319
320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
321 .ext_path = mt8195_mtk_ddp_ext,
322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
323 .mmsys_id = 1,
324 .mmsys_dev_num = 2,
325 .max_width = 8191,
326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
327 .min_height = 1,
328 };
329
330 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
331 .mmsys_dev_num = 1,
332 };
333
334 static const struct of_device_id mtk_drm_of_ids[] = {
335 { .compatible = "mediatek,mt2701-mmsys",
336 .data = &mt2701_mmsys_driver_data},
337 { .compatible = "mediatek,mt7623-mmsys",
338 .data = &mt7623_mmsys_driver_data},
339 { .compatible = "mediatek,mt2712-mmsys",
340 .data = &mt2712_mmsys_driver_data},
341 { .compatible = "mediatek,mt8167-mmsys",
342 .data = &mt8167_mmsys_driver_data},
343 { .compatible = "mediatek,mt8173-mmsys",
344 .data = &mt8173_mmsys_driver_data},
345 { .compatible = "mediatek,mt8183-mmsys",
346 .data = &mt8183_mmsys_driver_data},
347 { .compatible = "mediatek,mt8186-mmsys",
348 .data = &mt8186_mmsys_driver_data},
349 { .compatible = "mediatek,mt8188-vdosys0",
350 .data = &mt8188_vdosys0_driver_data},
351 { .compatible = "mediatek,mt8188-vdosys1",
352 .data = &mt8195_vdosys1_driver_data},
353 { .compatible = "mediatek,mt8192-mmsys",
354 .data = &mt8192_mmsys_driver_data},
355 { .compatible = "mediatek,mt8195-mmsys",
356 .data = &mt8195_vdosys0_driver_data},
357 { .compatible = "mediatek,mt8195-vdosys0",
358 .data = &mt8195_vdosys0_driver_data},
359 { .compatible = "mediatek,mt8195-vdosys1",
360 .data = &mt8195_vdosys1_driver_data},
361 { .compatible = "mediatek,mt8365-mmsys",
362 .data = &mt8365_mmsys_driver_data},
363 { }
364 };
365 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
366
mtk_drm_match(struct device * dev,const void * data)367 static int mtk_drm_match(struct device *dev, const void *data)
368 {
369 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
370 return true;
371 return false;
372 }
373
mtk_drm_get_all_drm_priv(struct device * dev)374 static bool mtk_drm_get_all_drm_priv(struct device *dev)
375 {
376 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
377 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
378 struct mtk_drm_private *temp_drm_priv;
379 struct device_node *phandle = dev->parent->of_node;
380 const struct of_device_id *of_id;
381 struct device_node *node;
382 struct device *drm_dev;
383 unsigned int cnt = 0;
384 int i, j;
385
386 for_each_child_of_node(phandle->parent, node) {
387 struct platform_device *pdev;
388
389 of_id = of_match_node(mtk_drm_of_ids, node);
390 if (!of_id)
391 continue;
392
393 pdev = of_find_device_by_node(node);
394 if (!pdev)
395 continue;
396
397 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
398 put_device(&pdev->dev);
399 if (!drm_dev)
400 continue;
401
402 temp_drm_priv = dev_get_drvdata(drm_dev);
403 put_device(drm_dev);
404 if (!temp_drm_priv)
405 continue;
406
407 if (temp_drm_priv->data->main_len)
408 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
409 else if (temp_drm_priv->data->ext_len)
410 all_drm_priv[CRTC_EXT] = temp_drm_priv;
411 else if (temp_drm_priv->data->third_len)
412 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
413
414 if (temp_drm_priv->mtk_drm_bound)
415 cnt++;
416
417 if (cnt == MAX_CRTC) {
418 of_node_put(node);
419 break;
420 }
421 }
422
423 if (drm_priv->data->mmsys_dev_num == cnt) {
424 for (i = 0; i < cnt; i++)
425 for (j = 0; j < cnt; j++)
426 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
427
428 return true;
429 }
430
431 return false;
432 }
433
mtk_drm_find_mmsys_comp(struct mtk_drm_private * private,int comp_id)434 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
435 {
436 const struct mtk_mmsys_driver_data *drv_data = private->data;
437 int i;
438
439 if (drv_data->main_path)
440 for (i = 0; i < drv_data->main_len; i++)
441 if (drv_data->main_path[i] == comp_id)
442 return true;
443
444 if (drv_data->ext_path)
445 for (i = 0; i < drv_data->ext_len; i++)
446 if (drv_data->ext_path[i] == comp_id)
447 return true;
448
449 if (drv_data->third_path)
450 for (i = 0; i < drv_data->third_len; i++)
451 if (drv_data->third_path[i] == comp_id)
452 return true;
453
454 if (drv_data->num_conn_routes)
455 for (i = 0; i < drv_data->num_conn_routes; i++)
456 if (drv_data->conn_routes[i].route_ddp == comp_id)
457 return true;
458
459 return false;
460 }
461
mtk_drm_kms_init(struct drm_device * drm)462 static int mtk_drm_kms_init(struct drm_device *drm)
463 {
464 struct mtk_drm_private *private = drm->dev_private;
465 struct mtk_drm_private *priv_n;
466 struct device *dma_dev = NULL;
467 struct drm_crtc *crtc;
468 int ret, i, j;
469
470 if (drm_firmware_drivers_only())
471 return -ENODEV;
472
473 ret = drmm_mode_config_init(drm);
474 if (ret)
475 return ret;
476
477 drm->mode_config.min_width = 64;
478 drm->mode_config.min_height = 64;
479
480 /*
481 * set max width and height as default value(4096x4096).
482 * this value would be used to check framebuffer size limitation
483 * at drm_mode_addfb().
484 */
485 drm->mode_config.max_width = 4096;
486 drm->mode_config.max_height = 4096;
487 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
488 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
489
490 for (i = 0; i < private->data->mmsys_dev_num; i++) {
491 drm->dev_private = private->all_drm_private[i];
492 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
493 if (ret) {
494 while (--i >= 0)
495 component_unbind_all(private->all_drm_private[i]->dev, drm);
496 return ret;
497 }
498 }
499
500 /*
501 * Ensure internal panels are at the top of the connector list before
502 * crtc creation.
503 */
504 drm_helper_move_panel_connectors_to_head(drm);
505
506 /*
507 * 1. We currently support two fixed data streams, each optional,
508 * and each statically assigned to a crtc:
509 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
510 * 2. For multi mmsys architecture, crtc path data are located in
511 * different drm private data structures. Loop through crtc index to
512 * create crtc from the main path and then ext_path and finally the
513 * third path.
514 */
515 for (i = 0; i < MAX_CRTC; i++) {
516 for (j = 0; j < private->data->mmsys_dev_num; j++) {
517 priv_n = private->all_drm_private[j];
518
519 if (priv_n->data->max_width)
520 drm->mode_config.max_width = priv_n->data->max_width;
521
522 if (priv_n->data->min_width)
523 drm->mode_config.min_width = priv_n->data->min_width;
524
525 if (priv_n->data->min_height)
526 drm->mode_config.min_height = priv_n->data->min_height;
527
528 if (i == CRTC_MAIN && priv_n->data->main_len) {
529 ret = mtk_crtc_create(drm, priv_n->data->main_path,
530 priv_n->data->main_len, j,
531 priv_n->data->conn_routes,
532 priv_n->data->num_conn_routes);
533 if (ret)
534 goto err_component_unbind;
535
536 continue;
537 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
538 ret = mtk_crtc_create(drm, priv_n->data->ext_path,
539 priv_n->data->ext_len, j, NULL, 0);
540 if (ret)
541 goto err_component_unbind;
542
543 continue;
544 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
545 ret = mtk_crtc_create(drm, priv_n->data->third_path,
546 priv_n->data->third_len, j, NULL, 0);
547 if (ret)
548 goto err_component_unbind;
549
550 continue;
551 }
552 }
553 }
554
555 /* IGT will check if the cursor size is configured */
556 drm->mode_config.cursor_width = 512;
557 drm->mode_config.cursor_height = 512;
558
559 /* Use OVL device for all DMA memory allocations */
560 crtc = drm_crtc_from_index(drm, 0);
561 if (crtc)
562 dma_dev = mtk_crtc_dma_dev_get(crtc);
563 if (!dma_dev) {
564 ret = -ENODEV;
565 dev_err(drm->dev, "Need at least one OVL device\n");
566 goto err_component_unbind;
567 }
568
569 drm_dev_set_dma_dev(drm, dma_dev);
570
571 /*
572 * Configure the DMA segment size to make sure we get contiguous IOVA
573 * when importing PRIME buffers.
574 */
575 dma_set_max_seg_size(dma_dev, UINT_MAX);
576
577 ret = drm_vblank_init(drm, MAX_CRTC);
578 if (ret < 0)
579 goto err_component_unbind;
580
581 drm_kms_helper_poll_init(drm);
582 drm_mode_config_reset(drm);
583
584 return 0;
585
586 err_component_unbind:
587 for (i = 0; i < private->data->mmsys_dev_num; i++)
588 component_unbind_all(private->all_drm_private[i]->dev, drm);
589
590 return ret;
591 }
592
mtk_drm_kms_deinit(struct drm_device * drm)593 static void mtk_drm_kms_deinit(struct drm_device *drm)
594 {
595 drm_kms_helper_poll_fini(drm);
596 drm_atomic_helper_shutdown(drm);
597
598 component_unbind_all(drm->dev, drm);
599 }
600
601 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
602
603 static const struct drm_driver mtk_drm_driver = {
604 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
605
606 DRM_GEM_DMA_DRIVER_OPS,
607 DRM_FBDEV_DMA_DRIVER_OPS,
608
609 .fops = &mtk_drm_fops,
610
611 .name = DRIVER_NAME,
612 .desc = DRIVER_DESC,
613 .major = DRIVER_MAJOR,
614 .minor = DRIVER_MINOR,
615 };
616
compare_dev(struct device * dev,void * data)617 static int compare_dev(struct device *dev, void *data)
618 {
619 return dev == (struct device *)data;
620 }
621
mtk_drm_bind(struct device * dev)622 static int mtk_drm_bind(struct device *dev)
623 {
624 struct mtk_drm_private *private = dev_get_drvdata(dev);
625 struct platform_device *pdev;
626 struct drm_device *drm;
627 int ret, i;
628
629 pdev = of_find_device_by_node(private->mutex_node);
630 if (!pdev) {
631 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
632 private->mutex_node);
633 of_node_put(private->mutex_node);
634 return -EPROBE_DEFER;
635 }
636
637 private->mutex_dev = &pdev->dev;
638 private->mtk_drm_bound = true;
639 private->dev = dev;
640
641 if (!mtk_drm_get_all_drm_priv(dev)) {
642 put_device(private->mutex_dev);
643 return 0;
644 }
645
646 drm = drm_dev_alloc(&mtk_drm_driver, dev);
647 if (IS_ERR(drm)) {
648 ret = PTR_ERR(drm);
649 goto err_put_dev;
650 }
651
652 private->drm_master = true;
653 drm->dev_private = private;
654 for (i = 0; i < private->data->mmsys_dev_num; i++)
655 private->all_drm_private[i]->drm = drm;
656
657 ret = mtk_drm_kms_init(drm);
658 if (ret < 0)
659 goto err_free;
660
661 ret = aperture_remove_all_conflicting_devices(DRIVER_NAME);
662 if (ret < 0)
663 dev_err(dev, "Error %d while removing conflicting aperture devices", ret);
664
665 ret = drm_dev_register(drm, 0);
666 if (ret < 0)
667 goto err_deinit;
668
669 drm_client_setup(drm, NULL);
670
671 return 0;
672
673 err_deinit:
674 mtk_drm_kms_deinit(drm);
675 err_free:
676 private->drm = NULL;
677 drm_dev_put(drm);
678 for (i = 0; i < private->data->mmsys_dev_num; i++)
679 private->all_drm_private[i]->drm = NULL;
680 err_put_dev:
681 put_device(private->mutex_dev);
682 return ret;
683 }
684
mtk_drm_unbind(struct device * dev)685 static void mtk_drm_unbind(struct device *dev)
686 {
687 struct mtk_drm_private *private = dev_get_drvdata(dev);
688
689 /* for multi mmsys dev, unregister drm dev in mmsys master */
690 if (private->drm_master) {
691 drm_dev_unregister(private->drm);
692 mtk_drm_kms_deinit(private->drm);
693 drm_dev_put(private->drm);
694 put_device(private->mutex_dev);
695 }
696 private->mtk_drm_bound = false;
697 private->drm_master = false;
698 private->drm = NULL;
699 }
700
701 static const struct component_master_ops mtk_drm_ops = {
702 .bind = mtk_drm_bind,
703 .unbind = mtk_drm_unbind,
704 };
705
706 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
707 { .compatible = "mediatek,mt8167-disp-aal",
708 .data = (void *)MTK_DISP_AAL},
709 { .compatible = "mediatek,mt8173-disp-aal",
710 .data = (void *)MTK_DISP_AAL},
711 { .compatible = "mediatek,mt8183-disp-aal",
712 .data = (void *)MTK_DISP_AAL},
713 { .compatible = "mediatek,mt8192-disp-aal",
714 .data = (void *)MTK_DISP_AAL},
715 { .compatible = "mediatek,mt8167-disp-ccorr",
716 .data = (void *)MTK_DISP_CCORR },
717 { .compatible = "mediatek,mt8183-disp-ccorr",
718 .data = (void *)MTK_DISP_CCORR },
719 { .compatible = "mediatek,mt8192-disp-ccorr",
720 .data = (void *)MTK_DISP_CCORR },
721 { .compatible = "mediatek,mt2701-disp-color",
722 .data = (void *)MTK_DISP_COLOR },
723 { .compatible = "mediatek,mt8167-disp-color",
724 .data = (void *)MTK_DISP_COLOR },
725 { .compatible = "mediatek,mt8173-disp-color",
726 .data = (void *)MTK_DISP_COLOR },
727 { .compatible = "mediatek,mt8167-disp-dither",
728 .data = (void *)MTK_DISP_DITHER },
729 { .compatible = "mediatek,mt8183-disp-dither",
730 .data = (void *)MTK_DISP_DITHER },
731 { .compatible = "mediatek,mt8195-disp-dsc",
732 .data = (void *)MTK_DISP_DSC },
733 { .compatible = "mediatek,mt8167-disp-gamma",
734 .data = (void *)MTK_DISP_GAMMA, },
735 { .compatible = "mediatek,mt8173-disp-gamma",
736 .data = (void *)MTK_DISP_GAMMA, },
737 { .compatible = "mediatek,mt8183-disp-gamma",
738 .data = (void *)MTK_DISP_GAMMA, },
739 { .compatible = "mediatek,mt8195-disp-gamma",
740 .data = (void *)MTK_DISP_GAMMA, },
741 { .compatible = "mediatek,mt8195-disp-merge",
742 .data = (void *)MTK_DISP_MERGE },
743 { .compatible = "mediatek,mt2701-disp-mutex",
744 .data = (void *)MTK_DISP_MUTEX },
745 { .compatible = "mediatek,mt2712-disp-mutex",
746 .data = (void *)MTK_DISP_MUTEX },
747 { .compatible = "mediatek,mt8167-disp-mutex",
748 .data = (void *)MTK_DISP_MUTEX },
749 { .compatible = "mediatek,mt8173-disp-mutex",
750 .data = (void *)MTK_DISP_MUTEX },
751 { .compatible = "mediatek,mt8183-disp-mutex",
752 .data = (void *)MTK_DISP_MUTEX },
753 { .compatible = "mediatek,mt8186-disp-mutex",
754 .data = (void *)MTK_DISP_MUTEX },
755 { .compatible = "mediatek,mt8188-disp-mutex",
756 .data = (void *)MTK_DISP_MUTEX },
757 { .compatible = "mediatek,mt8192-disp-mutex",
758 .data = (void *)MTK_DISP_MUTEX },
759 { .compatible = "mediatek,mt8195-disp-mutex",
760 .data = (void *)MTK_DISP_MUTEX },
761 { .compatible = "mediatek,mt8365-disp-mutex",
762 .data = (void *)MTK_DISP_MUTEX },
763 { .compatible = "mediatek,mt8173-disp-od",
764 .data = (void *)MTK_DISP_OD },
765 { .compatible = "mediatek,mt2701-disp-ovl",
766 .data = (void *)MTK_DISP_OVL },
767 { .compatible = "mediatek,mt8167-disp-ovl",
768 .data = (void *)MTK_DISP_OVL },
769 { .compatible = "mediatek,mt8173-disp-ovl",
770 .data = (void *)MTK_DISP_OVL },
771 { .compatible = "mediatek,mt8183-disp-ovl",
772 .data = (void *)MTK_DISP_OVL },
773 { .compatible = "mediatek,mt8192-disp-ovl",
774 .data = (void *)MTK_DISP_OVL },
775 { .compatible = "mediatek,mt8195-disp-ovl",
776 .data = (void *)MTK_DISP_OVL },
777 { .compatible = "mediatek,mt8183-disp-ovl-2l",
778 .data = (void *)MTK_DISP_OVL_2L },
779 { .compatible = "mediatek,mt8192-disp-ovl-2l",
780 .data = (void *)MTK_DISP_OVL_2L },
781 { .compatible = "mediatek,mt8192-disp-postmask",
782 .data = (void *)MTK_DISP_POSTMASK },
783 { .compatible = "mediatek,mt2701-disp-pwm",
784 .data = (void *)MTK_DISP_BLS },
785 { .compatible = "mediatek,mt8167-disp-pwm",
786 .data = (void *)MTK_DISP_PWM },
787 { .compatible = "mediatek,mt8173-disp-pwm",
788 .data = (void *)MTK_DISP_PWM },
789 { .compatible = "mediatek,mt2701-disp-rdma",
790 .data = (void *)MTK_DISP_RDMA },
791 { .compatible = "mediatek,mt8167-disp-rdma",
792 .data = (void *)MTK_DISP_RDMA },
793 { .compatible = "mediatek,mt8173-disp-rdma",
794 .data = (void *)MTK_DISP_RDMA },
795 { .compatible = "mediatek,mt8183-disp-rdma",
796 .data = (void *)MTK_DISP_RDMA },
797 { .compatible = "mediatek,mt8195-disp-rdma",
798 .data = (void *)MTK_DISP_RDMA },
799 { .compatible = "mediatek,mt8173-disp-ufoe",
800 .data = (void *)MTK_DISP_UFOE },
801 { .compatible = "mediatek,mt8173-disp-wdma",
802 .data = (void *)MTK_DISP_WDMA },
803 { .compatible = "mediatek,mt2701-dpi",
804 .data = (void *)MTK_DPI },
805 { .compatible = "mediatek,mt8167-dsi",
806 .data = (void *)MTK_DSI },
807 { .compatible = "mediatek,mt8173-dpi",
808 .data = (void *)MTK_DPI },
809 { .compatible = "mediatek,mt8183-dpi",
810 .data = (void *)MTK_DPI },
811 { .compatible = "mediatek,mt8186-dpi",
812 .data = (void *)MTK_DPI },
813 { .compatible = "mediatek,mt8188-dp-intf",
814 .data = (void *)MTK_DP_INTF },
815 { .compatible = "mediatek,mt8192-dpi",
816 .data = (void *)MTK_DPI },
817 { .compatible = "mediatek,mt8195-dp-intf",
818 .data = (void *)MTK_DP_INTF },
819 { .compatible = "mediatek,mt8195-dpi",
820 .data = (void *)MTK_DPI },
821 { .compatible = "mediatek,mt2701-dsi",
822 .data = (void *)MTK_DSI },
823 { .compatible = "mediatek,mt8173-dsi",
824 .data = (void *)MTK_DSI },
825 { .compatible = "mediatek,mt8183-dsi",
826 .data = (void *)MTK_DSI },
827 { .compatible = "mediatek,mt8186-dsi",
828 .data = (void *)MTK_DSI },
829 { .compatible = "mediatek,mt8188-dsi",
830 .data = (void *)MTK_DSI },
831 { }
832 };
833
mtk_drm_of_get_ddp_comp_type(struct device_node * node,enum mtk_ddp_comp_type * ctype)834 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype)
835 {
836 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
837
838 if (!of_id)
839 return -EINVAL;
840
841 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data);
842
843 return 0;
844 }
845
mtk_drm_of_get_ddp_ep_cid(struct device_node * node,int output_port,enum mtk_crtc_path crtc_path,struct device_node ** next,unsigned int * cid)846 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
847 int output_port, enum mtk_crtc_path crtc_path,
848 struct device_node **next, unsigned int *cid)
849 {
850 struct device_node *ep_dev_node, *ep_out;
851 enum mtk_ddp_comp_type comp_type;
852 int ret;
853
854 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path);
855 if (!ep_out)
856 return -ENOENT;
857
858 ep_dev_node = of_graph_get_remote_port_parent(ep_out);
859 of_node_put(ep_out);
860 if (!ep_dev_node)
861 return -EINVAL;
862
863 /*
864 * Pass the next node pointer regardless of failures in the later code
865 * so that if this function is called in a loop it will walk through all
866 * of the subsequent endpoints anyway.
867 */
868 *next = ep_dev_node;
869
870 if (!of_device_is_available(ep_dev_node))
871 return -ENODEV;
872
873 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
874 if (ret) {
875 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
876 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR;
877 return 0;
878 }
879 return ret;
880 }
881
882 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type);
883 if (ret < 0)
884 return ret;
885
886 /* All ok! Pass the Component ID to the caller. */
887 *cid = (unsigned int)ret;
888
889 return 0;
890 }
891
892 /**
893 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path
894 * @dev: The mediatek-drm device
895 * @cpath: CRTC Path relative to a VDO or MMSYS
896 * @out_path: Pointer to an array that will contain the new pipeline
897 * @out_path_len: Number of entries in the pipeline array
898 *
899 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending
900 * on the board-specific desired display configuration; this function walks
901 * through all of the output endpoints starting from a VDO or MMSYS hardware
902 * instance and builds the right pipeline as specified in device trees.
903 *
904 * Return:
905 * * %0 - Display HW Pipeline successfully built and validated
906 * * %-ENOENT - Display pipeline was not specified in device tree
907 * * %-EINVAL - Display pipeline built but validation failed
908 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller
909 */
mtk_drm_of_ddp_path_build_one(struct device * dev,enum mtk_crtc_path cpath,const unsigned int ** out_path,unsigned int * out_path_len)910 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath,
911 const unsigned int **out_path,
912 unsigned int *out_path_len)
913 {
914 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
915 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
916 unsigned int *final_ddp_path;
917 unsigned short int idx = 0;
918 bool ovl_adaptor_comp_added = false;
919 int ret;
920
921 /* Get the first entry for the temp_path array */
922 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
923 if (ret) {
924 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
925 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
926 ovl_adaptor_comp_added = true;
927 } else {
928 if (next)
929 dev_err(dev, "Invalid component %pOF\n", next);
930 else
931 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath);
932
933 return ret;
934 }
935 }
936 idx++;
937
938 /*
939 * Walk through port outputs until we reach the last valid mediatek-drm component.
940 * To be valid, this must end with an "invalid" component that is a display node.
941 */
942 do {
943 prev = next;
944 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
945 of_node_put(prev);
946 if (ret) {
947 of_node_put(next);
948 break;
949 }
950
951 /*
952 * If this is an OVL adaptor exclusive component and one of those
953 * was already added, don't add another instance of the generic
954 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether
955 * to probe that component master driver of which only one instance
956 * is needed and possible.
957 */
958 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
959 if (!ovl_adaptor_comp_added)
960 ovl_adaptor_comp_added = true;
961 else
962 idx--;
963 }
964 } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
965
966 /*
967 * The device component might not be enabled: in that case, don't
968 * check the last entry and just report that the device is missing.
969 */
970 if (ret == -ENODEV)
971 return ret;
972
973 /* If the last entry is not a final display output, the configuration is wrong */
974 switch (temp_path[idx - 1]) {
975 case DDP_COMPONENT_DP_INTF0:
976 case DDP_COMPONENT_DP_INTF1:
977 case DDP_COMPONENT_DPI0:
978 case DDP_COMPONENT_DPI1:
979 case DDP_COMPONENT_DSI0:
980 case DDP_COMPONENT_DSI1:
981 case DDP_COMPONENT_DSI2:
982 case DDP_COMPONENT_DSI3:
983 break;
984 default:
985 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
986 temp_path[idx - 1], ret);
987 return -EINVAL;
988 }
989
990 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL);
991 if (!final_ddp_path)
992 return -ENOMEM;
993
994 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx);
995
996 /* Pipeline built! */
997 *out_path = final_ddp_path;
998 *out_path_len = idx;
999
1000 return 0;
1001 }
1002
mtk_drm_of_ddp_path_build(struct device * dev,struct device_node * node,struct mtk_mmsys_driver_data * data)1003 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node,
1004 struct mtk_mmsys_driver_data *data)
1005 {
1006 struct device_node *ep_node;
1007 struct of_endpoint of_ep;
1008 bool output_present[MAX_CRTC] = { false };
1009 int ret;
1010
1011 for_each_endpoint_of_node(node, ep_node) {
1012 ret = of_graph_parse_endpoint(ep_node, &of_ep);
1013 if (ret) {
1014 dev_err_probe(dev, ret, "Cannot parse endpoint\n");
1015 break;
1016 }
1017
1018 if (of_ep.id >= MAX_CRTC) {
1019 ret = dev_err_probe(dev, -EINVAL,
1020 "Invalid endpoint%u number\n", of_ep.port);
1021 break;
1022 }
1023
1024 output_present[of_ep.id] = true;
1025 }
1026
1027 if (ret) {
1028 of_node_put(ep_node);
1029 return ret;
1030 }
1031
1032 if (output_present[CRTC_MAIN]) {
1033 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN,
1034 &data->main_path, &data->main_len);
1035 if (ret && ret != -ENODEV)
1036 return ret;
1037 }
1038
1039 if (output_present[CRTC_EXT]) {
1040 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT,
1041 &data->ext_path, &data->ext_len);
1042 if (ret && ret != -ENODEV)
1043 return ret;
1044 }
1045
1046 if (output_present[CRTC_THIRD]) {
1047 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD,
1048 &data->third_path, &data->third_len);
1049 if (ret && ret != -ENODEV)
1050 return ret;
1051 }
1052
1053 return 0;
1054 }
1055
mtk_drm_probe(struct platform_device * pdev)1056 static int mtk_drm_probe(struct platform_device *pdev)
1057 {
1058 struct device *dev = &pdev->dev;
1059 struct device_node *phandle = dev->parent->of_node;
1060 const struct of_device_id *of_id;
1061 struct mtk_drm_private *private;
1062 struct mtk_mmsys_driver_data *mtk_drm_data;
1063 struct device_node *node;
1064 struct component_match *match = NULL;
1065 struct platform_device *ovl_adaptor = NULL;
1066 int ret;
1067 int i;
1068
1069 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
1070 if (!private)
1071 return -ENOMEM;
1072
1073 private->mmsys_dev = dev->parent;
1074 if (!private->mmsys_dev) {
1075 dev_err(dev, "Failed to get MMSYS device\n");
1076 return -ENODEV;
1077 }
1078
1079 of_id = of_match_node(mtk_drm_of_ids, phandle);
1080 if (!of_id)
1081 return -ENODEV;
1082
1083 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data;
1084 if (!mtk_drm_data)
1085 return -EINVAL;
1086
1087 /* Try to build the display pipeline from devicetree graphs */
1088 if (of_graph_is_present(phandle)) {
1089 dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
1090 mtk_drm_data->mmsys_id);
1091 private->data = devm_kmemdup(dev, mtk_drm_data,
1092 sizeof(*mtk_drm_data), GFP_KERNEL);
1093 if (!private->data)
1094 return -ENOMEM;
1095
1096 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data);
1097 if (ret)
1098 return ret;
1099 } else {
1100 /* No devicetree graphs support: go with hardcoded paths if present */
1101 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
1102 private->data = mtk_drm_data;
1103 }
1104
1105 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
1106 sizeof(*private->all_drm_private),
1107 GFP_KERNEL);
1108 if (!private->all_drm_private)
1109 return -ENOMEM;
1110
1111 /* Bringup ovl_adaptor */
1112 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
1113 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
1114 PLATFORM_DEVID_AUTO,
1115 (void *)private->mmsys_dev,
1116 sizeof(*private->mmsys_dev));
1117 if (IS_ERR(ovl_adaptor))
1118 return PTR_ERR(ovl_adaptor);
1119
1120 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
1121 mtk_ddp_comp_init(dev, NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
1122 DDP_COMPONENT_DRM_OVL_ADAPTOR);
1123 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
1124 }
1125
1126 /* Iterate over sibling DISP function blocks */
1127 for_each_child_of_node(phandle->parent, node) {
1128 enum mtk_ddp_comp_type comp_type;
1129 int comp_id;
1130
1131 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
1132 if (ret)
1133 continue;
1134
1135 if (!of_device_is_available(node)) {
1136 dev_dbg(dev, "Skipping disabled component %pOF\n",
1137 node);
1138 continue;
1139 }
1140
1141 if (comp_type == MTK_DISP_MUTEX) {
1142 int id;
1143
1144 id = of_alias_get_id(node, "mutex");
1145 if (id < 0 || id == private->data->mmsys_id) {
1146 private->mutex_node = of_node_get(node);
1147 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
1148 }
1149 continue;
1150 }
1151
1152 comp_id = mtk_ddp_comp_get_id(node, comp_type);
1153 if (comp_id < 0) {
1154 dev_warn(dev, "Skipping unknown component %pOF\n",
1155 node);
1156 continue;
1157 }
1158
1159 if (!mtk_drm_find_mmsys_comp(private, comp_id))
1160 continue;
1161
1162 private->comp_node[comp_id] = of_node_get(node);
1163
1164 /*
1165 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
1166 * blocks have separate component platform drivers and initialize their own
1167 * DDP component structure. The others are initialized here.
1168 */
1169 if (comp_type == MTK_DISP_AAL ||
1170 comp_type == MTK_DISP_CCORR ||
1171 comp_type == MTK_DISP_COLOR ||
1172 comp_type == MTK_DISP_GAMMA ||
1173 comp_type == MTK_DISP_MERGE ||
1174 comp_type == MTK_DISP_OVL ||
1175 comp_type == MTK_DISP_OVL_2L ||
1176 comp_type == MTK_DISP_OVL_ADAPTOR ||
1177 comp_type == MTK_DISP_RDMA ||
1178 comp_type == MTK_DP_INTF ||
1179 comp_type == MTK_DPI ||
1180 comp_type == MTK_DSI) {
1181 dev_info(dev, "Adding component match for %pOF\n",
1182 node);
1183 drm_of_component_match_add(dev, &match, component_compare_of,
1184 node);
1185 }
1186
1187 ret = mtk_ddp_comp_init(dev, node, &private->ddp_comp[comp_id], comp_id);
1188 if (ret) {
1189 of_node_put(node);
1190 goto err_node;
1191 }
1192 }
1193
1194 if (!private->mutex_node) {
1195 dev_err(dev, "Failed to find disp-mutex node\n");
1196 ret = -ENODEV;
1197 goto err_node;
1198 }
1199
1200 pm_runtime_enable(dev);
1201
1202 platform_set_drvdata(pdev, private);
1203
1204 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
1205 if (ret)
1206 goto err_pm;
1207
1208 return 0;
1209
1210 err_pm:
1211 pm_runtime_disable(dev);
1212 err_node:
1213 if (ovl_adaptor)
1214 platform_device_unregister(ovl_adaptor);
1215 of_node_put(private->mutex_node);
1216 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1217 of_node_put(private->comp_node[i]);
1218 return ret;
1219 }
1220
mtk_drm_remove(struct platform_device * pdev)1221 static void mtk_drm_remove(struct platform_device *pdev)
1222 {
1223 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1224 struct device *ovl_adaptor_dev;
1225 int i;
1226
1227 ovl_adaptor_dev =
1228 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev;
1229
1230 component_master_del(&pdev->dev, &mtk_drm_ops);
1231 if (ovl_adaptor_dev)
1232 platform_device_unregister(to_platform_device(ovl_adaptor_dev));
1233 pm_runtime_disable(&pdev->dev);
1234 of_node_put(private->mutex_node);
1235 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1236 of_node_put(private->comp_node[i]);
1237 }
1238
mtk_drm_shutdown(struct platform_device * pdev)1239 static void mtk_drm_shutdown(struct platform_device *pdev)
1240 {
1241 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1242
1243 drm_atomic_helper_shutdown(private->drm);
1244 }
1245
mtk_drm_sys_prepare(struct device * dev)1246 static int mtk_drm_sys_prepare(struct device *dev)
1247 {
1248 struct mtk_drm_private *private = dev_get_drvdata(dev);
1249 struct drm_device *drm = private->drm;
1250
1251 if (private->drm_master)
1252 return drm_mode_config_helper_suspend(drm);
1253 else
1254 return 0;
1255 }
1256
mtk_drm_sys_complete(struct device * dev)1257 static void mtk_drm_sys_complete(struct device *dev)
1258 {
1259 struct mtk_drm_private *private = dev_get_drvdata(dev);
1260 struct drm_device *drm = private->drm;
1261 int ret = 0;
1262
1263 if (private->drm_master)
1264 ret = drm_mode_config_helper_resume(drm);
1265 if (ret)
1266 dev_err(dev, "Failed to resume\n");
1267 }
1268
1269 static const struct dev_pm_ops mtk_drm_pm_ops = {
1270 .prepare = mtk_drm_sys_prepare,
1271 .complete = mtk_drm_sys_complete,
1272 };
1273
1274 static struct platform_driver mtk_drm_platform_driver = {
1275 .probe = mtk_drm_probe,
1276 .remove = mtk_drm_remove,
1277 .shutdown = mtk_drm_shutdown,
1278 .driver = {
1279 .name = "mediatek-drm",
1280 .pm = &mtk_drm_pm_ops,
1281 },
1282 };
1283
1284 static struct platform_driver * const mtk_drm_drivers[] = {
1285 &mtk_disp_aal_driver,
1286 &mtk_disp_ccorr_driver,
1287 &mtk_disp_color_driver,
1288 &mtk_disp_gamma_driver,
1289 &mtk_disp_merge_driver,
1290 &mtk_disp_ovl_adaptor_driver,
1291 &mtk_disp_ovl_driver,
1292 &mtk_disp_rdma_driver,
1293 &mtk_dpi_driver,
1294 &mtk_drm_platform_driver,
1295 &mtk_dsi_driver,
1296 &mtk_ethdr_driver,
1297 &mtk_mdp_rdma_driver,
1298 &mtk_padding_driver,
1299 };
1300
mtk_drm_init(void)1301 static int __init mtk_drm_init(void)
1302 {
1303 return platform_register_drivers(mtk_drm_drivers,
1304 ARRAY_SIZE(mtk_drm_drivers));
1305 }
1306
mtk_drm_exit(void)1307 static void __exit mtk_drm_exit(void)
1308 {
1309 platform_unregister_drivers(mtk_drm_drivers,
1310 ARRAY_SIZE(mtk_drm_drivers));
1311 }
1312
1313 module_init(mtk_drm_init);
1314 module_exit(mtk_drm_exit);
1315
1316 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1317 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1318 MODULE_LICENSE("GPL v2");
1319