1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2023 MediaTek Inc. */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7
8 #include "mt7925.h"
9 #include "mac.h"
10 #include "mcu.h"
11 #include "regd.h"
12 #include "../dma.h"
13
14 static const struct pci_device_id mt7925_pci_device_table[] = {
15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
16 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
18 .driver_data = (kernel_ulong_t)MT7925_FIRMWARE_WM },
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7927),
20 .driver_data = (kernel_ulong_t)MT7927_FIRMWARE_WM },
21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x6639),
22 .driver_data = (kernel_ulong_t)MT7927_FIRMWARE_WM },
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0738),
24 .driver_data = (kernel_ulong_t)MT7927_FIRMWARE_WM },
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7928),
26 .driver_data = (kernel_ulong_t)MT7928_FIRMWARE_WM },
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7935),
28 .driver_data = (kernel_ulong_t)MT7928_FIRMWARE_WM },
29 { },
30 };
31
32 static bool mt7925_disable_aspm;
33 module_param_named(disable_aspm, mt7925_disable_aspm, bool, 0644);
34 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
35
mt7925e_init_reset(struct mt792x_dev * dev)36 static int mt7925e_init_reset(struct mt792x_dev *dev)
37 {
38 return mt792x_wpdma_reset(dev, true);
39 }
40
mt7925e_unregister_device(struct mt792x_dev * dev)41 static void mt7925e_unregister_device(struct mt792x_dev *dev)
42 {
43 int i;
44 struct mt76_connac_pm *pm = &dev->pm;
45 struct ieee80211_hw *hw = mt76_hw(dev);
46
47 if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
48 wiphy_rfkill_stop_polling(hw->wiphy);
49
50 cancel_work_sync(&dev->reset_work);
51 cancel_work_sync(&dev->init_work);
52 mt76_unregister_device(&dev->mt76);
53 mt76_for_each_q_rx(&dev->mt76, i)
54 napi_disable(&dev->mt76.napi[i]);
55 cancel_delayed_work_sync(&pm->ps_work);
56 cancel_delayed_work_sync(&dev->mlo_pm_work);
57 cancel_work_sync(&pm->wake_work);
58
59 mt7925_tx_token_put(dev);
60 __mt792x_mcu_drv_pmctrl(dev);
61 mt792x_dma_cleanup(dev);
62 mt792x_wfsys_reset(dev);
63 skb_queue_purge(&dev->mt76.mcu.res_q);
64
65 tasklet_disable(&dev->mt76.irq_tasklet);
66 }
67
mt7925_reg_remap_restore(struct mt792x_dev * dev)68 static void mt7925_reg_remap_restore(struct mt792x_dev *dev)
69 {
70 /* remap to ori status */
71 if (unlikely(dev->backup_l1)) {
72 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->backup_l1);
73 dev->backup_l1 = 0;
74 }
75
76 if (dev->backup_l2) {
77 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->backup_l2);
78 dev->backup_l2 = 0;
79 }
80 }
81
mt7925_reg_map_l1(struct mt792x_dev * dev,u32 addr)82 static u32 mt7925_reg_map_l1(struct mt792x_dev *dev, u32 addr)
83 {
84 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
85 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
86
87 dev->backup_l1 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
88
89 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
90 MT_HIF_REMAP_L1_MASK,
91 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
92
93 /* use read to push write */
94 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
95
96 return MT_HIF_REMAP_BASE_L1 + offset;
97 }
98
mt7925_reg_map_l2(struct mt792x_dev * dev,u32 addr)99 static u32 mt7925_reg_map_l2(struct mt792x_dev *dev, u32 addr)
100 {
101 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, MT_HIF_REMAP_BASE_L2);
102
103 dev->backup_l2 = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
104
105 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
106 MT_HIF_REMAP_L1_MASK,
107 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
108
109 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, addr);
110 /* use read to push write */
111 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
112
113 return MT_HIF_REMAP_BASE_L1;
114 }
115
__mt7925_reg_addr(struct mt792x_dev * dev,u32 addr)116 static u32 __mt7925_reg_addr(struct mt792x_dev *dev, u32 addr)
117 {
118 static const struct mt76_connac_reg_map default_fixed_map[] = {
119 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */
120 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */
121 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */
122 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */
123 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */
124 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
125 { 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */
126 { 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */
127 { 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */
128 { 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */
129 { 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */
130 { 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
131 { 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
132 { 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
133 { 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
134 { 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
135 { 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
136 { 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */
137 { 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
138 { 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */
139 { 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
140 { 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
141 { 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
142 { 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
143 { 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
144 { 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
145 { 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */
146 { 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */
147 { 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */
148 { 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */
149 { 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
150 { 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
151 { 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
152 { 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
153 { 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
154 { 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
155 { 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
156 { 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
157 { 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
158 { 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
159 { 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
160 { 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
161 { 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
162 { 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */
163 { 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */
164 { 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */
165 { 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */
166 { 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */
167 { 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */
168 { 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */
169 { 0x7c500000, 0x060000, 0x200000 }, /* remap */
170 { 0x0, 0x0, 0x0 } /* End */
171 };
172 /* The remap table was ordered from highest to lowest frequency
173 * to improve lookup efficiency.
174 */
175 static const struct mt76_connac_reg_map mt7928_fixed_map[] = {
176 {0x54000000, 0x002000, 0x01000}, /* WFDMA_0 (PCIE0 MCU DMA0) */
177 {0x55000000, 0x003000, 0x01000}, /* WFDMA_1 (PCIE0 MCU DMA1) */
178 {0x57000000, 0x005000, 0x01000}, /* WFDMA_3 (MCU wrap CR) */
179 {0x58000000, 0x006000, 0x01000}, /* WFDMA_4 (PCIE1 MCU DMA0) */
180 {0x59000000, 0x007000, 0x01000}, /* WFDMA_5 (PCIE1 MCU DMA1) */
181 {0x56000000, 0x004000, 0x01000}, /* WFDMA_2 (Reserved) */
182 {0x820D0000, 0x030000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
183 {0x820C4000, 0x0A8000, 0x04000}, /* WF_LMAC_TOP (WF_UWTBL) */
184 {0x820C0000, 0x008000, 0x04000}, /* WF_UMAC_TOP (PLE) */
185 {0x820C8000, 0x00C000, 0x02000}, /* WF_UMAC_TOP (PSE) */
186 {0x820CC000, 0x00E000, 0x02000}, /* WF_UMAC_TOP (PP) */
187 {0x820F0000, 0x0A0000, 0x00400}, /* WF_LMAC_TOP (WF_CFG) */
188 {0x820F1000, 0x0A0600, 0x00200}, /* WF_LMAC_TOP (WF_TRB) */
189 {0x820F2000, 0x0A0800, 0x00400}, /* WF_LMAC_TOP (WF_AGG) */
190 {0x820F3000, 0x0A0C00, 0x00400}, /* WF_LMAC_TOP (WF_ARB) */
191 {0x820F4000, 0x0A1000, 0x00400}, /* WF_LMAC_TOP (WF_TMAC) */
192 {0x820F5000, 0x0A1400, 0x00800}, /* WF_LMAC_TOP (WF_RMAC) */
193 {0x820F7000, 0x0A1E00, 0x00200}, /* WF_LMAC_TOP (WF_DMA) */
194 {0x820F9000, 0x0A3400, 0x00200}, /* WF_LMAC_TOP (WF_WTBLOFF) */
195 {0x820FA000, 0x0A4000, 0x00200}, /* WF_LMAC_TOP (WF_ETBF) */
196 {0x820FB000, 0x0A4200, 0x00400}, /* WF_LMAC_TOP (WF_LPON) */
197 {0x820FC000, 0x0A4600, 0x00200}, /* WF_LMAC_TOP (WF_INT) */
198 {0x820FD000, 0x0A4800, 0x00800}, /* WF_LMAC_TOP (WF_MIB) */
199 {0x820E0000, 0x020000, 0x00400}, /* WF_LMAC_TOP (WF_CFG) */
200 {0x820E1000, 0x020400, 0x00200}, /* WF_LMAC_TOP (WF_TRB) */
201 {0x820E2000, 0x020800, 0x00400}, /* WF_LMAC_TOP (WF_AGG) */
202 {0x820E3000, 0x020C00, 0x00400}, /* WF_LMAC_TOP (WF_ARB) */
203 {0x820E4000, 0x021000, 0x00400}, /* WF_LMAC_TOP (WF_TMAC) */
204 {0x820E5000, 0x021400, 0x00800}, /* WF_LMAC_TOP (WF_RMAC) */
205 {0x820CE000, 0x021C00, 0x00200}, /* WF_LMAC_TOP (WF_SEC) */
206 {0x820E7000, 0x021E00, 0x00200}, /* WF_LMAC_TOP (WF_DMA) */
207 {0x820CF000, 0x022000, 0x01000}, /* WF_LMAC_TOP (WF_PF) */
208 {0x820E9000, 0x023400, 0x00200}, /* WF_LMAC_TOP (WF_WTBLOFF) */
209 {0x820EA000, 0x024000, 0x00200}, /* WF_LMAC_TOP (WF_ETBF) */
210 {0x820EB000, 0x024200, 0x00400}, /* WF_LMAC_TOP (WF_LPON) */
211 {0x820EC000, 0x024600, 0x00200}, /* WF_LMAC_TOP (WF_INT) */
212 {0x820ED000, 0x024800, 0x00800}, /* WF_LMAC_TOP (WF_MIB) */
213 {0x820CA000, 0x026000, 0x02000}, /* WF_LMAC_TOP (WF_MUCOP) */
214 {0x7C500000, 0x060000, 0x200000}, /* remap */
215 {0x7C000000, 0x0F0000, 0x10000}, /* CONN_INFRA (off2on) */
216 {0x7C060000, 0x0E0000, 0x10000}, /* remap MT_CONN_ON_LPCTL and MT_CONN_ON_MISC */
217 {0x20060000, 0x0E0000, 0x10000}, /* CONN_INFRA conn_host_csr_top */
218 {0x7C010000, 0x100000, 0x10000}, /* CONN_INFRA (gpio clkgen cfg) */
219 {0x7C050000, 0x1A0000, 0x10000}, /* CONN_INFRA SYSRAM */
220 {0x7C080000, 0x190000, 0x10000}, /* CONN_INFRA (coex, pta) */
221 {0x7C070000, 0x180000, 0x10000}, /* CONN_INFRA Semaphore */
222 {0x7C040000, 0x170000, 0x10000}, /* CONN_INFRA (bus, afe) */
223 {0x7C026000, 0x0D6000, 0x0019C}, /* remap DMASHL TOP */
224 {0x20020000, 0x0D0000, 0x0C000}, /* CONN_INFRA wf_dma_host_side_cr */
225 {0x200B0000, 0x050000, 0x10000}, /* CONN_INFRA conn_von_sysram */
226 {0x20090000, 0x150000, 0x08000}, /* CONN_INFRA von_connsys_s0-s7 */
227 {0x7C098000, 0x158000, 0x08000}, /* CONN_INFRA von_connsys_hclk_s0-s7 */
228 {0x20030000, 0x160000, 0x10000}, /* CONN_INFRA CCIF */
229 {0x70000000, 0x1E0000, 0x10000}, /* CONN_INFRA CONN2AP */
230 {0x830C0000, 0x000000, 0x01000}, /* WF_MCU_BUS_CR_REMAP */
231 {0x81020000, 0x0C0000, 0x10000}, /* WF_TOP_MISC_ON */
232 {0x80020000, 0x0B0000, 0x10000}, /* WF_TOP_MISC_OFF */
233 {0x81040000, 0x120000, 0x01000}, /* WF_MCU_CFG_ON */
234 {0x00400000, 0x080000, 0x10000}, /* WF_MCU_SYSRAM */
235 {0x00410000, 0x090000, 0x10000}, /* WF_MCU_SYSRAM (Common driver) */
236 {0x88000000, 0x140000, 0x10000}, /* WF_MCU_CFG_LS */
237 {0x80010000, 0x124000, 0x01000}, /* WF_AXIDMA */
238 {0x81050000, 0x121000, 0x01000}, /* WF_MCU_EINT */
239 {0x81060000, 0x122000, 0x01000}, /* WF_MCU_GPT */
240 {0x81070000, 0x123000, 0x01000}, /* WF_MCU_WDT */
241 {0x830A0000, 0x040000, 0x10000}, /* WF_PHY_MAP0 */
242 {0x83090000, 0x060000, 0x10000}, /* WF_PHY_MAP2 */
243 {0x83000000, 0x110000, 0x10000}, /* WF_PHY_MAP3 */
244 {0x83010000, 0x130000, 0x10000}, /* WF_PHY_MAP4 */
245 {0x81030000, 0x0AE000, 0x00100}, /* WFSYS_AON */
246 {0x81031000, 0x0AE100, 0x00100}, /* WFSYS_AON */
247 {0x81032000, 0x0AE200, 0x00100}, /* WFSYS_AON */
248 {0x81033000, 0x0AE300, 0x00100}, /* WFSYS_AON */
249 {0x81034000, 0x0AE400, 0x00100}, /* WFSYS_AON */
250 {0xE0400000, 0x070000, 0x10000}, /* WF_UMCA_SYSRAM */
251 {0x70010000, 0x1C0000, 0x10000}, /* CB Infra1 */
252 {0x70020000, 0x1F0000, 0x10000}, /* Reserved for CBTOP, can't switch */
253 {0x74040000, 0x1D0000, 0x10000}, /* CB PCIe (cbtop remap) */
254 {0x18010000, 0x100000, 0x10000}, /* remap MT_HW_EMI_CTRL */
255 {0x00000000, 0x000000, 0x00000}, /* END */
256 };
257 const struct mt76_connac_reg_map *fixed_map;
258 size_t array_size;
259 u32 i;
260
261 if (addr < 0x200000)
262 return addr;
263
264 mt7925_reg_remap_restore(dev);
265
266 if (is_mt7928(&dev->mt76)) {
267 fixed_map = mt7928_fixed_map;
268 array_size = ARRAY_SIZE(mt7928_fixed_map);
269 } else {
270 fixed_map = default_fixed_map;
271 array_size = ARRAY_SIZE(default_fixed_map);
272 }
273
274 for (i = 0; i < array_size; i++) {
275 u32 ofs;
276
277 if (addr < fixed_map[i].phys)
278 continue;
279
280 ofs = addr - fixed_map[i].phys;
281 if (ofs > fixed_map[i].size)
282 continue;
283
284 return fixed_map[i].maps + ofs;
285 }
286
287 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
288 (addr >= 0x70000000 && addr < 0x78000000) ||
289 (addr >= 0x7c000000 && addr < 0x7c400000))
290 return mt7925_reg_map_l1(dev, addr);
291
292 return mt7925_reg_map_l2(dev, addr);
293 }
294
mt7925_rr(struct mt76_dev * mdev,u32 offset)295 static u32 mt7925_rr(struct mt76_dev *mdev, u32 offset)
296 {
297 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
298 u32 addr = __mt7925_reg_addr(dev, offset);
299
300 return dev->bus_ops->rr(mdev, addr);
301 }
302
mt7925_wr(struct mt76_dev * mdev,u32 offset,u32 val)303 static void mt7925_wr(struct mt76_dev *mdev, u32 offset, u32 val)
304 {
305 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
306 u32 addr = __mt7925_reg_addr(dev, offset);
307
308 dev->bus_ops->wr(mdev, addr, val);
309 }
310
mt7925_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)311 static u32 mt7925_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
312 {
313 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
314 u32 addr = __mt7925_reg_addr(dev, offset);
315
316 return dev->bus_ops->rmw(mdev, addr, mask, val);
317 }
318
319 static const struct mt792x_dma_layout mt7925_dma_layout = {
320 .tx_data0 = mt792x_dma_ring(MT7925_TXQ_BAND0,
321 MT7925_TX_RING_SIZE,
322 MT_TX_RING_BASE),
323 .tx_mcu = mt792x_dma_ring(MT7925_TXQ_MCU_WM,
324 MT7925_TX_MCU_RING_SIZE,
325 MT_TX_RING_BASE),
326 .tx_fwdl = mt792x_dma_ring(MT7925_TXQ_FWDL,
327 MT7925_TX_FWDL_RING_SIZE,
328 MT_TX_RING_BASE),
329 .rx_mcu = mt792x_dma_ring(MT7925_RXQ_MCU_WM,
330 MT7925_RX_MCU_RING_SIZE,
331 MT_RX_EVENT_RING_BASE),
332 .rx_data = mt792x_dma_ring(MT7925_RXQ_BAND0,
333 MT7925_RX_RING_SIZE,
334 MT_RX_DATA_RING_BASE),
335 };
336
337 static const struct mt792x_dma_layout mt7927_dma_layout = {
338 .tx_data0 = mt792x_dma_ring(MT7927_TXQ_BAND0,
339 MT7925_TX_RING_SIZE,
340 MT_TX_RING_BASE),
341 .tx_mcu = mt792x_dma_ring(MT7927_TXQ_MCU_WM,
342 MT7925_TX_MCU_RING_SIZE,
343 MT_TX_RING_BASE),
344 .tx_fwdl = mt792x_dma_ring(MT7927_TXQ_FWDL,
345 MT7925_TX_FWDL_RING_SIZE,
346 MT_TX_RING_BASE),
347 .rx_mcu = mt792x_dma_ring(MT7927_RXQ_MCU_WM,
348 MT7925_RX_MCU_RING_SIZE,
349 MT_RX_EVENT_RING_BASE),
350 .rx_data = mt792x_dma_ring(MT7927_RXQ_BAND0,
351 MT7925_RX_RING_SIZE,
352 MT_RX_DATA_RING_BASE),
353 };
354
355 static const struct mt792x_dma_layout mt7928_dma_layout = {
356 .tx_data0 = mt792x_dma_ring(MT7925_TXQ_BAND0,
357 MT7925_TX_RING_SIZE,
358 MT_TX_RING_BASE),
359 .tx_mcu = mt792x_dma_ring(MT7925_TXQ_MCU_WM,
360 MT7925_TX_MCU_RING_SIZE,
361 MT_TX_RING_BASE),
362 .tx_fwdl = mt792x_dma_ring(MT7925_TXQ_FWDL,
363 MT7925_TX_FWDL_RING_SIZE,
364 MT_TX_RING_BASE),
365 .tx_done = mt792x_dma_ring(MT7928_RXQ_MCU_WM2,
366 MT7928_RX_MCU_WA_RING_SIZE,
367 MT_RX_EVENT_RING_BASE),
368 .rx_mcu = mt792x_dma_ring(MT7928_RXQ_MCU_WM,
369 MT7925_RX_MCU_RING_SIZE,
370 MT_RX_EVENT_RING_BASE),
371 .rx_data = mt792x_dma_ring(MT7928_RXQ_BAND0,
372 MT7925_RX_RING_SIZE,
373 MT_RX_DATA_RING_BASE),
374 };
375
mt7927_dma_init(struct mt792x_dev * dev)376 static int mt7927_dma_init(struct mt792x_dev *dev)
377 {
378 int ret;
379
380 ret = mt792x_dma_alloc_queues(dev, &mt7927_dma_layout);
381 if (ret)
382 return ret;
383
384 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
385 MT7927_RXQ_DATA2,
386 MT7925_RX_MCU_RING_SIZE,
387 MT_RX_BUF_SIZE,
388 MT_RX_DATA_RING_BASE);
389 if (ret)
390 return ret;
391
392 ret = mt76_init_queues(dev, mt792x_poll_rx);
393 if (ret < 0)
394 return ret;
395
396 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
397 mt792x_poll_tx);
398 napi_enable(&dev->mt76.tx_napi);
399
400 return mt792x_dma_enable(dev);
401 }
402
mt7928_dma_shdl_lite_init(struct mt792x_dev * dev)403 static void mt7928_dma_shdl_lite_init(struct mt792x_dev *dev)
404 {
405 u32 addr, idx, grp1_5_quota, grp15_quota;
406 u32 q2group[8] = {
407 0x04000000, /* AC00->G0,..., AC03->G4 */
408 0x04010101, /* AC10->G1,..., AC13->G4 */
409 0x04020202, /* AC20->G2,..., AC23->G4 */
410 0x04030303, /* AC30->G3,..., AC33->G4 */
411 0x00000005, /* ALTX->G5,BMC->G0,BCN->G0 */
412 0x00000005, /* TGID=1 ALTX->G5 */
413 0x00000000, /* NAF/NBCN/FIXFID -> G0 */
414 0x00000005, /* TGID=2 ALTX->G5 */
415 };
416
417 /* RST */
418 mt76_wr(dev, MT_DMASHDL_LITE_MAIN_CONTROL, MT_DMASHDL_LITE_MAIN_CONTROL_SW_RST);
419 /* pse page size 0x10, ple page size 0x7e0 */
420 mt76_wr(dev, MT_DMASHDL_LITE_PAGE_SIZE,
421 FIELD_PREP(MT_DMASHDL_LITE_PSE_PAGE_SIZE_MASK, 0x10) |
422 FIELD_PREP(MT_DMASHDL_LITE_PLE_PAGE_SIZE_MASK, 0x7e0));
423 /* pse max page 8, ple max page 1 */
424 mt76_wr(dev, MT_DMASHDL_LITE_PKT_MAX_SIZE,
425 FIELD_PREP(MT_DMASHDL_LITE_PSE_PKT_MAX_SIZE_MASK, 8) |
426 FIELD_PREP(MT_DMASHDL_LITE_PLE_PKT_MAX_SIZE_MASK, 1));
427 /* SN/UDF check */
428 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_SN_CHK0, 0xffffffff);
429 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_SN_CHK1, 0xffffffff);
430 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_UDF_CHK0, 0xffffffff);
431 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_UDF_CHK1, 0xffffffff);
432 /* q mapping */
433 for (addr = MT_DMASHDL_LITE_Q_MAPPING0, idx = 0;
434 idx < ARRAY_SIZE(q2group);
435 idx++, addr += 4)
436 mt76_wr(dev, addr, q2group[idx]);
437 /* refill, set 0 to enable group 0,1,2,3,4,5 & 15 */
438 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_DISABLE0, 0xffff7fc0);
439 mt76_wr(dev, MT_DMASHDL_LITE_GROUP_DISABLE1, 0xffffffff);
440 /* max/min quota */
441 grp1_5_quota = FIELD_PREP(MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK, 0x3f0) |
442 FIELD_PREP(MT_DMASHDL_LITE_GROUP_MIN_QUOTA_MASK, 0x10);
443 grp15_quota = FIELD_PREP(MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK, 0x30);
444
445 for (addr = MT_DMASHDL_LITE_GROUP0_QUOTA, idx = 0;
446 idx < DMASHDL_LITE_GROUP_NUM;
447 idx++, addr += 4)
448 mt76_wr(dev, addr, (idx <= 5) ? grp1_5_quota :
449 ((idx == 15) ? grp15_quota : 0));
450 }
451
mt7925_dma_init(struct mt792x_dev * dev)452 static int mt7925_dma_init(struct mt792x_dev *dev)
453 {
454 int ret;
455 const struct mt792x_dma_layout *layout =
456 is_mt7928(&dev->mt76) ? &mt7928_dma_layout : &mt7925_dma_layout;
457
458 ret = mt792x_dma_alloc_queues(dev, layout);
459 if (ret)
460 return ret;
461
462 ret = mt76_init_queues(dev, mt792x_poll_rx);
463 if (ret < 0)
464 return ret;
465
466 if (is_mt7928(&dev->mt76))
467 mt7928_dma_shdl_lite_init(dev);
468
469 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
470 mt792x_poll_tx);
471 napi_enable(&dev->mt76.tx_napi);
472
473 return mt792x_dma_enable(dev);
474 }
475
476 static const struct mt792x_pcie_reg mt7925_pcie_reg = {
477 .imask = MT7925_PCIE_MAC_INT_ENABLE,
478 .pm = MT7925_PCIE_MAC_PM,
479 };
480
481 static const struct mt792x_pcie_reg mt7928_pcie_reg = {
482 .imask = MT7928_PCIE_MAC_INT_ENABLE,
483 .pm = MT7928_PCIE_MAC_PM,
484 };
485
486 static const struct mt792x_irq_map mt7925_irq_map = {
487 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
488 .tx = {
489 .all_complete_mask = MT_INT_TX_DONE_ALL,
490 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
491 },
492 .rx = {
493 .all_complete_mask = MT7925_INT_RX_DONE_ALL,
494 .data_complete_mask = MT7925_INT_RX_DONE_DATA,
495 .wm_complete_mask = MT7925_INT_RX_DONE_WM,
496 .wm2_complete_mask = MT_INT_RX_DONE_WM2,
497 },
498 };
499
500 static const struct mt792x_irq_map mt7927_irq_map = {
501 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
502 .tx = {
503 .all_complete_mask = MT_INT_TX_DONE_ALL,
504 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
505 },
506 .rx = {
507 .all_complete_mask = MT7927_INT_RX_DONE_ALL,
508 .data_complete_mask = MT7927_INT_RX_DONE_DATA,
509 .wm_complete_mask = MT7927_INT_RX_DONE_WM,
510 .wm2_complete_mask = MT7927_INT_RX_DONE_WM2,
511 },
512 };
513
514 static const struct mt792x_irq_map mt7928_irq_map = {
515 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
516 .tx = {
517 .all_complete_mask = MT_INT_TX_DONE_ALL,
518 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
519 },
520 .rx = {
521 .all_complete_mask = MT7928_INT_RX_DONE_ALL,
522 .data_complete_mask = MT7928_INT_RX_DONE_DATA,
523 .wm_complete_mask = MT7928_INT_RX_DONE_WM,
524 .wm2_complete_mask = MT_INT_RX_DONE_WM2,
525 },
526 };
527
mt7925_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)528 static int mt7925_pci_probe(struct pci_dev *pdev,
529 const struct pci_device_id *id)
530 {
531 static const struct mt76_driver_ops drv_ops = {
532 /* txwi_size = txd size + txp size */
533 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
534 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
535 MT_DRV_AMSDU_OFFLOAD,
536 .survey_flags = SURVEY_INFO_TIME_TX |
537 SURVEY_INFO_TIME_RX |
538 SURVEY_INFO_TIME_BSS_RX,
539 .token_size = MT7925_TOKEN_SIZE,
540 .tx_prepare_skb = mt7925e_tx_prepare_skb,
541 .tx_complete_skb = mt76_connac_tx_complete_skb,
542 .rx_check = mt7925_rx_check,
543 .rx_skb = mt7925_queue_rx_skb,
544 .rx_poll_complete = mt792x_rx_poll_complete,
545 .sta_add = mt7925_mac_sta_add,
546 .sta_event = mt7925_mac_sta_event,
547 .sta_remove = mt7925_mac_sta_remove,
548 .update_survey = mt792x_update_channel,
549 };
550 static const struct mt792x_hif_ops mt7925_pcie_ops = {
551 .init_reset = mt7925e_init_reset,
552 .reset = mt7925e_mac_reset,
553 .mcu_init = mt7925e_mcu_init,
554 .drv_own = mt792xe_mcu_drv_pmctrl,
555 .fw_own = mt792xe_mcu_fw_pmctrl,
556 };
557 bool is_mt7927_hw, is_mt7928_hw;
558 struct mt76_bus_ops *bus_ops;
559 struct ieee80211_ops *ops;
560 struct mt792x_dev *dev;
561 struct mt76_dev *mdev;
562 u8 features;
563 int ret;
564 u16 cmd;
565
566 ret = pcim_enable_device(pdev);
567 if (ret)
568 return ret;
569
570 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
571 if (ret)
572 return ret;
573
574 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
575 if (!(cmd & PCI_COMMAND_MEMORY)) {
576 cmd |= PCI_COMMAND_MEMORY;
577 pci_write_config_word(pdev, PCI_COMMAND, cmd);
578 }
579 pci_set_master(pdev);
580
581 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
582 if (ret < 0)
583 return ret;
584
585 is_mt7927_hw = (pdev->device == 0x6639 || pdev->device == 0x7927 ||
586 pdev->device == 0x0738);
587 is_mt7928_hw = (pdev->device == 0x7928 || pdev->device == 0x7935);
588
589 if (is_mt7928_hw)
590 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(34));
591 else
592 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
593
594 if (ret)
595 goto err_free_pci_vec;
596
597 /* MT7927: ASPM L1 causes unreliable WFDMA register access */
598 if (mt7925_disable_aspm || is_mt7927_hw)
599 mt76_pci_disable_aspm(pdev);
600
601 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7925_ops,
602 (void *)id->driver_data, &features);
603 if (!ops) {
604 ret = -ENOMEM;
605 goto err_free_pci_vec;
606 }
607
608 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
609 if (!mdev) {
610 ret = -ENOMEM;
611 goto err_free_pci_vec;
612 }
613
614 pci_set_drvdata(pdev, mdev);
615
616 dev = container_of(mdev, struct mt792x_dev, mt76);
617 dev->fw_features = features;
618 dev->hif_ops = &mt7925_pcie_ops;
619 dev->pcie_reg = &mt7925_pcie_reg;
620
621 if (is_mt7928_hw) {
622 dev->pcie_reg = &mt7928_pcie_reg;
623 dev->irq_map = &mt7928_irq_map;
624 mdev->rev = 0x7928 << 16;
625 } else if (is_mt7927_hw) {
626 dev->irq_map = &mt7927_irq_map;
627 } else {
628 dev->irq_map = &mt7925_irq_map;
629 }
630
631 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
632 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
633
634 dev->phy.dev = dev;
635 dev->phy.mt76 = &dev->mt76.phy;
636 dev->mt76.phy.priv = &dev->phy;
637 dev->bus_ops = dev->mt76.bus;
638 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
639 GFP_KERNEL);
640 if (!bus_ops) {
641 ret = -ENOMEM;
642 goto err_free_dev;
643 }
644
645 bus_ops->rr = mt7925_rr;
646 bus_ops->wr = mt7925_wr;
647 bus_ops->rmw = mt7925_rmw;
648 dev->mt76.bus = bus_ops;
649
650 if (!mt7925_disable_aspm && mt76_pci_aspm_supported(pdev))
651 dev->aspm_supported = true;
652
653 if (is_mt7928(&dev->mt76))
654 dev->skip_wpdma_reinit = true;
655
656 ret = __mt792x_mcu_fw_pmctrl(dev);
657 if (ret)
658 goto err_free_dev;
659
660 ret = __mt792xe_mcu_drv_pmctrl(dev);
661 if (ret)
662 goto err_free_dev;
663
664 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
665 (mt76_rr(dev, MT_HW_REV) & 0xff);
666
667 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
668
669 if (is_mt7927_hw && mt76_chip(mdev) != 0x7927) {
670 dev_info(mdev->dev,
671 "MT7927 raw CHIPID=0x%04x, forcing chip=0x7927\n",
672 mt76_chip(mdev));
673 mdev->rev = (0x7927 << 16) | (mdev->rev & 0xff);
674 } else if (is_mt7928_hw && mt76_chip(mdev) != 0x7928) {
675 dev_info(mdev->dev,
676 "MT7928 raw CHIPID=0x%04x, forcing chip=0x7928\n",
677 mt76_chip(mdev));
678 mdev->rev = (0x7928 << 16) | (mdev->rev & 0xff);
679 }
680
681 mt76_rmw_field(dev, MT_HW_EMI_CTL, MT_HW_EMI_CTL_SLPPROT_EN, 1);
682
683 ret = mt792x_wfsys_reset(dev);
684 if (ret)
685 goto err_free_dev;
686
687 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
688 mt76_wr(dev, dev->pcie_reg->imask, 0xff);
689
690 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
691 IRQF_SHARED, KBUILD_MODNAME, dev);
692 if (ret)
693 goto err_free_dev;
694
695 if (is_mt7927(&dev->mt76))
696 ret = mt7927_dma_init(dev);
697 else if (is_mt7925(&dev->mt76) || is_mt7928(&dev->mt76))
698 ret = mt7925_dma_init(dev);
699 else
700 ret = -EINVAL;
701
702 if (ret)
703 goto err_free_irq;
704
705 ret = mt7925_register_device(dev);
706 if (ret)
707 goto err_free_dma;
708
709 return 0;
710
711 err_free_dma:
712 mt792x_dma_cleanup(dev);
713 err_free_irq:
714 devm_free_irq(&pdev->dev, pdev->irq, dev);
715 err_free_dev:
716 mt76_free_device(&dev->mt76);
717 err_free_pci_vec:
718 pci_free_irq_vectors(pdev);
719
720 return ret;
721 }
722
mt7925_pci_remove(struct pci_dev * pdev)723 static void mt7925_pci_remove(struct pci_dev *pdev)
724 {
725 struct mt76_dev *mdev = pci_get_drvdata(pdev);
726 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
727
728 set_bit(MT76_REMOVED, &mdev->phy.state);
729 mt7925e_unregister_device(dev);
730 devm_free_irq(&pdev->dev, pdev->irq, dev);
731 mt76_free_device(&dev->mt76);
732 pci_free_irq_vectors(pdev);
733 }
734
mt7925_pci_suspend(struct device * device)735 static int mt7925_pci_suspend(struct device *device)
736 {
737 struct pci_dev *pdev = to_pci_dev(device);
738 struct mt76_dev *mdev = pci_get_drvdata(pdev);
739 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
740 struct mt76_connac_pm *pm = &dev->pm;
741 int i, err, ret;
742
743 pm->suspended = true;
744 dev->hif_resumed = false;
745 flush_work(&dev->reset_work);
746 cancel_delayed_work_sync(&pm->ps_work);
747 cancel_delayed_work_sync(&dev->mlo_pm_work);
748 cancel_work_sync(&pm->wake_work);
749
750 mt7925_roc_abort_sync(dev);
751
752 err = mt792x_mcu_drv_pmctrl(dev);
753 if (err < 0)
754 goto restore_suspend;
755
756 wait_event_timeout(dev->wait,
757 !dev->regd_in_progress, 5 * HZ);
758
759 /* always enable deep sleep during suspend to reduce
760 * power consumption
761 */
762 mt7925_mcu_set_deep_sleep(dev, true);
763
764 mt76_connac_mcu_set_hif_suspend(mdev, true, false);
765 ret = wait_event_timeout(dev->wait,
766 dev->hif_idle, 3 * HZ);
767 if (!ret) {
768 err = -ETIMEDOUT;
769 goto restore_suspend;
770 }
771
772 napi_disable(&mdev->tx_napi);
773 mt76_worker_disable(&mdev->tx_worker);
774
775 mt76_for_each_q_rx(mdev, i) {
776 napi_disable(&mdev->napi[i]);
777 }
778
779 /* wait until dma is idle */
780 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
781 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
782 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
783
784 /* put dma disabled */
785 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
786 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
787
788 /* disable interrupt */
789 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
790 mt76_wr(dev, dev->pcie_reg->imask, 0x0);
791
792 synchronize_irq(pdev->irq);
793 tasklet_kill(&mdev->irq_tasklet);
794
795 err = mt792x_mcu_fw_pmctrl(dev);
796 if (err)
797 goto restore_napi;
798
799 return 0;
800
801 restore_napi:
802 mt76_for_each_q_rx(mdev, i) {
803 napi_enable(&mdev->napi[i]);
804 }
805 napi_enable(&mdev->tx_napi);
806
807 if (!pm->ds_enable)
808 mt7925_mcu_set_deep_sleep(dev, false);
809
810 mt76_connac_mcu_set_hif_suspend(mdev, false, false);
811 ret = wait_event_timeout(dev->wait,
812 dev->hif_resumed, 3 * HZ);
813 if (!ret)
814 err = -ETIMEDOUT;
815 restore_suspend:
816 pm->suspended = false;
817
818 if (err < 0)
819 mt792x_reset(&dev->mt76);
820
821 return err;
822 }
823
_mt7925_pci_resume(struct device * device,bool restore)824 static int _mt7925_pci_resume(struct device *device, bool restore)
825 {
826 struct pci_dev *pdev = to_pci_dev(device);
827 struct mt76_dev *mdev = pci_get_drvdata(pdev);
828 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
829 struct mt76_connac_pm *pm = &dev->pm;
830 int i, err, ret;
831
832 dev->hif_idle = false;
833 err = mt792x_mcu_drv_pmctrl(dev);
834 if (err < 0)
835 goto failed;
836
837 mt792x_wpdma_reinit_cond(dev);
838
839 /* enable interrupt */
840 mt76_wr(dev, dev->pcie_reg->imask, 0xff);
841 mt76_connac_irq_enable(&dev->mt76,
842 dev->irq_map->tx.all_complete_mask |
843 dev->irq_map->rx.all_complete_mask |
844 MT_INT_MCU_CMD);
845 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
846
847 /* put dma enabled */
848 mt76_set(dev, MT_WFDMA0_GLO_CFG,
849 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
850
851 mt76_worker_enable(&mdev->tx_worker);
852
853 mt76_for_each_q_rx(mdev, i) {
854 napi_enable(&mdev->napi[i]);
855 }
856 napi_enable(&mdev->tx_napi);
857
858 local_bh_disable();
859 mt76_for_each_q_rx(mdev, i) {
860 napi_schedule(&mdev->napi[i]);
861 }
862 napi_schedule(&mdev->tx_napi);
863 local_bh_enable();
864
865 if (restore)
866 goto failed;
867
868 mt76_connac_mcu_set_hif_suspend(mdev, false, false);
869 ret = wait_event_timeout(dev->wait,
870 dev->hif_resumed, 3 * HZ);
871 if (!ret) {
872 err = -ETIMEDOUT;
873 goto failed;
874 }
875
876 /* restore previous ds setting */
877 if (!pm->ds_enable)
878 mt7925_mcu_set_deep_sleep(dev, false);
879
880 mt7925_mcu_regd_update(dev, mdev->alpha2, dev->country_ie_env);
881 failed:
882 pm->suspended = false;
883
884 if (err < 0 || restore)
885 mt792x_reset(&dev->mt76);
886
887 return err;
888 }
889
mt7925_pci_shutdown(struct pci_dev * pdev)890 static void mt7925_pci_shutdown(struct pci_dev *pdev)
891 {
892 mt7925_pci_remove(pdev);
893 }
894
mt7925_pci_resume(struct device * device)895 static int mt7925_pci_resume(struct device *device)
896 {
897 return _mt7925_pci_resume(device, false);
898 }
899
mt7925_pci_restore(struct device * device)900 static int mt7925_pci_restore(struct device *device)
901 {
902 return _mt7925_pci_resume(device, true);
903 }
904
905 static const struct dev_pm_ops mt7925_pm_ops = {
906 .suspend = pm_sleep_ptr(mt7925_pci_suspend),
907 .resume = pm_sleep_ptr(mt7925_pci_resume),
908 .freeze = pm_sleep_ptr(mt7925_pci_suspend),
909 .thaw = pm_sleep_ptr(mt7925_pci_resume),
910 .poweroff = pm_sleep_ptr(mt7925_pci_suspend),
911 .restore = pm_sleep_ptr(mt7925_pci_restore),
912 };
913
914 static struct pci_driver mt7925_pci_driver = {
915 .name = KBUILD_MODNAME,
916 .id_table = mt7925_pci_device_table,
917 .probe = mt7925_pci_probe,
918 .remove = mt7925_pci_remove,
919 .shutdown = mt7925_pci_shutdown,
920 .driver.pm = pm_sleep_ptr(&mt7925_pm_ops),
921 };
922
923 module_pci_driver(mt7925_pci_driver);
924
925 MODULE_DEVICE_TABLE(pci, mt7925_pci_device_table);
926 MODULE_FIRMWARE(MT7925_FIRMWARE_WM);
927 MODULE_FIRMWARE(MT7925_ROM_PATCH);
928 MODULE_FIRMWARE(MT7927_FIRMWARE_WM);
929 MODULE_FIRMWARE(MT7927_ROM_PATCH);
930 MODULE_FIRMWARE(MT7928_FIRMWARE_WM);
931 MODULE_FIRMWARE(MT7928_ROM_PATCH);
932 MODULE_FIRMWARE(MT7928_CB_ROM_PATCH);
933 MODULE_FIRMWARE(MT7928_PHY_RAM);
934 MODULE_AUTHOR("Deren Wu <deren.wu@mediatek.com>");
935 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
936 MODULE_DESCRIPTION("MediaTek MT7925E (PCIe) wireless driver");
937 MODULE_LICENSE("Dual BSD/GPL");
938