1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/of.h>
10
11 #include "mt7921.h"
12 #include "../mt76_connac2_mac.h"
13 #include "../dma.h"
14 #include "mcu.h"
15 #include "regd.h"
16
17 static const struct pci_device_id mt7921_pci_device_table[] = {
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
19 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
21 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
22 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
23 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
25 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
26 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
27 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
28 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
29 .driver_data = (kernel_ulong_t)MT7920_FIRMWARE_WM },
30 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7902),
31 .driver_data = (kernel_ulong_t)MT7902_FIRMWARE_WM },
32 { },
33 };
34
35 static bool mt7921_disable_aspm;
36 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
37 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
38
mt7921e_init_reset(struct mt792x_dev * dev)39 static int mt7921e_init_reset(struct mt792x_dev *dev)
40 {
41 return mt792x_wpdma_reset(dev, true);
42 }
43
mt7921e_unregister_device(struct mt792x_dev * dev)44 static void mt7921e_unregister_device(struct mt792x_dev *dev)
45 {
46 int i;
47 struct mt76_connac_pm *pm = &dev->pm;
48 struct ieee80211_hw *hw = mt76_hw(dev);
49
50 if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN)
51 wiphy_rfkill_stop_polling(hw->wiphy);
52
53 cancel_work_sync(&dev->init_work);
54 mt76_unregister_device(&dev->mt76);
55 mt76_for_each_q_rx(&dev->mt76, i)
56 napi_disable(&dev->mt76.napi[i]);
57 cancel_delayed_work_sync(&pm->ps_work);
58 cancel_work_sync(&pm->wake_work);
59 cancel_work_sync(&dev->reset_work);
60
61 mt76_connac2_tx_token_put(&dev->mt76);
62 __mt792x_mcu_drv_pmctrl(dev);
63 mt792x_dma_cleanup(dev);
64 mt792x_wfsys_reset(dev);
65 skb_queue_purge(&dev->mt76.mcu.res_q);
66
67 tasklet_disable(&dev->mt76.irq_tasklet);
68 }
69
__mt7921_reg_addr(struct mt792x_dev * dev,u32 addr)70 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr)
71 {
72 static const struct mt76_connac_reg_map fixed_map[] = {
73 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
74 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
75 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
76 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
77 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
78 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
79 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
80 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
81 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
82 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
83 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
84 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
85 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
86 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
87 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
88 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
89 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
90 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
91 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
92 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
93 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
94 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
95 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
96 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
97 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
98 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
99 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
100 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
101 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
102 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
103 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
104 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
105 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
106 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
107 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
108 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
109 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
110 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
111 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
112 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
113 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
114 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
115 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
116 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
117 };
118 int i;
119
120 if (addr < 0x100000)
121 return addr;
122
123 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
124 u32 ofs;
125
126 if (addr < fixed_map[i].phys)
127 continue;
128
129 ofs = addr - fixed_map[i].phys;
130 if (ofs > fixed_map[i].size)
131 continue;
132
133 return fixed_map[i].maps + ofs;
134 }
135
136 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
137 (addr >= 0x70000000 && addr < 0x78000000) ||
138 (addr >= 0x7c000000 && addr < 0x7c400000))
139 return mt7921_reg_map_l1(dev, addr);
140
141 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
142 addr);
143
144 return 0;
145 }
146
mt7921_rr(struct mt76_dev * mdev,u32 offset)147 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
148 {
149 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
150 u32 addr = __mt7921_reg_addr(dev, offset);
151
152 return dev->bus_ops->rr(mdev, addr);
153 }
154
mt7921_wr(struct mt76_dev * mdev,u32 offset,u32 val)155 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
156 {
157 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
158 u32 addr = __mt7921_reg_addr(dev, offset);
159
160 dev->bus_ops->wr(mdev, addr, val);
161 }
162
mt7921_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)163 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
164 {
165 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
166 u32 addr = __mt7921_reg_addr(dev, offset);
167
168 return dev->bus_ops->rmw(mdev, addr, mask, val);
169 }
170
mt7921_dma_init(struct mt792x_dev * dev)171 static int mt7921_dma_init(struct mt792x_dev *dev)
172 {
173 struct mt7921_dma_layout layout = {
174 /* General case: MT7921 / MT7922 /MT7920 */
175 .mcu_wm_txq = MT7921_TXQ_MCU_WM,
176 .mcu_rxdone_ring_size = MT7921_RX_MCU_RING_SIZE,
177 .has_mcu_wa = true,
178 };
179 bool is_mt7902;
180 int ret;
181
182 is_mt7902 = mt7921_l1_rr(dev, MT_HW_CHIPID) == 0x7902;
183
184 /*
185 * MT7902 special case:
186 * - MCU-WM TXQ uses index 15
187 * - RX Ring0 is larger and shared for event/TX-done
188 * - MT7902 does not use the MCU_WA ring
189 */
190 if (is_mt7902) {
191 layout.mcu_wm_txq = MT7902_TXQ_MCU_WM;
192 layout.mcu_rxdone_ring_size = MT7902_RX_MCU_RING_SIZE;
193 layout.has_mcu_wa = false;
194 }
195
196 mt76_dma_attach(&dev->mt76);
197
198 ret = mt792x_dma_disable(dev, true);
199 if (ret)
200 return ret;
201
202 /* init tx queue */
203 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
204 MT7921_TX_RING_SIZE,
205 MT_TX_RING_BASE, NULL, 0);
206 if (ret)
207 return ret;
208
209 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
210
211 /* command to WM */
212 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, layout.mcu_wm_txq,
213 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
214 if (ret)
215 return ret;
216
217 /* firmware download */
218 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
219 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
220 if (ret)
221 return ret;
222
223 /* event from WM before firmware download */
224 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
225 MT7921_RXQ_MCU_WM,
226 layout.mcu_rxdone_ring_size,
227 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
228 if (ret)
229 return ret;
230
231 if (layout.has_mcu_wa) {
232 /* Change mcu queue after firmware download */
233 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
234 MT7921_RXQ_MCU_WM,
235 MT7921_RX_MCU_WA_RING_SIZE,
236 MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
237 if (ret)
238 return ret;
239 }
240
241 /* rx data */
242 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
243 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
244 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
245 if (ret)
246 return ret;
247
248 ret = mt76_init_queues(dev, mt792x_poll_rx);
249 if (ret < 0)
250 return ret;
251
252 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
253 mt792x_poll_tx);
254 napi_enable(&dev->mt76.tx_napi);
255
256 return mt792x_dma_enable(dev);
257 }
258
mt7921_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)259 static int mt7921_pci_probe(struct pci_dev *pdev,
260 const struct pci_device_id *id)
261 {
262 static const struct mt76_driver_ops drv_ops = {
263 /* txwi_size = txd size + txp size */
264 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
265 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
266 MT_DRV_AMSDU_OFFLOAD,
267 .survey_flags = SURVEY_INFO_TIME_TX |
268 SURVEY_INFO_TIME_RX |
269 SURVEY_INFO_TIME_BSS_RX,
270 .token_size = MT7921_TOKEN_SIZE,
271 .tx_prepare_skb = mt7921e_tx_prepare_skb,
272 .tx_complete_skb = mt76_connac_tx_complete_skb,
273 .rx_check = mt7921_rx_check,
274 .rx_skb = mt7921_queue_rx_skb,
275 .rx_poll_complete = mt792x_rx_poll_complete,
276 .sta_add = mt7921_mac_sta_add,
277 .sta_event = mt7921_mac_sta_event,
278 .sta_remove = mt7921_mac_sta_remove,
279 .update_survey = mt792x_update_channel,
280 .set_channel = mt7921_set_channel,
281 };
282 static const struct mt792x_hif_ops mt7921_pcie_ops = {
283 .init_reset = mt7921e_init_reset,
284 .reset = mt7921e_mac_reset,
285 .mcu_init = mt7921e_mcu_init,
286 .drv_own = mt792xe_mcu_drv_pmctrl,
287 .fw_own = mt792xe_mcu_fw_pmctrl,
288 };
289 static const struct mt792x_pcie_reg mt7921_pcie_reg = {
290 .imask = MT_PCIE_MAC_INT_ENABLE,
291 .pm = MT_PCIE_MAC_PM,
292 };
293 static const struct mt792x_irq_map irq_map = {
294 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
295 .tx = {
296 .all_complete_mask = MT_INT_TX_DONE_ALL,
297 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
298 },
299 .rx = {
300 .all_complete_mask = MT_INT_RX_DONE_ALL,
301 .data_complete_mask = MT_INT_RX_DONE_DATA,
302 .wm_complete_mask = MT_INT_RX_DONE_WM,
303 .wm2_complete_mask = MT_INT_RX_DONE_WM2,
304 },
305 };
306 struct ieee80211_ops *ops;
307 struct mt76_bus_ops *bus_ops;
308 struct mt792x_dev *dev;
309 struct mt76_dev *mdev;
310 void __iomem *regs;
311 u16 cmd, chipid;
312 u8 features;
313 int ret;
314
315 ret = pcim_enable_device(pdev);
316 if (ret)
317 return ret;
318
319 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
320 if (!(cmd & PCI_COMMAND_MEMORY)) {
321 cmd |= PCI_COMMAND_MEMORY;
322 pci_write_config_word(pdev, PCI_COMMAND, cmd);
323 }
324 pci_set_master(pdev);
325
326 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
327 if (ret < 0)
328 return ret;
329
330 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
331 if (ret)
332 goto err_free_pci_vec;
333
334 if (mt7921_disable_aspm)
335 mt76_pci_disable_aspm(pdev);
336
337 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops,
338 (void *)id->driver_data, &features);
339 if (!ops) {
340 ret = -ENOMEM;
341 goto err_free_pci_vec;
342 }
343
344 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
345 if (!mdev) {
346 ret = -ENOMEM;
347 goto err_free_pci_vec;
348 }
349
350 pci_set_drvdata(pdev, mdev);
351
352 dev = container_of(mdev, struct mt792x_dev, mt76);
353
354 regs = pcim_iomap_region(pdev, 0, pci_name(pdev));
355 if (IS_ERR(regs)) {
356 ret = PTR_ERR(regs);
357 goto err_free_dev;
358 }
359
360 dev->fw_features = features;
361 dev->hif_ops = &mt7921_pcie_ops;
362 dev->pcie_reg = &mt7921_pcie_reg;
363 dev->irq_map = &irq_map;
364 mt76_mmio_init(&dev->mt76, regs);
365
366 if (id->device == 0x7902) {
367 struct mt792x_irq_map *map;
368
369 /* MT7902 needs a mutable copy because wm2_complete_mask differs */
370 map = devm_kmemdup(&pdev->dev, &irq_map,
371 sizeof(irq_map), GFP_KERNEL);
372 if (!map) {
373 ret = -ENOMEM;
374 goto err_free_dev;
375 }
376
377 map->rx.wm2_complete_mask = 0;
378 dev->irq_map = map;
379 }
380
381 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
382
383 dev->phy.dev = dev;
384 dev->phy.mt76 = &dev->mt76.phy;
385 dev->mt76.phy.priv = &dev->phy;
386 dev->bus_ops = dev->mt76.bus;
387 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
388 GFP_KERNEL);
389 if (!bus_ops) {
390 ret = -ENOMEM;
391 goto err_free_dev;
392 }
393
394 bus_ops->rr = mt7921_rr;
395 bus_ops->wr = mt7921_wr;
396 bus_ops->rmw = mt7921_rmw;
397 dev->mt76.bus = bus_ops;
398
399 if (!mt7921_disable_aspm && mt76_pci_aspm_supported(pdev))
400 dev->aspm_supported = true;
401
402 ret = mt792xe_mcu_fw_pmctrl(dev);
403 if (ret)
404 goto err_free_dev;
405
406 ret = __mt792xe_mcu_drv_pmctrl(dev);
407 if (ret)
408 goto err_free_dev;
409
410 chipid = mt7921_l1_rr(dev, MT_HW_CHIPID);
411 if (chipid == 0x7961 && (mt7921_l1_rr(dev, MT_HW_BOUND) & BIT(7)))
412 chipid = 0x7920;
413 mdev->rev = (chipid << 16) |
414 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
415 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
416
417 ret = mt792x_wfsys_reset(dev);
418 if (ret)
419 goto err_free_dev;
420
421 mt76_wr(dev, irq_map.host_irq_enable, 0);
422
423 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
424
425 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
426 IRQF_SHARED, KBUILD_MODNAME, dev);
427 if (ret)
428 goto err_free_dev;
429
430 ret = mt7921_dma_init(dev);
431 if (ret)
432 goto err_free_irq;
433
434 ret = mt7921_register_device(dev);
435 if (ret)
436 goto err_free_irq;
437
438 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
439 device_init_wakeup(dev->mt76.dev, true);
440
441 return 0;
442
443 err_free_irq:
444 devm_free_irq(&pdev->dev, pdev->irq, dev);
445 err_free_dev:
446 mt76_free_device(&dev->mt76);
447 err_free_pci_vec:
448 pci_free_irq_vectors(pdev);
449
450 return ret;
451 }
452
mt7921_pci_remove(struct pci_dev * pdev)453 static void mt7921_pci_remove(struct pci_dev *pdev)
454 {
455 struct mt76_dev *mdev = pci_get_drvdata(pdev);
456 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
457
458 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source"))
459 device_init_wakeup(dev->mt76.dev, false);
460
461 mt7921e_unregister_device(dev);
462 set_bit(MT76_REMOVED, &mdev->phy.state);
463 devm_free_irq(&pdev->dev, pdev->irq, dev);
464 mt76_free_device(&dev->mt76);
465 pci_free_irq_vectors(pdev);
466 }
467
mt7921_pci_suspend(struct device * device)468 static int mt7921_pci_suspend(struct device *device)
469 {
470 struct pci_dev *pdev = to_pci_dev(device);
471 struct mt76_dev *mdev = pci_get_drvdata(pdev);
472 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
473 struct mt76_connac_pm *pm = &dev->pm;
474 int i, err;
475
476 pm->suspended = true;
477 flush_work(&dev->reset_work);
478 cancel_delayed_work_sync(&pm->ps_work);
479 cancel_work_sync(&pm->wake_work);
480
481 mt7921_roc_abort_sync(dev);
482
483 err = mt792x_mcu_drv_pmctrl(dev);
484 if (err < 0)
485 goto restore_suspend;
486
487 wait_event_timeout(dev->wait,
488 !dev->regd_in_progress, 5 * HZ);
489
490 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_OFF_LED);
491 if (err < 0)
492 goto restore_suspend;
493
494 err = mt76_connac_mcu_set_hif_suspend(mdev, true, true);
495 if (err)
496 goto restore_suspend;
497
498 /* always enable deep sleep during suspend to reduce
499 * power consumption
500 */
501 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
502
503 napi_disable(&mdev->tx_napi);
504 mt76_worker_disable(&mdev->tx_worker);
505
506 mt76_for_each_q_rx(mdev, i) {
507 napi_disable(&mdev->napi[i]);
508 }
509
510 /* wait until dma is idle */
511 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
512 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
513 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
514
515 /* put dma disabled */
516 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
517 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
518
519 /* disable interrupt */
520 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
521 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
522 synchronize_irq(pdev->irq);
523 tasklet_kill(&mdev->irq_tasklet);
524
525 err = mt792x_mcu_fw_pmctrl(dev);
526 if (err)
527 goto restore_napi;
528
529 return 0;
530
531 restore_napi:
532 mt76_for_each_q_rx(mdev, i) {
533 napi_enable(&mdev->napi[i]);
534 }
535 napi_enable(&mdev->tx_napi);
536
537 if (!pm->ds_enable)
538 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
539
540 mt76_connac_mcu_set_hif_suspend(mdev, false, true);
541
542 restore_suspend:
543 pm->suspended = false;
544
545 if (err < 0)
546 mt792x_reset(&dev->mt76);
547
548 return err;
549 }
550
mt7921_pci_resume(struct device * device)551 static int mt7921_pci_resume(struct device *device)
552 {
553 struct pci_dev *pdev = to_pci_dev(device);
554 struct mt76_dev *mdev = pci_get_drvdata(pdev);
555 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
556 struct mt76_connac_pm *pm = &dev->pm;
557 int i, err;
558
559 err = mt792x_mcu_drv_pmctrl(dev);
560 if (err < 0)
561 goto failed;
562
563 mt792x_wpdma_reinit_cond(dev);
564
565 /* enable interrupt */
566 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
567 mt76_connac_irq_enable(&dev->mt76,
568 dev->irq_map->tx.all_complete_mask |
569 dev->irq_map->rx.all_complete_mask |
570 MT_INT_MCU_CMD);
571 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
572
573 /* put dma enabled */
574 mt76_set(dev, MT_WFDMA0_GLO_CFG,
575 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
576
577 mt76_worker_enable(&mdev->tx_worker);
578
579 mt76_for_each_q_rx(mdev, i) {
580 napi_enable(&mdev->napi[i]);
581 }
582 napi_enable(&mdev->tx_napi);
583
584 local_bh_disable();
585 mt76_for_each_q_rx(mdev, i) {
586 napi_schedule(&mdev->napi[i]);
587 }
588 napi_schedule(&mdev->tx_napi);
589 local_bh_enable();
590
591 /* restore previous ds setting */
592 if (!pm->ds_enable)
593 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
594
595 err = mt76_connac_mcu_set_hif_suspend(mdev, false, true);
596 if (err < 0)
597 goto failed;
598
599 mt7921_mcu_regd_update(dev, mdev->alpha2, dev->country_ie_env);
600 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_ON_LED);
601 failed:
602 pm->suspended = false;
603
604 if (err < 0)
605 mt792x_reset(&dev->mt76);
606
607 return err;
608 }
609
mt7921_aer_rr(struct mt76_dev * mdev,u32 offset)610 static u32 mt7921_aer_rr(struct mt76_dev *mdev, u32 offset)
611 {
612 return 0;
613 }
614
mt7921_aer_wr(struct mt76_dev * mdev,u32 offset,u32 val)615 static void mt7921_aer_wr(struct mt76_dev *mdev, u32 offset, u32 val)
616 {
617 ;
618 }
619
mt791_aer_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)620 static u32 mt791_aer_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
621 {
622 return 0;
623 }
624
625 static const struct mt76_bus_ops mt7921_aer_bus_hung_ops = {
626 .rr = mt7921_aer_rr,
627 .wr = mt7921_aer_wr,
628 .rmw = mt791_aer_rmw,
629 .type = MT76_BUS_MMIO
630 };
631
mt7921_pci_set_aer_bus_hung_ops(struct mt792x_dev * dev)632 static void mt7921_pci_set_aer_bus_hung_ops(struct mt792x_dev *dev)
633 {
634 if (READ_ONCE(dev->mt76.bus) == &mt7921_aer_bus_hung_ops)
635 return;
636
637 atomic_set(&dev->mt76.bus_hung, true);
638 WRITE_ONCE(dev->mt76.bus, &mt7921_aer_bus_hung_ops);
639 }
640
mt7921_error_detected(struct pci_dev * pdev,pci_channel_state_t state)641 static pci_ers_result_t mt7921_error_detected(struct pci_dev *pdev,
642 pci_channel_state_t state)
643 {
644 struct mt76_dev *mdev = pci_get_drvdata(pdev);
645 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
646 u32 aer_unc_val = 0, aer_co_val = 0;
647
648 dev_err(mdev->dev, "PCIE error detect state: %d\n", state);
649
650 /* Clear SW IRQ tasklet first */
651 tasklet_kill(&mdev->irq_tasklet);
652
653 if (state == pci_channel_io_perm_failure) {
654 mt7921_pci_set_aer_bus_hung_ops(dev);
655 return PCI_ERS_RESULT_DISCONNECT;
656 }
657
658 pci_read_config_dword(pdev, PCIE_AER_UNC_STATUS_OFFSET, &aer_unc_val);
659 pci_read_config_dword(pdev, PCIE_AER_CO_STATUS_OFFSET, &aer_co_val);
660
661 dev_warn(mdev->dev, "PCIE_AER_UNC_STATUS_OFFSET: 0x%x\n", aer_unc_val);
662 dev_warn(mdev->dev, "PCIE_AER_CO_STATUS_OFFSET: 0x%x\n", aer_co_val);
663
664 /**
665 * Due to this error is from link error and this AER is un-correctable,
666 * so can't covered by device
667 **/
668 if (aer_unc_val != 0) {
669 mt7921_pci_set_aer_bus_hung_ops(dev);
670 return PCI_ERS_RESULT_DISCONNECT;
671 }
672
673 /**
674 * Try to recover it when state is pci_channel_io_frozen or
675 * AER is correctable error
676 **/
677 if (state == pci_channel_io_frozen || aer_co_val != 0) {
678 /* Disable PCIE activity first. */
679 pci_disable_device(pdev);
680 return PCI_ERS_RESULT_NEED_RESET;
681 }
682
683 return PCI_ERS_RESULT_NONE;
684 }
685
mt7921_slot_reset(struct pci_dev * pdev)686 static pci_ers_result_t mt7921_slot_reset(struct pci_dev *pdev)
687 {
688 struct mt76_dev *mdev = pci_get_drvdata(pdev);
689 int ret = 0;
690
691 ret = pci_enable_device_mem(pdev);
692
693 if (ret) {
694 dev_err(mdev->dev, "pci_enable_device_mem failed: %d\n", ret);
695 return PCI_ERS_RESULT_DISCONNECT;
696 }
697
698 pci_set_master(pdev);
699 pci_restore_state(pdev);
700 pci_save_state(pdev);
701 /* Also try do the vendor reset to let it more clear. */
702 mt792x_reset(mdev);
703
704 return PCI_ERS_RESULT_RECOVERED;
705 }
706
707 static const struct pci_error_handlers mt7921_err_handler = {
708 .error_detected = mt7921_error_detected,
709 .slot_reset = mt7921_slot_reset,
710 };
711
mt7921_pci_shutdown(struct pci_dev * pdev)712 static void mt7921_pci_shutdown(struct pci_dev *pdev)
713 {
714 mt7921_pci_remove(pdev);
715 }
716
717 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
718
719 static struct pci_driver mt7921_pci_driver = {
720 .name = KBUILD_MODNAME,
721 .id_table = mt7921_pci_device_table,
722 .probe = mt7921_pci_probe,
723 .remove = mt7921_pci_remove,
724 .shutdown = mt7921_pci_shutdown,
725 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops),
726 .err_handler = &mt7921_err_handler,
727 };
728
729 module_pci_driver(mt7921_pci_driver);
730
731 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
732 MODULE_FIRMWARE(MT7920_FIRMWARE_WM);
733 MODULE_FIRMWARE(MT7920_ROM_PATCH);
734 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
735 MODULE_FIRMWARE(MT7921_ROM_PATCH);
736 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
737 MODULE_FIRMWARE(MT7922_ROM_PATCH);
738 MODULE_FIRMWARE(MT7902_FIRMWARE_WM);
739 MODULE_FIRMWARE(MT7902_ROM_PATCH);
740 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
741 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
742 MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver");
743 MODULE_LICENSE("Dual BSD/GPL");
744