1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/debugfs.h>
11 #include <linux/of_address.h>
12 #include <linux/uaccess.h>
13
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_of.h>
18
19 #include "msm_drv.h"
20 #include "msm_debugfs.h"
21 #include "msm_gem.h"
22 #include "msm_gpu.h"
23 #include "msm_kms.h"
24
25 /*
26 * MSM driver version:
27 * - 1.0.0 - initial interface
28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
29 * - 1.2.0 - adds explicit fence support for submit ioctl
30 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
31 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
32 * MSM_GEM_INFO ioctl.
33 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
34 * GEM object's debug name
35 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
36 * - 1.6.0 - Syncobj support
37 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
39 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
40 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
41 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
42 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA
43 * - 1.13.0 - Add VM_BIND
44 */
45 #define MSM_VERSION_MAJOR 1
46 #define MSM_VERSION_MINOR 13
47 #define MSM_VERSION_PATCHLEVEL 0
48
49 bool dumpstate;
50 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
51 module_param(dumpstate, bool, 0600);
52
53 static bool modeset = true;
54 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
55 module_param(modeset, bool, 0600);
56
57 static bool separate_gpu_kms;
58 MODULE_PARM_DESC(separate_gpu_drm, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)");
59 module_param(separate_gpu_kms, bool, 0400);
60
61 DECLARE_FAULT_ATTR(fail_gem_alloc);
62 DECLARE_FAULT_ATTR(fail_gem_iova);
63
msm_gpu_no_components(void)64 bool msm_gpu_no_components(void)
65 {
66 return separate_gpu_kms;
67 }
68
msm_drm_uninit(struct device * dev,const struct component_ops * gpu_ops)69 static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops)
70 {
71 struct platform_device *pdev = to_platform_device(dev);
72 struct msm_drm_private *priv = platform_get_drvdata(pdev);
73 struct drm_device *ddev = priv->dev;
74
75 /*
76 * Shutdown the hw if we're far enough along where things might be on.
77 * If we run this too early, we'll end up panicking in any variety of
78 * places. Since we don't register the drm device until late in
79 * msm_drm_init, drm_dev->registered is used as an indicator that the
80 * shutdown will be successful.
81 */
82 if (ddev->registered) {
83 drm_dev_unregister(ddev);
84 if (priv->kms)
85 msm_drm_kms_unregister(dev);
86 }
87
88 msm_gem_shrinker_cleanup(ddev);
89
90 msm_perf_debugfs_cleanup(priv);
91 msm_rd_debugfs_cleanup(priv);
92
93 if (priv->kms)
94 msm_drm_kms_uninit(dev);
95
96 if (gpu_ops)
97 gpu_ops->unbind(dev, dev, NULL);
98 else
99 component_unbind_all(dev, ddev);
100
101 ddev->dev_private = NULL;
102 drm_dev_put(ddev);
103
104 return 0;
105 }
106
msm_drm_init(struct device * dev,const struct drm_driver * drv,const struct component_ops * gpu_ops)107 static int msm_drm_init(struct device *dev, const struct drm_driver *drv,
108 const struct component_ops *gpu_ops)
109 {
110 struct msm_drm_private *priv = dev_get_drvdata(dev);
111 struct drm_device *ddev;
112 int ret;
113
114 if (drm_firmware_drivers_only())
115 return -ENODEV;
116
117 ddev = drm_dev_alloc(drv, dev);
118 if (IS_ERR(ddev)) {
119 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
120 return PTR_ERR(ddev);
121 }
122 ddev->dev_private = priv;
123 priv->dev = ddev;
124
125 INIT_LIST_HEAD(&priv->objects);
126 mutex_init(&priv->obj_lock);
127
128 /*
129 * Initialize the LRUs:
130 */
131 drm_gem_lru_init(&priv->lru.unbacked);
132 drm_gem_lru_init(&priv->lru.pinned);
133 drm_gem_lru_init(&priv->lru.willneed);
134 drm_gem_lru_init(&priv->lru.dontneed);
135
136 /* Initialize stall-on-fault */
137 spin_lock_init(&priv->fault_stall_lock);
138 priv->stall_enabled = true;
139
140 /* Teach lockdep about lock ordering wrt. shrinker: */
141 fs_reclaim_acquire(GFP_KERNEL);
142 might_lock(&ddev->gem_lru_mutex);
143 fs_reclaim_release(GFP_KERNEL);
144
145 if (priv->kms_init) {
146 ret = drmm_mode_config_init(ddev);
147 if (ret)
148 goto err_put_dev;
149 }
150
151 dma_set_max_seg_size(dev, UINT_MAX);
152
153 /* Bind all our sub-components: */
154 if (gpu_ops)
155 ret = gpu_ops->bind(dev, dev, NULL);
156 else
157 ret = component_bind_all(dev, ddev);
158 if (ret)
159 goto err_put_dev;
160
161 ret = msm_gem_shrinker_init(ddev);
162 if (ret)
163 goto err_msm_uninit;
164
165 if (priv->kms_init) {
166 ret = msm_drm_kms_init(dev, drv);
167 if (ret)
168 goto err_msm_uninit;
169 }
170
171 ret = drm_dev_register(ddev, 0);
172 if (ret)
173 goto err_msm_uninit;
174
175 ret = msm_debugfs_late_init(ddev);
176 if (ret)
177 goto err_msm_uninit;
178
179 if (priv->kms_init)
180 msm_drm_kms_post_init(dev);
181
182 return 0;
183
184 err_msm_uninit:
185 msm_drm_uninit(dev, gpu_ops);
186
187 return ret;
188
189 err_put_dev:
190 drm_dev_put(ddev);
191
192 return ret;
193 }
194
195 /*
196 * DRM operations:
197 */
198
load_gpu(struct drm_device * dev)199 static void load_gpu(struct drm_device *dev)
200 {
201 static DEFINE_MUTEX(init_lock);
202 struct msm_drm_private *priv = dev->dev_private;
203
204 mutex_lock(&init_lock);
205
206 if (!priv->gpu)
207 priv->gpu = adreno_load_gpu(dev);
208
209 mutex_unlock(&init_lock);
210 }
211
212 /**
213 * msm_context_vm - lazily create the context's VM
214 *
215 * @dev: the drm device
216 * @ctx: the context
217 *
218 * The VM is lazily created, so that userspace has a chance to opt-in to having
219 * a userspace managed VM before the VM is created.
220 *
221 * Note that this does not return a reference to the VM. Once the VM is created,
222 * it exists for the lifetime of the context.
223 */
msm_context_vm(struct drm_device * dev,struct msm_context * ctx)224 struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx)
225 {
226 static DEFINE_MUTEX(init_lock);
227 struct msm_drm_private *priv = dev->dev_private;
228
229 /* Once ctx->vm is created it is valid for the lifetime of the context: */
230 if (ctx->vm)
231 return ctx->vm;
232
233 mutex_lock(&init_lock);
234 if (!ctx->vm) {
235 ctx->vm = msm_gpu_create_private_vm(
236 priv->gpu, current, !ctx->userspace_managed_vm);
237
238 }
239 mutex_unlock(&init_lock);
240
241 return ctx->vm;
242 }
243
context_init(struct drm_device * dev,struct drm_file * file)244 static int context_init(struct drm_device *dev, struct drm_file *file)
245 {
246 static atomic_t ident = ATOMIC_INIT(0);
247 struct msm_context *ctx;
248
249 ctx = kzalloc_obj(*ctx);
250 if (!ctx)
251 return -ENOMEM;
252
253 INIT_LIST_HEAD(&ctx->submitqueues);
254 rwlock_init(&ctx->queuelock);
255
256 kref_init(&ctx->ref);
257 msm_submitqueue_init(dev, ctx);
258
259 file->driver_priv = ctx;
260
261 ctx->seqno = atomic_inc_return(&ident);
262
263 return 0;
264 }
265
msm_open(struct drm_device * dev,struct drm_file * file)266 static int msm_open(struct drm_device *dev, struct drm_file *file)
267 {
268 /* For now, load gpu on open.. to avoid the requirement of having
269 * firmware in the initrd.
270 */
271 load_gpu(dev);
272
273 return context_init(dev, file);
274 }
275
context_close(struct msm_context * ctx)276 static void context_close(struct msm_context *ctx)
277 {
278 ctx->closed = true;
279 msm_submitqueue_close(ctx);
280 msm_context_put(ctx);
281 }
282
msm_postclose(struct drm_device * dev,struct drm_file * file)283 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
284 {
285 struct msm_drm_private *priv = dev->dev_private;
286 struct msm_context *ctx = file->driver_priv;
287
288 /*
289 * It is not possible to set sysprof param to non-zero if gpu
290 * is not initialized:
291 */
292 if (priv->gpu)
293 msm_context_set_sysprof(ctx, priv->gpu, 0);
294
295 context_close(ctx);
296 }
297
298 /*
299 * DRM ioctls:
300 */
301
msm_ioctl_get_param(struct drm_device * dev,void * data,struct drm_file * file)302 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
303 struct drm_file *file)
304 {
305 struct msm_drm_private *priv = dev->dev_private;
306 struct drm_msm_param *args = data;
307 struct msm_gpu *gpu;
308
309 /* for now, we just have 3d pipe.. eventually this would need to
310 * be more clever to dispatch to appropriate gpu module:
311 */
312 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
313 return -EINVAL;
314
315 gpu = priv->gpu;
316
317 if (!gpu)
318 return -ENXIO;
319
320 return gpu->funcs->get_param(gpu, file->driver_priv,
321 args->param, &args->value, &args->len);
322 }
323
msm_ioctl_set_param(struct drm_device * dev,void * data,struct drm_file * file)324 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
325 struct drm_file *file)
326 {
327 struct msm_drm_private *priv = dev->dev_private;
328 struct drm_msm_param *args = data;
329 struct msm_gpu *gpu;
330
331 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
332 return -EINVAL;
333
334 gpu = priv->gpu;
335
336 if (!gpu)
337 return -ENXIO;
338
339 return gpu->funcs->set_param(gpu, file->driver_priv,
340 args->param, args->value, args->len);
341 }
342
msm_ioctl_gem_new(struct drm_device * dev,void * data,struct drm_file * file)343 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
344 struct drm_file *file)
345 {
346 struct drm_msm_gem_new *args = data;
347 uint32_t flags = args->flags;
348
349 if (args->flags & ~MSM_BO_FLAGS) {
350 DRM_ERROR("invalid flags: %08x\n", args->flags);
351 return -EINVAL;
352 }
353
354 /*
355 * Uncached CPU mappings are deprecated, as of:
356 *
357 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
358 *
359 * So promote them to WC.
360 */
361 if (flags & MSM_BO_UNCACHED) {
362 flags &= ~MSM_BO_CACHED;
363 flags |= MSM_BO_WC;
364 }
365
366 if (should_fail(&fail_gem_alloc, args->size))
367 return -ENOMEM;
368
369 return msm_gem_new_handle(dev, file, args->size,
370 args->flags, &args->handle, NULL);
371 }
372
to_ktime(struct drm_msm_timespec timeout)373 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
374 {
375 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
376 }
377
msm_ioctl_gem_cpu_prep(struct drm_device * dev,void * data,struct drm_file * file)378 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
379 struct drm_file *file)
380 {
381 struct drm_msm_gem_cpu_prep *args = data;
382 struct drm_gem_object *obj;
383 ktime_t timeout = to_ktime(args->timeout);
384 int ret;
385
386 if (args->op & ~MSM_PREP_FLAGS) {
387 DRM_ERROR("invalid op: %08x\n", args->op);
388 return -EINVAL;
389 }
390
391 obj = drm_gem_object_lookup(file, args->handle);
392 if (!obj)
393 return -ENOENT;
394
395 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
396
397 drm_gem_object_put(obj);
398
399 return ret;
400 }
401
msm_ioctl_gem_cpu_fini(struct drm_device * dev,void * data,struct drm_file * file)402 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
403 struct drm_file *file)
404 {
405 struct drm_msm_gem_cpu_fini *args = data;
406 struct drm_gem_object *obj;
407 int ret;
408
409 obj = drm_gem_object_lookup(file, args->handle);
410 if (!obj)
411 return -ENOENT;
412
413 ret = msm_gem_cpu_fini(obj);
414
415 drm_gem_object_put(obj);
416
417 return ret;
418 }
419
msm_ioctl_gem_info_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t * iova)420 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
421 struct drm_file *file, struct drm_gem_object *obj,
422 uint64_t *iova)
423 {
424 struct msm_drm_private *priv = dev->dev_private;
425 struct msm_context *ctx = file->driver_priv;
426
427 if (!priv->gpu)
428 return -EINVAL;
429
430 if (msm_context_is_vmbind(ctx))
431 return UERR(EINVAL, dev, "VM_BIND is enabled");
432
433 if (should_fail(&fail_gem_iova, obj->size))
434 return -ENOMEM;
435
436 /*
437 * Don't pin the memory here - just get an address so that userspace can
438 * be productive
439 */
440 return msm_gem_get_iova(obj, msm_context_vm(dev, ctx), iova);
441 }
442
msm_ioctl_gem_info_set_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t iova)443 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
444 struct drm_file *file, struct drm_gem_object *obj,
445 uint64_t iova)
446 {
447 struct msm_drm_private *priv = dev->dev_private;
448 struct msm_context *ctx = file->driver_priv;
449 struct drm_gpuvm *vm = msm_context_vm(dev, ctx);
450
451 if (!priv->gpu)
452 return -EINVAL;
453
454 if (msm_context_is_vmbind(ctx))
455 return UERR(EINVAL, dev, "VM_BIND is enabled");
456
457 /* Only supported if per-process address space is supported: */
458 if (priv->gpu->vm == vm)
459 return UERR(EOPNOTSUPP, dev, "requires per-process pgtables");
460
461 if (should_fail(&fail_gem_iova, obj->size))
462 return -ENOMEM;
463
464 return msm_gem_set_iova(obj, vm, iova);
465 }
466
msm_ioctl_gem_info_set_metadata(struct drm_gem_object * obj,__user void * metadata,u32 metadata_size)467 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
468 __user void *metadata,
469 u32 metadata_size)
470 {
471 struct msm_gem_object *msm_obj = to_msm_bo(obj);
472 void *new_metadata;
473 void *buf;
474 int ret;
475
476 /* Impose a moderate upper bound on metadata size: */
477 if (metadata_size > 128) {
478 return -EOVERFLOW;
479 }
480
481 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */
482 buf = memdup_user(metadata, metadata_size);
483 if (IS_ERR(buf))
484 return PTR_ERR(buf);
485
486 ret = msm_gem_lock_interruptible(obj);
487 if (ret)
488 goto out;
489
490 new_metadata =
491 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL);
492 if (!new_metadata) {
493 ret = -ENOMEM;
494 goto out;
495 }
496
497 msm_obj->metadata = new_metadata;
498 msm_obj->metadata_size = metadata_size;
499 memcpy(msm_obj->metadata, buf, metadata_size);
500
501 msm_gem_unlock(obj);
502
503 out:
504 kfree(buf);
505
506 return ret;
507 }
508
msm_ioctl_gem_info_get_metadata(struct drm_gem_object * obj,__user void * metadata,u32 * metadata_size)509 static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,
510 __user void *metadata,
511 u32 *metadata_size)
512 {
513 struct msm_gem_object *msm_obj = to_msm_bo(obj);
514 void *buf;
515 int ret, len;
516
517 if (!metadata) {
518 /*
519 * Querying the size is inherently racey, but
520 * EXT_external_objects expects the app to confirm
521 * via device and driver UUIDs that the exporter and
522 * importer versions match. All we can do from the
523 * kernel side is check the length under obj lock
524 * when userspace tries to retrieve the metadata
525 */
526 *metadata_size = msm_obj->metadata_size;
527 return 0;
528 }
529
530 ret = msm_gem_lock_interruptible(obj);
531 if (ret)
532 return ret;
533
534 /* Avoid copy_to_user() under gem obj lock: */
535 len = msm_obj->metadata_size;
536 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL);
537
538 if (!buf) {
539 msm_gem_unlock(obj);
540 return -ENOMEM;
541 }
542
543 msm_gem_unlock(obj);
544
545 if (*metadata_size < len) {
546 ret = -ETOOSMALL;
547 } else if (copy_to_user(metadata, buf, len)) {
548 ret = -EFAULT;
549 } else {
550 *metadata_size = len;
551 }
552
553 kfree(buf);
554
555 return ret;
556 }
557
msm_ioctl_gem_info(struct drm_device * dev,void * data,struct drm_file * file)558 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
559 struct drm_file *file)
560 {
561 struct drm_msm_gem_info *args = data;
562 struct drm_gem_object *obj;
563 struct msm_gem_object *msm_obj;
564 int i, ret = 0;
565
566 if (args->pad)
567 return -EINVAL;
568
569 switch (args->info) {
570 case MSM_INFO_GET_OFFSET:
571 case MSM_INFO_GET_IOVA:
572 case MSM_INFO_SET_IOVA:
573 case MSM_INFO_GET_FLAGS:
574 /* value returned as immediate, not pointer, so len==0: */
575 if (args->len)
576 return -EINVAL;
577 break;
578 case MSM_INFO_SET_NAME:
579 case MSM_INFO_GET_NAME:
580 case MSM_INFO_SET_METADATA:
581 case MSM_INFO_GET_METADATA:
582 break;
583 default:
584 return -EINVAL;
585 }
586
587 obj = drm_gem_object_lookup(file, args->handle);
588 if (!obj)
589 return -ENOENT;
590
591 msm_obj = to_msm_bo(obj);
592
593 switch (args->info) {
594 case MSM_INFO_GET_OFFSET:
595 ret = drm_gem_create_mmap_offset(obj);
596 if (ret == 0)
597 args->value = drm_vma_node_offset_addr(&obj->vma_node);
598 break;
599 case MSM_INFO_GET_IOVA:
600 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
601 break;
602 case MSM_INFO_SET_IOVA:
603 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
604 break;
605 case MSM_INFO_GET_FLAGS:
606 if (drm_gem_is_imported(obj)) {
607 ret = -EINVAL;
608 break;
609 }
610 /* Hide internal kernel-only flags: */
611 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
612 ret = 0;
613 break;
614 case MSM_INFO_SET_NAME:
615 /* length check should leave room for terminating null: */
616 if (args->len >= sizeof(msm_obj->name)) {
617 ret = -EINVAL;
618 break;
619 }
620 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
621 args->len)) {
622 msm_obj->name[0] = '\0';
623 ret = -EFAULT;
624 break;
625 }
626 msm_obj->name[args->len] = '\0';
627 for (i = 0; i < args->len; i++) {
628 if (!isprint(msm_obj->name[i])) {
629 msm_obj->name[i] = '\0';
630 break;
631 }
632 }
633 break;
634 case MSM_INFO_GET_NAME:
635 if (args->value && (args->len < strlen(msm_obj->name))) {
636 ret = -ETOOSMALL;
637 break;
638 }
639 args->len = strlen(msm_obj->name);
640 if (args->value) {
641 if (copy_to_user(u64_to_user_ptr(args->value),
642 msm_obj->name, args->len))
643 ret = -EFAULT;
644 }
645 break;
646 case MSM_INFO_SET_METADATA:
647 ret = msm_ioctl_gem_info_set_metadata(
648 obj, u64_to_user_ptr(args->value), args->len);
649 break;
650 case MSM_INFO_GET_METADATA:
651 ret = msm_ioctl_gem_info_get_metadata(
652 obj, u64_to_user_ptr(args->value), &args->len);
653 break;
654 }
655
656 drm_gem_object_put(obj);
657
658 return ret;
659 }
660
wait_fence(struct msm_gpu_submitqueue * queue,uint32_t fence_id,ktime_t timeout,uint32_t flags)661 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
662 ktime_t timeout, uint32_t flags)
663 {
664 struct dma_fence *fence;
665 int ret;
666
667 if (fence_after(fence_id, queue->last_fence)) {
668 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
669 fence_id, queue->last_fence);
670 return -EINVAL;
671 }
672
673 /*
674 * Map submitqueue scoped "seqno" (which is actually an idr key)
675 * back to underlying dma-fence
676 *
677 * The fence is removed from the fence_idr when the submit is
678 * retired, so if the fence is not found it means there is nothing
679 * to wait for
680 */
681 spin_lock(&queue->idr_lock);
682 fence = idr_find(&queue->fence_idr, fence_id);
683 if (fence)
684 fence = dma_fence_get_rcu(fence);
685 spin_unlock(&queue->idr_lock);
686
687 if (!fence)
688 return 0;
689
690 if (flags & MSM_WAIT_FENCE_BOOST)
691 dma_fence_set_deadline(fence, ktime_get());
692
693 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
694 if (ret == 0) {
695 ret = -ETIMEDOUT;
696 } else if (ret != -ERESTARTSYS) {
697 ret = 0;
698 }
699
700 dma_fence_put(fence);
701
702 return ret;
703 }
704
msm_ioctl_wait_fence(struct drm_device * dev,void * data,struct drm_file * file)705 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
706 struct drm_file *file)
707 {
708 struct msm_drm_private *priv = dev->dev_private;
709 struct drm_msm_wait_fence *args = data;
710 struct msm_gpu_submitqueue *queue;
711 int ret;
712
713 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
714 DRM_ERROR("invalid flags: %08x\n", args->flags);
715 return -EINVAL;
716 }
717
718 if (!priv->gpu)
719 return 0;
720
721 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
722 if (!queue)
723 return -ENOENT;
724
725 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
726
727 msm_submitqueue_put(queue);
728
729 return ret;
730 }
731
msm_ioctl_gem_madvise(struct drm_device * dev,void * data,struct drm_file * file)732 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
733 struct drm_file *file)
734 {
735 struct drm_msm_gem_madvise *args = data;
736 struct drm_gem_object *obj;
737 int ret;
738
739 switch (args->madv) {
740 case MSM_MADV_DONTNEED:
741 case MSM_MADV_WILLNEED:
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 obj = drm_gem_object_lookup(file, args->handle);
748 if (!obj) {
749 return -ENOENT;
750 }
751
752 ret = msm_gem_madvise(obj, args->madv);
753 if (ret >= 0) {
754 args->retained = ret;
755 ret = 0;
756 }
757
758 drm_gem_object_put(obj);
759
760 return ret;
761 }
762
763
msm_ioctl_submitqueue_new(struct drm_device * dev,void * data,struct drm_file * file)764 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
765 struct drm_file *file)
766 {
767 struct drm_msm_submitqueue *args = data;
768
769 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
770 return -EINVAL;
771
772 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
773 args->flags, &args->id);
774 }
775
msm_ioctl_submitqueue_query(struct drm_device * dev,void * data,struct drm_file * file)776 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
777 struct drm_file *file)
778 {
779 return msm_submitqueue_query(dev, file->driver_priv, data);
780 }
781
msm_ioctl_submitqueue_close(struct drm_device * dev,void * data,struct drm_file * file)782 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
783 struct drm_file *file)
784 {
785 u32 id = *(u32 *) data;
786
787 return msm_submitqueue_remove(file->driver_priv, id);
788 }
789
790 static const struct drm_ioctl_desc msm_ioctls[] = {
791 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
792 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
793 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
794 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
795 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
796 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
797 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
798 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
799 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
800 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
801 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
802 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
803 DRM_IOCTL_DEF_DRV(MSM_VM_BIND, msm_ioctl_vm_bind, DRM_RENDER_ALLOW),
804 };
805
msm_show_fdinfo(struct drm_printer * p,struct drm_file * file)806 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
807 {
808 struct drm_device *dev = file->minor->dev;
809 struct msm_drm_private *priv = dev->dev_private;
810
811 if (!priv->gpu)
812 return;
813
814 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
815
816 drm_show_memory_stats(p, file);
817 }
818
819 static const struct file_operations fops = {
820 .owner = THIS_MODULE,
821 DRM_GEM_FOPS,
822 .show_fdinfo = drm_show_fdinfo,
823 };
824
825 #define DRIVER_FEATURES_GPU ( \
826 DRIVER_GEM | \
827 DRIVER_GEM_GPUVA | \
828 DRIVER_RENDER | \
829 DRIVER_SYNCOBJ | \
830 DRIVER_SYNCOBJ_TIMELINE | \
831 0 )
832
833 #define DRIVER_FEATURES_KMS ( \
834 DRIVER_GEM | \
835 DRIVER_GEM_GPUVA | \
836 DRIVER_ATOMIC | \
837 DRIVER_MODESET | \
838 0 )
839
840 static const struct drm_driver msm_driver = {
841 .driver_features = DRIVER_FEATURES_GPU | DRIVER_FEATURES_KMS,
842 .open = msm_open,
843 .postclose = msm_postclose,
844 .dumb_create = msm_gem_dumb_create,
845 .dumb_map_offset = drm_gem_dumb_map_offset,
846 .gem_prime_import = msm_gem_prime_import,
847 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
848 #ifdef CONFIG_DEBUG_FS
849 .debugfs_init = msm_debugfs_init,
850 #endif
851 MSM_FBDEV_DRIVER_OPS,
852 .show_fdinfo = msm_show_fdinfo,
853 .ioctls = msm_ioctls,
854 .num_ioctls = ARRAY_SIZE(msm_ioctls),
855 .fops = &fops,
856 .name = "msm",
857 .desc = "MSM Snapdragon DRM",
858 .major = MSM_VERSION_MAJOR,
859 .minor = MSM_VERSION_MINOR,
860 .patchlevel = MSM_VERSION_PATCHLEVEL,
861 };
862
863 static const struct drm_driver msm_kms_driver = {
864 .driver_features = DRIVER_FEATURES_KMS,
865 .open = msm_open,
866 .postclose = msm_postclose,
867 .dumb_create = msm_gem_dumb_create,
868 .dumb_map_offset = drm_gem_dumb_map_offset,
869 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
870 #ifdef CONFIG_DEBUG_FS
871 .debugfs_init = msm_debugfs_init,
872 #endif
873 MSM_FBDEV_DRIVER_OPS,
874 .show_fdinfo = msm_show_fdinfo,
875 .fops = &fops,
876 .name = "msm-kms",
877 .desc = "MSM Snapdragon DRM",
878 .major = MSM_VERSION_MAJOR,
879 .minor = MSM_VERSION_MINOR,
880 .patchlevel = MSM_VERSION_PATCHLEVEL,
881 };
882
883 static const struct drm_driver msm_gpu_driver = {
884 .driver_features = DRIVER_FEATURES_GPU,
885 .open = msm_open,
886 .postclose = msm_postclose,
887 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
888 #ifdef CONFIG_DEBUG_FS
889 .debugfs_init = msm_debugfs_init,
890 #endif
891 .show_fdinfo = msm_show_fdinfo,
892 .ioctls = msm_ioctls,
893 .num_ioctls = ARRAY_SIZE(msm_ioctls),
894 .fops = &fops,
895 .name = "msm",
896 .desc = "MSM Snapdragon DRM",
897 .major = MSM_VERSION_MAJOR,
898 .minor = MSM_VERSION_MINOR,
899 .patchlevel = MSM_VERSION_PATCHLEVEL,
900 };
901
902 /*
903 * Componentized driver support:
904 */
905
906 /*
907 * Identify what components need to be added by parsing what remote-endpoints
908 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
909 * is no external component that we need to add since LVDS is within MDP4
910 * itself.
911 */
add_mdp_components(struct device * master_dev,struct component_match ** matchptr)912 static int add_mdp_components(struct device *master_dev,
913 struct component_match **matchptr)
914 {
915 struct device_node *np = master_dev->of_node;
916 struct device_node *ep_node;
917
918 for_each_endpoint_of_node(np, ep_node) {
919 struct device_node *intf;
920 struct of_endpoint ep;
921 int ret;
922
923 ret = of_graph_parse_endpoint(ep_node, &ep);
924 if (ret) {
925 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
926 of_node_put(ep_node);
927 return ret;
928 }
929
930 /*
931 * The LCDC/LVDS port on MDP4 is a speacial case where the
932 * remote-endpoint isn't a component that we need to add
933 */
934 if (of_device_is_compatible(np, "qcom,mdp4") &&
935 ep.port == 0)
936 continue;
937
938 /*
939 * It's okay if some of the ports don't have a remote endpoint
940 * specified. It just means that the port isn't connected to
941 * any external interface.
942 */
943 intf = of_graph_get_remote_port_parent(ep_node);
944 if (!intf)
945 continue;
946
947 if (of_device_is_available(intf))
948 drm_of_component_match_add(master_dev, matchptr,
949 component_compare_of, intf);
950
951 of_node_put(intf);
952 }
953
954 return 0;
955 }
956
957 #if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)958 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
959 {
960 /* If just a single driver is enabled, use it no matter what */
961 return true;
962 }
963 #else
964
965 static bool prefer_mdp5 = true;
966 MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
967 module_param(prefer_mdp5, bool, 0444);
968
969 /* list all platforms that have been migrated from mdp5 to dpu driver */
970 static const char *const msm_mdp5_dpu_migrated[] = {
971 /* there never was qcom,msm8998-mdp5 */
972 "qcom,sdm630-mdp5",
973 "qcom,sdm660-mdp5",
974 NULL
975 };
976
977 /* list all platforms supported by both mdp5 and dpu drivers */
978 static const char *const msm_mdp5_dpu_migration[] = {
979 "qcom,msm8917-mdp5",
980 "qcom,msm8937-mdp5",
981 "qcom,msm8953-mdp5",
982 "qcom,msm8996-mdp5",
983 NULL,
984 };
985
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)986 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
987 {
988 /* If it is not an MDP5 device, use DPU */
989 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
990 return dpu_driver;
991
992 /* If it is no longer supported by MDP5, use DPU */
993 if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated))
994 return dpu_driver;
995
996 /* If it is not in the migration list, use MDP5 */
997 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
998 return !dpu_driver;
999
1000 return prefer_mdp5 ? !dpu_driver : dpu_driver;
1001 }
1002 #endif
1003
1004 /*
1005 * We don't know what's the best binding to link the gpu with the drm device.
1006 * Fow now, we just hunt for all the possible gpus that we support, and add them
1007 * as components.
1008 */
1009 static const struct of_device_id msm_gpu_match[] = {
1010 { .compatible = "qcom,adreno" },
1011 { .compatible = "qcom,adreno-3xx" },
1012 { .compatible = "amd,imageon" },
1013 { .compatible = "qcom,kgsl-3d0" },
1014 { },
1015 };
1016
add_gpu_components(struct device * dev,struct component_match ** matchptr)1017 static int add_gpu_components(struct device *dev,
1018 struct component_match **matchptr)
1019 {
1020 struct device_node *np;
1021
1022 np = of_find_matching_node(NULL, msm_gpu_match);
1023 if (!np)
1024 return 0;
1025
1026 if (of_device_is_available(np) && adreno_has_gpu(np))
1027 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1028
1029 of_node_put(np);
1030
1031 return 0;
1032 }
1033
msm_drm_bind(struct device * dev)1034 static int msm_drm_bind(struct device *dev)
1035 {
1036 return msm_drm_init(dev,
1037 msm_gpu_no_components() ?
1038 &msm_kms_driver :
1039 &msm_driver,
1040 NULL);
1041 }
1042
msm_drm_unbind(struct device * dev)1043 static void msm_drm_unbind(struct device *dev)
1044 {
1045 msm_drm_uninit(dev, NULL);
1046 }
1047
1048 const struct component_master_ops msm_drm_ops = {
1049 .bind = msm_drm_bind,
1050 .unbind = msm_drm_unbind,
1051 };
1052
msm_drv_probe(struct device * master_dev,int (* kms_init)(struct drm_device * dev),struct msm_kms * kms)1053 int msm_drv_probe(struct device *master_dev,
1054 int (*kms_init)(struct drm_device *dev),
1055 struct msm_kms *kms)
1056 {
1057 struct msm_drm_private *priv;
1058 struct component_match *match = NULL;
1059 int ret;
1060
1061 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1062 if (!priv)
1063 return -ENOMEM;
1064
1065 priv->kms = kms;
1066 priv->kms_init = kms_init;
1067 dev_set_drvdata(master_dev, priv);
1068
1069 /* Add mdp components if we have KMS. */
1070 if (kms_init) {
1071 ret = add_mdp_components(master_dev, &match);
1072 if (ret)
1073 return ret;
1074 }
1075
1076 if (!msm_gpu_no_components()) {
1077 ret = add_gpu_components(master_dev, &match);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 /* on all devices that I am aware of, iommu's which can map
1083 * any address the cpu can see are used:
1084 */
1085 ret = dma_set_mask_and_coherent(master_dev, ~0);
1086 if (ret)
1087 return ret;
1088
1089 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1090 if (ret)
1091 return ret;
1092
1093 return 0;
1094 }
1095
msm_gpu_probe(struct platform_device * pdev,const struct component_ops * ops)1096 int msm_gpu_probe(struct platform_device *pdev,
1097 const struct component_ops *ops)
1098 {
1099 struct msm_drm_private *priv;
1100 int ret;
1101
1102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1103 if (!priv)
1104 return -ENOMEM;
1105
1106 platform_set_drvdata(pdev, priv);
1107
1108 /* on all devices that I am aware of, iommu's which can map
1109 * any address the cpu can see are used:
1110 */
1111 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1112 if (ret)
1113 return ret;
1114
1115 return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops);
1116 }
1117
msm_gpu_remove(struct platform_device * pdev,const struct component_ops * ops)1118 void msm_gpu_remove(struct platform_device *pdev,
1119 const struct component_ops *ops)
1120 {
1121 msm_drm_uninit(&pdev->dev, ops);
1122 }
1123
msm_drm_register(void)1124 static int __init msm_drm_register(void)
1125 {
1126 if (!modeset)
1127 return -EINVAL;
1128
1129 DBG("init");
1130 msm_mdp_register();
1131 msm_dpu_register();
1132 msm_dsi_register();
1133 msm_hdmi_register();
1134 msm_dp_register();
1135 adreno_register();
1136 msm_mdp4_register();
1137 msm_mdss_register();
1138
1139 return 0;
1140 }
1141
msm_drm_unregister(void)1142 static void __exit msm_drm_unregister(void)
1143 {
1144 DBG("fini");
1145 msm_mdss_unregister();
1146 msm_mdp4_unregister();
1147 msm_dp_unregister();
1148 msm_hdmi_unregister();
1149 adreno_unregister();
1150 msm_dsi_unregister();
1151 msm_mdp_unregister();
1152 msm_dpu_unregister();
1153 }
1154
1155 module_init(msm_drm_register);
1156 module_exit(msm_drm_unregister);
1157
1158 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1159 MODULE_DESCRIPTION("MSM DRM Driver");
1160 MODULE_LICENSE("GPL");
1161