1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83TD510 PHY 3 * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/ethtool_netlink.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/phy.h> 11 12 #define DP83TD510E_PHY_ID 0x20000181 13 14 /* MDIO_MMD_VEND2 registers */ 15 #define DP83TD510E_PHY_STS 0x10 16 /* Bit 7 - mii_interrupt, active high. Clears on read. 17 * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending. 18 * This differs from the DP83TD510E datasheet (2020) which states this bit 19 * clears on write 0. 20 */ 21 #define DP83TD510E_STS_MII_INT BIT(7) 22 #define DP83TD510E_LINK_STATUS BIT(0) 23 24 #define DP83TD510E_GEN_CFG 0x11 25 #define DP83TD510E_GENCFG_INT_POLARITY BIT(3) 26 #define DP83TD510E_GENCFG_INT_EN BIT(1) 27 #define DP83TD510E_GENCFG_INT_OE BIT(0) 28 29 #define DP83TD510E_INTERRUPT_REG_1 0x12 30 #define DP83TD510E_INT1_LINK BIT(13) 31 #define DP83TD510E_INT1_LINK_EN BIT(5) 32 33 #define DP83TD510E_RCSR 0x17 34 #define DP83TD510E_RMII_MODE_EN BIT(5) 35 #define DP83TD510E_RGMII_MODE_EN BIT(9) 36 #define DP83TD510E_TX_CLK_SHIFT BIT(11) 37 #define DP83TD510E_RX_CLK_SHIFT BIT(12) 38 39 #define DP83TD510E_CTRL 0x1f 40 #define DP83TD510E_CTRL_HW_RESET BIT(15) 41 #define DP83TD510E_CTRL_SW_RESET BIT(14) 42 43 /* 44 * DP83TD510E_PKT_STAT_x registers correspond to similarly named registers 45 * in the datasheet (PKT_STAT_1 through PKT_STAT_6). These registers store 46 * 32-bit or 16-bit counters for TX and RX statistics and must be read in 47 * sequence to ensure the counters are cleared correctly. 48 * 49 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0]. 50 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16]. 51 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count. 52 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0]. 53 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16]. 54 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count. 55 * 56 * Keeping the register names as defined in the datasheet helps maintain 57 * clarity and alignment with the documentation. 58 */ 59 #define DP83TD510E_PKT_STAT_1 0x12b 60 #define DP83TD510E_PKT_STAT_2 0x12c 61 #define DP83TD510E_PKT_STAT_3 0x12d 62 #define DP83TD510E_PKT_STAT_4 0x12e 63 #define DP83TD510E_PKT_STAT_5 0x12f 64 #define DP83TD510E_PKT_STAT_6 0x130 65 66 #define DP83TD510E_AN_STAT_1 0x60c 67 #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15) 68 69 #define DP83TD510E_MSE_DETECT 0xa85 70 #define DP83TD510E_MSE_MAX U16_MAX 71 72 #define DP83TD510_SQI_MAX 7 73 74 /* Register values are converted to SNR(dB) as suggested by 75 * "Application Report - DP83TD510E Cable Diagnostics Toolkit": 76 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB. 77 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic 78 * features for 100BASE-T1 automotive Ethernet PHYs" 79 */ 80 static const u16 dp83td510_mse_sqi_map[] = { 81 0x0569, /* < 18dB */ 82 0x044c, /* 18dB =< SNR < 19dB */ 83 0x0369, /* 19dB =< SNR < 20dB */ 84 0x02b6, /* 20dB =< SNR < 21dB */ 85 0x0227, /* 21dB =< SNR < 22dB */ 86 0x01b6, /* 22dB =< SNR < 23dB */ 87 0x015b, /* 23dB =< SNR < 24dB */ 88 0x0000 /* 24dB =< SNR */ 89 }; 90 91 struct dp83td510_stats { 92 u64 tx_pkt_cnt; 93 u64 tx_err_pkt_cnt; 94 u64 rx_pkt_cnt; 95 u64 rx_err_pkt_cnt; 96 }; 97 98 struct dp83td510_priv { 99 bool alcd_test_active; 100 struct dp83td510_stats stats; 101 }; 102 103 /* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY 104 * 105 * I assume that this PHY is using a variation of Spread Spectrum Time Domain 106 * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs. 107 * Here are the following observations which likely confirm this: 108 * - The DP83TD510 PHY transmits a modulated signal of configurable length 109 * (default 16000 µs) instead of a single pulse pattern, which is typical 110 * for traditional TDR. 111 * - The pulse observed on the wire, triggered by the HW RESET register, is not 112 * part of the cable testing process. 113 * 114 * I assume that SSTDR seems to be a logical choice for the 10BaseT1L 115 * environment due to improved noise resistance, making it suitable for 116 * environments with significant electrical noise, such as long 10BaseT1L cable 117 * runs. 118 * 119 * Configuration Variables: 120 * The SSTDR variation used in this PHY involves more configuration variables 121 * that can dramatically affect the functionality and precision of cable 122 * testing. Since most of these configuration options are either not well 123 * documented or documented with minimal details, the following sections 124 * describe my understanding and observations of these variables and their 125 * impact on TDR functionality. 126 * 127 * Timeline: 128 * ,<--cfg_pre_silence_time 129 * | ,<-SSTDR Modulated Transmission 130 * | | ,<--cfg_post_silence_time 131 * | | | ,<--Force Link Mode 132 * |<--'-->|<-------'------->|<--'-->|<--------'------->| 133 * 134 * - cfg_pre_silence_time: Optional silence time before TDR transmission starts. 135 * - SSTDR Modulated Transmission: Transmission duration configured by 136 * cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type. 137 * - cfg_post_silence_time: Silence time after TDR transmission. 138 * - Force Link Mode: If nothing is configured after cfg_post_silence_time, 139 * the PHY continues in force link mode without autonegotiation. 140 */ 141 142 #define DP83TD510E_TDR_CFG 0x1e 143 #define DP83TD510E_TDR_START BIT(15) 144 #define DP83TD510E_TDR_DONE BIT(1) 145 #define DP83TD510E_TDR_FAIL BIT(0) 146 147 #define DP83TD510E_TDR_CFG1 0x300 148 /* cfg_tdr_tx_type: Transmit voltage level for TDR. 149 * 0 = 1V, 1 = 2.4V 150 * Note: Using different voltage levels may not work 151 * in all configuration variations. For example, setting 152 * 2.4V may give different cable length measurements. 153 * Other settings may be needed to make it work properly. 154 */ 155 #define DP83TD510E_TDR_TX_TYPE BIT(12) 156 #define DP83TD510E_TDR_TX_TYPE_1V 0 157 #define DP83TD510E_TDR_TX_TYPE_2_4V 1 158 /* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode 159 * for the TDR will proceed with forced link state after this time. For Linux 160 * it is better to set max value to avoid false link state detection. 161 */ 162 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2) 163 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS 0 164 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS 1 165 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS 2 166 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS 3 167 /* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to 168 * settle down all pulses and reflections. Since for 10BASE-T1L we have 169 * maximum 2000m cable length, we can set it to 1ms. 170 */ 171 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0) 172 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS 0 173 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS 1 174 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS 2 175 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS 3 176 177 #define DP83TD510E_TDR_CFG2 0x301 178 #define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8) 179 #define DP83TD510E_TDR_END_TAP_INDEX_1_DEF 36 180 #define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0) 181 #define DP83TD510E_TDR_START_TAP_INDEX_1_DEF 4 182 183 #define DP83TD510E_TDR_CFG3 0x302 184 /* cfg_tdr_tx_duration: Duration of the TDR transmission in microseconds. 185 * This value sets the duration of the modulated signal used for TDR 186 * measurements. 187 * - Default: 16000 µs 188 * - Observation: A minimum duration of 6000 µs is recommended to ensure 189 * accurate detection of cable faults. Durations shorter than 6000 µs may 190 * result in incomplete data, especially for shorter cables (e.g., 20 meters), 191 * leading to false "OK" results. Longer durations (e.g., 6000 µs or more) 192 * provide better accuracy, particularly for detecting open circuits. 193 */ 194 #define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0) 195 #define DP83TD510E_TDR_TX_DURATION_US_DEF 16000 196 197 #define DP83TD510E_TDR_FAULT_CFG1 0x303 198 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8) 199 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF 4 200 #define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0) 201 #define DP83TD510E_TDR_FLT_INIT_1_DEF 62 202 203 #define DP83TD510E_TDR_FAULT_STAT 0x30c 204 #define DP83TD510E_TDR_PEAK_DETECT BIT(11) 205 #define DP83TD510E_TDR_PEAK_SIGN BIT(10) 206 #define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0) 207 208 /* Not documented registers and values but recommended according to 209 * "DP83TD510E Cable Diagnostics Toolkit revC" 210 */ 211 #define DP83TD510E_UNKN_030E 0x30e 212 #define DP83TD510E_030E_VAL 0x2520 213 214 #define DP83TD510E_LEDS_CFG_1 0x460 215 #define DP83TD510E_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4)) 216 #define DP83TD510E_LED_FN_MASK(idx) (0xf << ((idx) * 4)) 217 /* link OK */ 218 #define DP83TD510E_LED_MODE_LINK_OK 0x0 219 /* TX/RX activity */ 220 #define DP83TD510E_LED_MODE_TX_RX_ACTIVITY 0x1 221 /* TX activity */ 222 #define DP83TD510E_LED_MODE_TX_ACTIVITY 0x2 223 /* RX activity */ 224 #define DP83TD510E_LED_MODE_RX_ACTIVITY 0x3 225 /* LR */ 226 #define DP83TD510E_LED_MODE_LR 0x4 227 /* SR */ 228 #define DP83TD510E_LED_MODE_SR 0x5 229 /* LED SPEED: High for 10Base-T */ 230 #define DP83TD510E_LED_MODE_LED_SPEED 0x6 231 /* Duplex mode */ 232 #define DP83TD510E_LED_MODE_DUPLEX 0x7 233 /* link + blink on activity with stretch option */ 234 #define DP83TD510E_LED_MODE_LINK_BLINK 0x8 235 /* blink on activity with stretch option */ 236 #define DP83TD510E_LED_MODE_BLINK_ACTIVITY 0x9 237 /* blink on tx activity with stretch option */ 238 #define DP83TD510E_LED_MODE_BLINK_TX 0xa 239 /* blink on rx activity with stretch option */ 240 #define DP83TD510E_LED_MODE_BLINK_RX 0xb 241 /* link_lost */ 242 #define DP83TD510E_LED_MODE_LINK_LOST 0xc 243 /* PRBS error: toggles on error */ 244 #define DP83TD510E_LED_MODE_PRBS_ERROR 0xd 245 /* XMII TX/RX Error with stretch option */ 246 #define DP83TD510E_LED_MODE_XMII_ERR 0xe 247 248 #define DP83TD510E_LED_COUNT 4 249 250 #define DP83TD510E_LEDS_CFG_2 0x469 251 #define DP83TD510E_LED_POLARITY(idx) BIT((idx) * 4 + 2) 252 #define DP83TD510E_LED_DRV_VAL(idx) BIT((idx) * 4 + 1) 253 #define DP83TD510E_LED_DRV_EN(idx) BIT((idx) * 4) 254 255 #define DP83TD510E_ALCD_STAT 0xa9f 256 #define DP83TD510E_ALCD_COMPLETE BIT(15) 257 #define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0) 258 259 static int dp83td510_get_mse_capability(struct phy_device *phydev, 260 struct phy_mse_capability *cap) 261 { 262 /* DP83TD510E documents only a single (average) MSE register 263 * (used to derive SQI); no peak or worst-peak counters are 264 * described. Advertise only PHY_MSE_CAP_AVG. 265 */ 266 cap->supported_caps = PHY_MSE_CAP_AVG; 267 /* 10BASE-T1L is a single-pair medium, so there are no B/C/D channels. 268 * We still advertise PHY_MSE_CAP_CHANNEL_A to indicate that the PHY 269 * can attribute the measurement to a specific pair (the only one), 270 * rather than exposing it only as a link-aggregate. 271 * 272 * Rationale: 273 * - Keeps the ethtool MSE_GET selection logic consistent: per-channel 274 * (A/B/C/D) is preferred over WORST/LINK, so userspace receives a 275 * CHANNEL_A nest instead of LINK. 276 * - Signals to tools that "per-pair" data is available (even if there's 277 * just one pair), avoiding the impression that only aggregate values 278 * are supported. 279 * - Remains compatible with multi-pair PHYs and uniform UI handling. 280 * 281 * Note: WORST and other channels are not advertised on 10BASE-T1L. 282 */ 283 cap->supported_caps |= PHY_MSE_CHANNEL_A | PHY_MSE_CAP_LINK; 284 cap->max_average_mse = DP83TD510E_MSE_MAX; 285 286 /* The datasheet does not specify the refresh rate or symbol count, 287 * but based on similar PHYs and standards, we can assume a common 288 * value. For 10BASE-T1L, the symbol rate is 7.5 MBd. A common 289 * diagnostic interval is around 1ms. 290 * 7.5e6 symbols/sec * 0.001 sec = 7500 symbols. 291 */ 292 cap->refresh_rate_ps = 1000000000; /* 1 ms */ 293 cap->num_symbols = 7500; 294 295 return 0; 296 } 297 298 static int dp83td510_get_mse_snapshot(struct phy_device *phydev, 299 enum phy_mse_channel channel, 300 struct phy_mse_snapshot *snapshot) 301 { 302 int ret; 303 304 if (channel != PHY_MSE_CHANNEL_LINK && 305 channel != PHY_MSE_CHANNEL_A) 306 return -EOPNOTSUPP; 307 308 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); 309 if (ret < 0) 310 return ret; 311 312 snapshot->average_mse = ret; 313 314 return 0; 315 } 316 317 static int dp83td510_led_brightness_set(struct phy_device *phydev, u8 index, 318 enum led_brightness brightness) 319 { 320 u32 val; 321 322 if (index >= DP83TD510E_LED_COUNT) 323 return -EINVAL; 324 325 val = DP83TD510E_LED_DRV_EN(index); 326 327 if (brightness) 328 val |= DP83TD510E_LED_DRV_VAL(index); 329 330 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, 331 DP83TD510E_LED_DRV_VAL(index) | 332 DP83TD510E_LED_DRV_EN(index), val); 333 } 334 335 static int dp83td510_led_mode(u8 index, unsigned long rules) 336 { 337 if (index >= DP83TD510E_LED_COUNT) 338 return -EINVAL; 339 340 switch (rules) { 341 case BIT(TRIGGER_NETDEV_LINK): 342 return DP83TD510E_LED_MODE_LINK_OK; 343 case BIT(TRIGGER_NETDEV_LINK_10): 344 return DP83TD510E_LED_MODE_LED_SPEED; 345 case BIT(TRIGGER_NETDEV_FULL_DUPLEX): 346 return DP83TD510E_LED_MODE_DUPLEX; 347 case BIT(TRIGGER_NETDEV_TX): 348 return DP83TD510E_LED_MODE_TX_ACTIVITY; 349 case BIT(TRIGGER_NETDEV_RX): 350 return DP83TD510E_LED_MODE_RX_ACTIVITY; 351 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 352 return DP83TD510E_LED_MODE_TX_RX_ACTIVITY; 353 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | 354 BIT(TRIGGER_NETDEV_RX): 355 return DP83TD510E_LED_MODE_LINK_BLINK; 356 default: 357 return -EOPNOTSUPP; 358 } 359 } 360 361 static int dp83td510_led_hw_is_supported(struct phy_device *phydev, u8 index, 362 unsigned long rules) 363 { 364 int ret; 365 366 ret = dp83td510_led_mode(index, rules); 367 if (ret < 0) 368 return ret; 369 370 return 0; 371 } 372 373 static int dp83td510_led_hw_control_set(struct phy_device *phydev, u8 index, 374 unsigned long rules) 375 { 376 int mode, ret; 377 378 mode = dp83td510_led_mode(index, rules); 379 if (mode < 0) 380 return mode; 381 382 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1, 383 DP83TD510E_LED_FN_MASK(index), 384 DP83TD510E_LED_FN(index, mode)); 385 if (ret) 386 return ret; 387 388 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, 389 DP83TD510E_LED_DRV_EN(index), 0); 390 } 391 392 static int dp83td510_led_hw_control_get(struct phy_device *phydev, 393 u8 index, unsigned long *rules) 394 { 395 int val; 396 397 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1); 398 if (val < 0) 399 return val; 400 401 val &= DP83TD510E_LED_FN_MASK(index); 402 val >>= index * 4; 403 404 switch (val) { 405 case DP83TD510E_LED_MODE_LINK_OK: 406 *rules = BIT(TRIGGER_NETDEV_LINK); 407 break; 408 /* LED mode: LED SPEED (10BaseT1L indicator) */ 409 case DP83TD510E_LED_MODE_LED_SPEED: 410 *rules = BIT(TRIGGER_NETDEV_LINK_10); 411 break; 412 case DP83TD510E_LED_MODE_DUPLEX: 413 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX); 414 break; 415 case DP83TD510E_LED_MODE_TX_ACTIVITY: 416 *rules = BIT(TRIGGER_NETDEV_TX); 417 break; 418 case DP83TD510E_LED_MODE_RX_ACTIVITY: 419 *rules = BIT(TRIGGER_NETDEV_RX); 420 break; 421 case DP83TD510E_LED_MODE_TX_RX_ACTIVITY: 422 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); 423 break; 424 case DP83TD510E_LED_MODE_LINK_BLINK: 425 *rules = BIT(TRIGGER_NETDEV_LINK) | 426 BIT(TRIGGER_NETDEV_TX) | 427 BIT(TRIGGER_NETDEV_RX); 428 break; 429 default: 430 *rules = 0; 431 break; 432 } 433 434 return 0; 435 } 436 437 static int dp83td510_led_polarity_set(struct phy_device *phydev, int index, 438 unsigned long modes) 439 { 440 u16 polarity = DP83TD510E_LED_POLARITY(index); 441 u32 mode; 442 443 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 444 switch (mode) { 445 case PHY_LED_ACTIVE_LOW: 446 polarity = 0; 447 break; 448 case PHY_LED_ACTIVE_HIGH: 449 polarity = DP83TD510E_LED_POLARITY(index); 450 break; 451 default: 452 return -EINVAL; 453 } 454 } 455 456 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2, 457 DP83TD510E_LED_POLARITY(index), polarity); 458 } 459 460 /** 461 * dp83td510_update_stats - Update the PHY statistics for the DP83TD510 PHY. 462 * @phydev: Pointer to the phy_device structure. 463 * 464 * The function reads the PHY statistics registers and updates the statistics 465 * structure. 466 * 467 * Returns: 0 on success or a negative error code on failure. 468 */ 469 static int dp83td510_update_stats(struct phy_device *phydev) 470 { 471 struct dp83td510_priv *priv = phydev->priv; 472 u32 count; 473 int ret; 474 475 /* The DP83TD510E_PKT_STAT registers are divided into two groups: 476 * - Group 1 (TX stats): DP83TD510E_PKT_STAT_1 to DP83TD510E_PKT_STAT_3 477 * - Group 2 (RX stats): DP83TD510E_PKT_STAT_4 to DP83TD510E_PKT_STAT_6 478 * 479 * Registers in each group are cleared only after reading them in a 480 * plain sequence (e.g., 1, 2, 3 for Group 1 or 4, 5, 6 for Group 2). 481 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will 482 * prevent the group from being cleared. Additionally, the counters 483 * for a group are frozen as soon as the first register in that group 484 * is accessed. 485 */ 486 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_1); 487 if (ret < 0) 488 return ret; 489 /* tx_pkt_cnt_15_0 */ 490 count = ret; 491 492 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_2); 493 if (ret < 0) 494 return ret; 495 /* tx_pkt_cnt_31_16 */ 496 count |= ret << 16; 497 priv->stats.tx_pkt_cnt += count; 498 499 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_3); 500 if (ret < 0) 501 return ret; 502 /* tx_err_pkt_cnt */ 503 priv->stats.tx_err_pkt_cnt += ret; 504 505 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_4); 506 if (ret < 0) 507 return ret; 508 /* rx_pkt_cnt_15_0 */ 509 count = ret; 510 511 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_5); 512 if (ret < 0) 513 return ret; 514 /* rx_pkt_cnt_31_16 */ 515 count |= ret << 16; 516 priv->stats.rx_pkt_cnt += count; 517 518 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_6); 519 if (ret < 0) 520 return ret; 521 /* rx_err_pkt_cnt */ 522 priv->stats.rx_err_pkt_cnt += ret; 523 524 return 0; 525 } 526 527 static void dp83td510_get_phy_stats(struct phy_device *phydev, 528 struct ethtool_eth_phy_stats *eth_stats, 529 struct ethtool_phy_stats *stats) 530 { 531 struct dp83td510_priv *priv = phydev->priv; 532 533 stats->tx_packets = priv->stats.tx_pkt_cnt; 534 stats->tx_errors = priv->stats.tx_err_pkt_cnt; 535 stats->rx_packets = priv->stats.rx_pkt_cnt; 536 stats->rx_errors = priv->stats.rx_err_pkt_cnt; 537 } 538 539 static int dp83td510_config_intr(struct phy_device *phydev) 540 { 541 int ret; 542 543 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 544 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 545 DP83TD510E_INTERRUPT_REG_1, 546 DP83TD510E_INT1_LINK_EN); 547 if (ret) 548 return ret; 549 550 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 551 DP83TD510E_GEN_CFG, 552 DP83TD510E_GENCFG_INT_POLARITY | 553 DP83TD510E_GENCFG_INT_EN | 554 DP83TD510E_GENCFG_INT_OE); 555 } else { 556 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 557 DP83TD510E_INTERRUPT_REG_1, 0x0); 558 if (ret) 559 return ret; 560 561 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 562 DP83TD510E_GEN_CFG, 563 DP83TD510E_GENCFG_INT_EN); 564 if (ret) 565 return ret; 566 } 567 568 return ret; 569 } 570 571 static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev) 572 { 573 int ret; 574 575 /* Read the current enabled interrupts */ 576 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); 577 if (ret < 0) { 578 phy_error(phydev); 579 return IRQ_NONE; 580 } else if (!(ret & DP83TD510E_INT1_LINK_EN) || 581 !(ret & DP83TD510E_INT1_LINK)) { 582 return IRQ_NONE; 583 } 584 585 phy_trigger_machine(phydev); 586 587 return IRQ_HANDLED; 588 } 589 590 static int dp83td510_read_status(struct phy_device *phydev) 591 { 592 u16 phy_sts; 593 int ret; 594 595 phydev->speed = SPEED_UNKNOWN; 596 phydev->duplex = DUPLEX_UNKNOWN; 597 phydev->pause = 0; 598 phydev->asym_pause = 0; 599 linkmode_zero(phydev->lp_advertising); 600 601 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS); 602 603 phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS); 604 if (phydev->link) { 605 /* This PHY supports only one link mode: 10BaseT1L_Full */ 606 phydev->duplex = DUPLEX_FULL; 607 phydev->speed = SPEED_10; 608 609 if (phydev->autoneg == AUTONEG_ENABLE) { 610 ret = genphy_c45_read_lpa(phydev); 611 if (ret) 612 return ret; 613 614 phy_resolve_aneg_linkmode(phydev); 615 } 616 } 617 618 if (phydev->autoneg == AUTONEG_ENABLE) { 619 ret = genphy_c45_baset1_read_status(phydev); 620 if (ret < 0) 621 return ret; 622 623 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 624 DP83TD510E_AN_STAT_1); 625 if (ret < 0) 626 return ret; 627 628 if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL) 629 phydev->master_slave_state = MASTER_SLAVE_STATE_ERR; 630 } else { 631 return genphy_c45_pma_baset1_read_master_slave(phydev); 632 } 633 634 return 0; 635 } 636 637 static int dp83td510_config_aneg(struct phy_device *phydev) 638 { 639 bool changed = false; 640 int ret; 641 642 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 643 if (ret < 0) 644 return ret; 645 646 if (phydev->autoneg == AUTONEG_DISABLE) 647 return genphy_c45_an_disable_aneg(phydev); 648 649 ret = genphy_c45_an_config_aneg(phydev); 650 if (ret < 0) 651 return ret; 652 if (ret > 0) 653 changed = true; 654 655 return genphy_c45_check_and_restart_aneg(phydev, changed); 656 } 657 658 static bool dp83td510_config_rgmii_rx_delay(struct phy_device *phydev) 659 { 660 return phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 661 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID; 662 } 663 664 static bool dp83td510_config_rgmii_tx_delay(struct phy_device *phydev) 665 { 666 return phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 667 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID; 668 } 669 670 static int dp83td510_config_init(struct phy_device *phydev) 671 { 672 int rgmii_delay = 0; 673 bool rx_int_delay; 674 bool tx_int_delay; 675 int ret; 676 677 if (phy_interface_is_rgmii(phydev)) { 678 rx_int_delay = dp83td510_config_rgmii_rx_delay(phydev); 679 if (rx_int_delay) 680 rgmii_delay |= DP83TD510E_RX_CLK_SHIFT; 681 682 tx_int_delay = dp83td510_config_rgmii_tx_delay(phydev); 683 684 if (tx_int_delay) 685 rgmii_delay |= DP83TD510E_TX_CLK_SHIFT; 686 687 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR, 688 DP83TD510E_RX_CLK_SHIFT | 689 DP83TD510E_TX_CLK_SHIFT, 690 rgmii_delay); 691 if (ret) 692 return ret; 693 694 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 695 DP83TD510E_RCSR, DP83TD510E_RGMII_MODE_EN); 696 697 if (ret) 698 return ret; 699 700 } else if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 701 /* set RMII_MODE_EN, clear RGMII_MODE_EN. We need to clear RGMII 702 * here because otherwise, RMII/MII configuration would be 703 * ignored as RGMII would be selected. 704 */ 705 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR, 706 DP83TD510E_RMII_MODE_EN | 707 DP83TD510E_RGMII_MODE_EN, 708 DP83TD510E_RMII_MODE_EN); 709 if (ret) 710 return ret; 711 } else { 712 /* may be MII, which is supported, or something else. Just 713 * return success to keep the old behavior and not break 714 * anything. Configuration may have been done by straps so 715 * it's better to not touch it. 716 */ 717 ret = 0; 718 } 719 720 return ret; 721 } 722 723 static int dp83td510_get_sqi(struct phy_device *phydev) 724 { 725 int sqi, ret; 726 u16 mse_val; 727 728 if (!phydev->link) 729 return 0; 730 731 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); 732 if (ret < 0) 733 return ret; 734 735 mse_val = 0xFFFF & ret; 736 for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) { 737 if (mse_val >= dp83td510_mse_sqi_map[sqi]) 738 return sqi; 739 } 740 741 return -EINVAL; 742 } 743 744 static int dp83td510_get_sqi_max(struct phy_device *phydev) 745 { 746 return DP83TD510_SQI_MAX; 747 } 748 749 /** 750 * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY. 751 * @phydev: Pointer to the phy_device structure. 752 * 753 * This sequence is implemented according to the "Application Note DP83TD510E 754 * Cable Diagnostics Toolkit revC". 755 * 756 * Returns: 0 on success, a negative error code on failure. 757 */ 758 static int dp83td510_cable_test_start(struct phy_device *phydev) 759 { 760 struct dp83td510_priv *priv = phydev->priv; 761 int ret; 762 763 /* If link partner is active, we won't be able to use TDR, since 764 * we can't force link partner to be silent. The autonegotiation 765 * pulses will be too frequent and the TDR sequence will be 766 * too long. So, TDR will always fail. Since the link is established 767 * we already know that the cable is working, so we can get some 768 * extra information line the cable length using ALCD. 769 */ 770 if (phydev->link) { 771 priv->alcd_test_active = true; 772 return 0; 773 } 774 775 priv->alcd_test_active = false; 776 777 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, 778 DP83TD510E_CTRL_HW_RESET); 779 if (ret) 780 return ret; 781 782 ret = genphy_c45_an_disable_aneg(phydev); 783 if (ret) 784 return ret; 785 786 /* Force master mode */ 787 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 788 MDIO_PMA_PMD_BT1_CTRL_CFG_MST); 789 if (ret) 790 return ret; 791 792 /* There is no official recommendation for this register, but it is 793 * better to use 1V for TDR since other values seems to be optimized 794 * for this amplitude. Except of amplitude, it is better to configure 795 * pre TDR silence time to 10ms to avoid false reflections (value 0 796 * seems to be too short, otherwise we need to implement own silence 797 * time). Also, post TDR silence time should be set to 1000ms to avoid 798 * false link state detection, it fits to the polling time of the 799 * PHY framework. The idea is to wait until 800 * dp83td510_cable_test_get_status() will be called and reconfigure 801 * the PHY to the default state within the post silence time window. 802 */ 803 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1, 804 DP83TD510E_TDR_TX_TYPE | 805 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME | 806 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME, 807 DP83TD510E_TDR_TX_TYPE_1V | 808 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS | 809 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS); 810 if (ret) 811 return ret; 812 813 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, 814 FIELD_PREP(DP83TD510E_TDR_END_TAP_INDEX_1, 815 DP83TD510E_TDR_END_TAP_INDEX_1_DEF) | 816 FIELD_PREP(DP83TD510E_TDR_START_TAP_INDEX_1, 817 DP83TD510E_TDR_START_TAP_INDEX_1_DEF)); 818 if (ret) 819 return ret; 820 821 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1, 822 FIELD_PREP(DP83TD510E_TDR_FLT_LOC_OFFSET_1, 823 DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF) | 824 FIELD_PREP(DP83TD510E_TDR_FLT_INIT_1, 825 DP83TD510E_TDR_FLT_INIT_1_DEF)); 826 if (ret) 827 return ret; 828 829 /* Undocumented register, from the "Application Note DP83TD510E Cable 830 * Diagnostics Toolkit revC". 831 */ 832 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E, 833 DP83TD510E_030E_VAL); 834 if (ret) 835 return ret; 836 837 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3, 838 DP83TD510E_TDR_TX_DURATION_US_DEF); 839 if (ret) 840 return ret; 841 842 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, 843 DP83TD510E_CTRL_SW_RESET); 844 if (ret) 845 return ret; 846 847 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG, 848 DP83TD510E_TDR_START); 849 } 850 851 /** 852 * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the 853 * DP83TD510 PHY. 854 * @phydev: Pointer to the phy_device structure. 855 * @finished: Pointer to a boolean that indicates whether the test is finished. 856 * 857 * The function sets the @finished flag to true if the test is complete. 858 * 859 * Returns: 0 on success or a negative error code on failure. 860 */ 861 static int dp83td510_cable_test_get_tdr_status(struct phy_device *phydev, 862 bool *finished) 863 { 864 int ret, stat; 865 866 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG); 867 if (ret < 0) 868 return ret; 869 870 if (!(ret & DP83TD510E_TDR_DONE)) 871 return 0; 872 873 if (!(ret & DP83TD510E_TDR_FAIL)) { 874 int location; 875 876 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 877 DP83TD510E_TDR_FAULT_STAT); 878 if (ret < 0) 879 return ret; 880 881 if (ret & DP83TD510E_TDR_PEAK_DETECT) { 882 if (ret & DP83TD510E_TDR_PEAK_SIGN) 883 stat = ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 884 else 885 stat = ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 886 887 location = FIELD_GET(DP83TD510E_TDR_PEAK_LOCATION, 888 ret) * 100; 889 ethnl_cable_test_fault_length(phydev, 890 ETHTOOL_A_CABLE_PAIR_A, 891 location); 892 } else { 893 stat = ETHTOOL_A_CABLE_RESULT_CODE_OK; 894 } 895 } else { 896 /* Most probably we have active link partner */ 897 stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 898 } 899 900 *finished = true; 901 902 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat); 903 904 return phy_init_hw(phydev); 905 } 906 907 /** 908 * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the 909 * DP83TD510 PHY. 910 * @phydev: Pointer to the phy_device structure. 911 * @finished: Pointer to a boolean that indicates whether the test is finished. 912 * 913 * The function sets the @finished flag to true if the test is complete. 914 * The function reads the cable length and reports it to the user. 915 * 916 * Returns: 0 on success or a negative error code on failure. 917 */ 918 static int dp83td510_cable_test_get_alcd_status(struct phy_device *phydev, 919 bool *finished) 920 { 921 unsigned int location; 922 int ret, phy_sts; 923 924 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS); 925 926 if (!(phy_sts & DP83TD510E_LINK_STATUS)) { 927 /* If the link is down, we can't do any thing usable now */ 928 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A, 929 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC, 930 ETHTOOL_A_CABLE_INF_SRC_ALCD); 931 *finished = true; 932 return 0; 933 } 934 935 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_ALCD_STAT); 936 if (ret < 0) 937 return ret; 938 939 if (!(ret & DP83TD510E_ALCD_COMPLETE)) 940 return 0; 941 942 location = FIELD_GET(DP83TD510E_ALCD_CABLE_LENGTH, ret) * 100; 943 944 ethnl_cable_test_fault_length_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A, 945 location, 946 ETHTOOL_A_CABLE_INF_SRC_ALCD); 947 948 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A, 949 ETHTOOL_A_CABLE_RESULT_CODE_OK, 950 ETHTOOL_A_CABLE_INF_SRC_ALCD); 951 *finished = true; 952 953 return 0; 954 } 955 956 /** 957 * dp83td510_cable_test_get_status - Get the status of the cable test for the 958 * DP83TD510 PHY. 959 * @phydev: Pointer to the phy_device structure. 960 * @finished: Pointer to a boolean that indicates whether the test is finished. 961 * 962 * The function sets the @finished flag to true if the test is complete. 963 * 964 * Returns: 0 on success or a negative error code on failure. 965 */ 966 static int dp83td510_cable_test_get_status(struct phy_device *phydev, 967 bool *finished) 968 { 969 struct dp83td510_priv *priv = phydev->priv; 970 *finished = false; 971 972 if (priv->alcd_test_active) 973 return dp83td510_cable_test_get_alcd_status(phydev, finished); 974 975 return dp83td510_cable_test_get_tdr_status(phydev, finished); 976 } 977 978 static int dp83td510_get_features(struct phy_device *phydev) 979 { 980 /* This PHY can't respond on MDIO bus if no RMII clock is enabled. 981 * In case RMII mode is used (most meaningful mode for this PHY) and 982 * the PHY do not have own XTAL, and CLK providing MAC is not probed, 983 * we won't be able to read all needed ability registers. 984 * So provide it manually. 985 */ 986 987 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 988 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported); 989 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); 990 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 991 phydev->supported); 992 993 return 0; 994 } 995 996 static int dp83td510_probe(struct phy_device *phydev) 997 { 998 struct device *dev = &phydev->mdio.dev; 999 struct dp83td510_priv *priv; 1000 1001 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1002 if (!priv) 1003 return -ENOMEM; 1004 1005 phydev->priv = priv; 1006 1007 return 0; 1008 } 1009 1010 static struct phy_driver dp83td510_driver[] = { 1011 { 1012 PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID), 1013 .name = "TI DP83TD510E", 1014 1015 .flags = PHY_POLL_CABLE_TEST, 1016 .config_init = dp83td510_config_init, 1017 .probe = dp83td510_probe, 1018 .config_aneg = dp83td510_config_aneg, 1019 .read_status = dp83td510_read_status, 1020 .get_features = dp83td510_get_features, 1021 .config_intr = dp83td510_config_intr, 1022 .handle_interrupt = dp83td510_handle_interrupt, 1023 .get_sqi = dp83td510_get_sqi, 1024 .get_sqi_max = dp83td510_get_sqi_max, 1025 .cable_test_start = dp83td510_cable_test_start, 1026 .cable_test_get_status = dp83td510_cable_test_get_status, 1027 .get_phy_stats = dp83td510_get_phy_stats, 1028 .update_stats = dp83td510_update_stats, 1029 1030 .get_mse_capability = dp83td510_get_mse_capability, 1031 .get_mse_snapshot = dp83td510_get_mse_snapshot, 1032 1033 .led_brightness_set = dp83td510_led_brightness_set, 1034 .led_hw_is_supported = dp83td510_led_hw_is_supported, 1035 .led_hw_control_set = dp83td510_led_hw_control_set, 1036 .led_hw_control_get = dp83td510_led_hw_control_get, 1037 .led_polarity_set = dp83td510_led_polarity_set, 1038 1039 .suspend = genphy_suspend, 1040 .resume = genphy_resume, 1041 } }; 1042 module_phy_driver(dp83td510_driver); 1043 1044 static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = { 1045 { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) }, 1046 { } 1047 }; 1048 MODULE_DEVICE_TABLE(mdio, dp83td510_tbl); 1049 1050 MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver"); 1051 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>"); 1052 MODULE_LICENSE("GPL v2"); 1053